DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see pages 7-9, filed 11/21/2025, with respect to the rejection(s) of claims 1-11 and 21-23, 25 and 26 under 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Cheng (CN 112928163 A) in view of Landru et al. (US 20110275226 A1).
The examiner acknowledges the addition of new claims 29-32
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1, 2 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng (CN 112928163 A) in view of Landru et al. (US 20110275226 A1).
Regarding claim 1, Cheng discloses a method, comprising: forming a fin (110) having a sidewall; (Fig. 5) forming an additional layer of fin material (120) over the sidewall wherein the additional layer (12) has an initial thickness greater than the desired thickness; (Fig. 6)
(“In this embodiment, the plasma enhanced atomic layer deposition (Plasma enhanced atomic layer deposition, PEALD) process is used to form the buffer layer 120.”
“ the deposited film can reach the thickness of the single layer atom, because the atomic layer deposition process can accurately deposit one atomic layer in each period”
“when forming the buffer layer 120 needs to use larger output power, the flow of the oxygen-containing gas is large, which is easy to cause the buffer layer 120 to the fin 110 generates a larger consumption”)
reducing the initial thickness of the additional layer of fin (120) material through controlled oxidation to form a fin structure with the desired thickness (“by the oxygen-containing gas atmosphere, the buffer layer 120 for plasma processing 130, the plasma processing 130 can generate oxygen ions, the buffer layer 120 in the side product of the key breaking; and removing some impurity ions in the buffer layer 120, making the film quality of the buffer layer 120 close to the thin film formed by the thermal oxidation growth process,” suggesting that the initial thickness is reduced due to an oxidation process.)
Furthermore, Landru discloses:
“In the area of structures of semiconductor-on-insulator type (SOI) it is known to apply thermal treatment to cause diffusion of at least part of the oxygen from the buried oxide layer through the thin semiconductor layer, so as to reduce or eliminate the thickness of this oxide layer.” (In [0002])
Therefore it would have been obvious to one skilled in the art before the effective filing date to use the teachings of Cheng and Landru for reducing the initial thickness of the additional layer of fin material through controlled oxidation to form a fin structure with the desired thickness in order “to dissolve the oxide layer--in whole or in part--in determined regions of the SOI structure, corresponding to a desired pattern, whilst preserving the initial oxide layer in the other regions.” (Landru, [0003])
Regarding claim 2, Cheng discloses the method of claim 1, wherein: the fin (110) comprises silicon or comprises a first portion of silicon and a second portion of silicon germanium; (“In this embodiment, the material of the fin 110 is the same as the material of the substrate 100, the material of the fin 110 is silicon. In other embodiments, the material of the fin may also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium arsenide and so on suitable for forming a fin of the semiconductor material, the material of the fin can be different from the material of the substrate.”)
and the additional layer of fin material comprises silicon. (“the material of the buffer layer 120 comprises silicon oxide”)
Regarding claim 4, Cheng discloses the method of claim 3, wherein: the fin (110) comprises silicon or comprises a first portion of silicon and a second portion of silicon germanium the additional layer of fin material comprises silicon; (“In this embodiment, the material of the fin 110 is the same as the material of the substrate 100, the material of the fin 110 is silicon. In other embodiments, the material of the fin may also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium arsenide and so on suitable for forming a fin of the semiconductor material, the material of the fin can be different from the material of the substrate.”) and
the second layer (140) comprises silicon oxide (“the sacrificial layer 140 is made of silicon, so that the subsequent formed oxide layer is made of silicon oxide,”)
Claims 3, 5, 6, 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng (CN 112928163 A) in view of Landru et al. (US 20110275226 A1) and further in view of Wang et al. (US 20190067283 A1).
Regarding claim 3, Cheng an discloses the method of claim 1, wherein reducing the initial thickness of the additional layer of fin material (“by the oxygen-containing gas atmosphere, the buffer layer 120 for plasma processing 130, the plasma processing 130 can generate oxygen ions, the buffer layer 120 in the side product of the key breaking; and removing some impurity ions in the buffer layer 120, making the film quality of the buffer layer 120 close to the thin film formed by the thermal oxidation growth process,” suggesting that the initial thickness is reduced due to the thermal oxidation process.)
the additional layer of fin material (120) to form a fin structure (110) with the desired thickness comprises: forming a second layer (140) over the additional layer of fin material (120). (Fig. 8)
Furthermore, Landru discloses:
“In the area of structures of semiconductor-on-insulator type (SOI) it is known to apply thermal treatment to cause diffusion of at least part of the oxygen from the buried oxide layer through the thin semiconductor layer, so as to reduce or eliminate the thickness of this oxide layer.” (In [0002])
Therefore it would have been obvious to one skilled in the art before the effective filing date to use the teachings of Cheng and Landru for reducing the initial thickness of the additional layer of fin material through controlled oxidation to form a fin structure with the desired thickness in order “to dissolve the oxide layer--in whole or in part--in determined regions of the SOI structure, corresponding to a desired pattern, whilst preserving the initial oxide layer in the other regions.” (Landru, [0003])
Cheng in view of Landru do not disclose;
And performing a thermal anneal process to reduce the initial thickness of the additional layer of fin material.
However, Wang discloses:
performing a thermal anneal process(process 364) to reduce the initial thickness of the additional layer of fin material (280).
performing the thermal anneal process comprises consuming silicon at the interface and growing silicon oxide at the interface ([0030]-[0031], Fig. 10)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Cheng, Landru and Wang for performing a thermal anneal process to reduce the initial thickness of the additional layer of fin material in order to “reduce or prevent oxidization of the fin structure.” (Wang, [0024])
Regarding claim 5, Cheng discloses the method of claim 3, wherein: the second layer (140) contacts the additional layer of fin material (120) at an interface; (Fig. 8)
Cheng does not disclose:
and performing the thermal anneal process comprises consuming silicon at the interface and growing silicon oxide at the interface.
However, Wang discloses:
performing the thermal anneal process (process 364) comprises consuming silicon at the interface and growing silicon oxide at the interface ([0031], Fig. 10)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Cheng, Landru and Wang for performing the thermal anneal process comprises consuming silicon at the interface and growing silicon oxide at the interface in order to “reduce or prevent oxidization of the fin structure.” (Wang, [0024])
Regarding claim 6, Cheng discloses the method of claim 3, wherein: the second layer (140) comprises silicon oxide (per [0024]) (“the sacrificial layer 140 is made of silicon, so that the subsequent formed oxide layer is made of silicon oxide,”);
Cheng does not disclose
and performing the thermal anneal process comprises repairing sub-oxide in the second layer.
However, Wang discloses
and performing the thermal anneal process (process 364) comprises repairing sub-oxide in the second layer (282). ([0031], Fig. 10)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Cheng, Landru and Wang for performing the thermal anneal process comprises repairing sub-oxide in the second layer in order to “reduce or prevent oxidization of the fin structure.” (Wang, [0024])
Regarding claim 10, Cheng discloses the method of claim 3, further comprising: determining a desired adjustment to the thickness of the additional layer of fin material (120); (“by the oxygen-containing gas atmosphere, the buffer layer 120 for plasma processing 130, the plasma processing 130 can generate oxygen ions, the buffer layer 120 in the side product of the key breaking; and removing some impurity ions in the buffer layer 120, making the film quality of the buffer layer 120 close to the thin film formed by the thermal oxidation growth process,” suggesting that the initial thickness is reduced due to the thermal oxidation process.)
Cheng does not explicitly disclose:
and performing the thermal anneal process for a duration of time effective to obtain the desired adjustment to the thickness of the additional layer of fin material.
However, Wang does disclose:
and performing the thermal anneal process (366) for a duration of time (“for a duration of about two hours to about three hours” per [0030] since this anneal process is performed under the same conditions as the anneal process 364 per [0033])) effective to obtain the desired adjustment to the thickness of the additional layer of fin material (280). (notice after the anneal process is done is Fig. 12 this removes a partial thickness of 280 shown in Wang, Fig. 13)
Therefore, it would have been obvious to one skilled in the art before the effective filing date to use the teachings of Cheng and Wang to perform the thermal anneal process for a duration of time effective to obtain the desired adjustment to the thickness of the additional layer of fin material so that “may be free from the problems of abnormal turn-on and the short channel effect (SCE).” (Wang, [0055])
Claims 7, 9 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng (CN 112928163 A) as applied to claim 3 above, and further in view of Lo et al. (US 20170077286 A1).
Regarding claim 7, Cheng discloses the method of claim 3, wherein: the second layer (140) comprises silicon oxide (“the sacrificial layer 140 is made of silicon, so that the subsequent formed oxide layer is made of silicon oxide,”);
Cheng does not disclose
and performing the thermal anneal process comprises densifying the silicon oxide.
However, Lo discloses:
“flowable silicon oxide materials are formed in a multiple-operation process. After the flowable film is deposited, it is cured and then annealed to remove un-desired element(s) to form silicon oxide. When the un-desired element(s) is removed, the flowable film densifies and shrinks.”
Therefore, it would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Cheng and Lo for performing the thermal anneal process comprises densifying the silicon oxide in order to “prevent an underlying layer from oxidizing.” (Lo, [0033])
Regarding claim 9, Cheng discloses the method of claim 3. Cheng does not disclose further comprising removing the second layer from an upper portion of the fin structure, wherein the second layer remains laterally adjacent to a lower portion of the fin structure.
However, Lo discloses:
removing the second layer (150) from an upper portion of the fin structure (210), wherein the second layer (150) remains laterally adjacent to a lower portion of the fin structure (210). ([0043], Fig. 9)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Cheng and Lo for removing the second layer from an upper portion of the fin structure, wherein the second layer remains laterally adjacent to a lower portion of the fin structure in order to in order to “it is possible to control the width of the fin structure for the n-channel and p-channel Fin FET more precisely due to less damage in the hard mask patterns.” (Lo, [0082])
Regarding claim 11, Lo discloses the method of claim 3, wherein the second layer (150) is formed with different thicknesses (annotated below) at different regions (bottom/sides)
Lo does not explicitly disclose:
such that the thermal anneal process selectively reduces the thickness of the additional layer of fin material.
However, Lo does disclose:
“flowable silicon oxide materials are formed in a multiple-operation process. After the flowable film is deposited, it is cured and then annealed to remove un-desired element(s) to form silicon oxide. When the un-desired element(s) is removed, the flowable film densifies and shrinks.”
Therefore, it would have been obvious to one skilled in the art before the effective filing date to use the teachings of Lo for the thermal anneal process selectively reduces the thickness of the additional layer of fin material in order to “ prevent an underlying layer from oxidizing”. (Lo, [0033])
Claims 21 is rejected under 35 U.S.C. 103 as being unpatentable over Cheng (CN 112928163 A) in view of Landru et al. (US 20110275226 A1).
Regarding claim 21, Cheng discloses a method, comprising: forming a semiconductor structure (11) having a sidewall; (Fig. 10)
forming an additional layer of semiconductor material (120) over the sidewall, (Fig. 6)
wherein the additional layer (120) has an initial thickness; (Fig. 6) and
adjusting the initial thickness ((“by the oxygen-containing gas atmosphere, the buffer layer 120 for plasma processing 130, the plasma processing 130 can generate oxygen ions, the buffer layer 120 in the side product of the key breaking; and removing some impurity ions in the buffer layer 120, making the film quality of the buffer layer 120 close to the thin film formed by the thermal oxidation growth process,” suggesting that the initial thickness is reduced due to an oxidation process.) of the additional layer of semiconductor material (120) to form a combined structure (fig. 6) with a desired thickness,
Cheng does not explicitly disclose:
adjusting the thickness of the additional layer of semiconductor material comprises: determining an amount of the additional layer to be consumed; and performing a controlled oxidation for a duration selected based on the amount of the additional layer to be consumed.
However, Landru discloses:
“[0002] In the area of structures of semiconductor-on-insulator type (SOI) it is known to apply thermal treatment to cause diffusion of at least part of the oxygen from the buried oxide layer through the thin semiconductor layer, so as to reduce or eliminate the thickness of this oxide layer.
[0003] This dissolution step can be applied to the entire structure, or it can be applied locally i.e. to dissolve the oxide layer--in whole or in part--in determined regions of the SOI structure, corresponding to a desired pattern, whilst preserving the initial oxide layer in the other regions. This is termed "local dissolution" of the oxide layer.”
Therefore it would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Cheng and Landru for adjusting the thickness of the additional layer of semiconductor material comprises: determining an amount of the additional layer to be consumed; and performing a controlled oxidation for a duration selected based on the amount of the additional layer to be consumed in order “to dissolve the oxide layer--in whole or in part--in determined regions of the SOI structure, corresponding to a desired pattern, whilst preserving the initial oxide layer in the other regions.” (Landru, [0003])
Claims 22, 23, 25 and 26 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng (CN 112928163 A) in view of Landru et al. (US 20110275226 A1) as applied to claim 21 above and further in view of Wang et al. (US 20190067283 A1).
Regarding claim 22, Cheng discloses the method of claim 21, performing controlled oxidation (“thermal oxidation process”)
Cheng does not disclose:
performing a thermal anneal process with a gas composition including oxygen and nitrogen to oxidize a portion of the additional layer.
However, Wang discloses:
performing a thermal anneal process (364) with a gas composition including oxygen and nitrogen to oxidize a portion of the additional layer (282A). ([0030]-[0031], Fig. 10)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Cheng and Wang for performing a thermal anneal process with a gas composition including oxygen and nitrogen to oxidize a portion of the additional layer in order for “the top portion 282A of the liner layer 282 is oxidized more than a bottom portion 282B of the liner layer 282,” (Wang, [0031]).
Regarding claim 23, Cheng discloses the method of claim 21, further comprising, after adjusting the thickness of the additional layer (120), (“by the oxygen-containing gas atmosphere, the buffer layer 120 for plasma processing 130, the plasma processing 130 can generate oxygen ions, the buffer layer 120 in the side product of the key breaking; and removing some impurity ions in the buffer layer 120, making the film quality of the buffer layer 120 close to the thin film formed by the thermal oxidation growth process,”)
Cheng does not disclose:
depositing an insulation material over the combined structure to form a shallow trench isolation feature.
However, Wang discloses:
depositing an insulation material (226) over the fin structure (210) to form a shallow trench isolation feature (per [0035]). (Fig. 10)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Cheng and Wang for depositing an insulation material over the combined structure to form a shallow trench isolation feature in order to “form isolation regions 206 such as shallow trench isolation (STI) regions, in the first region 350A and the second region 350B”, (Wang, [0035])
Regarding claim 25, Cheng discloses the method of claim 21, wherein adjusting the thickness of the additional layer of fin material (“by the oxygen-containing gas atmosphere, the buffer layer 120 for plasma processing 130, the plasma processing 130 can generate oxygen ions, the buffer layer 120 in the side product of the key breaking; and removing some impurity ions in the buffer layer 120, making the film quality of the buffer layer 120 close to the thin film formed by the thermal oxidation growth process,” suggesting that the initial thickness is reduced due to an oxidation process) comprises: forming a second layer (140) over the additional layer (120) using a plasma-enhanced atomic layer deposition process
Cheng does not explicitly disclose:
performing a thermal anneal process to reduce the thickness of the additional layer.
However, Wang discloses:
performing a thermal anneal process (364) to reduce the thickness of the additional layer (282A). ([0030]-[0031], Fig. 10)
Therefore, it would have been obvious to one skilled in the art before the effective filing date to use the teachings of Cheng and Wang to perform a thermal anneal process to reduce the thickness of the additional layer in order to “convert into an oxide of a material of the liner layer 282.” (Wang, [0031])
Regarding claim 26, Cheng discloses the method of claim 21 further comprising, after adjusting the thickness of the additional layer, (“by the oxygen-containing gas atmosphere, the buffer layer 120 for plasma processing 130, the plasma processing 130 can generate oxygen ions, the buffer layer 120 in the side product of the key breaking; and removing some impurity ions in the buffer layer 120, making the film quality of the buffer layer 120 close to the thin film formed by the thermal oxidation growth process,” suggesting that the initial thickness is adjusted due to an oxidation process.)
Cheng does not disclose:
performing a chemical mechanical planarization process to planarize a top surface of the combined structure.
However, Wang discloses:
performing a chemical mechanical planarization process (per [0032]) to planarize a top surface of the combined structure (600). ([0032], Fig. 11)
It would have been obvious to ones killed in the art before the effective filing date to combine the teachings of Cheng and Wang for performing a chemical mechanical planarization process to planarize a top surface of the combined structure so that “the liner layer 282 in the first region 350A and a top surface 217 of the patterned mask 210 in the second region 350B is exposed. “ (Wang, [0032])
Claims 29, 31, and 32 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng (CN 112928163 A) in view of Lo et al (US 20170077286 A1) and Landru et al. (US 20110275226 A1).
Regarding claim 29, Cheng discloses a method, comprising: forming a semiconductor device element (110) having a sidewall; (Fig. 5)
forming an additional layer of material (120) over the element (110); (Fig. 6)
forming a second layer (140) over the additional layer (120)
Cheng does not disclose wherein
the second layer has a thin portion with a first initial thickness and a thick portion with a second initial thickness greater than the first initial thickness;
However, Lo discloses:
the second layer (282A) has a thin portion (sides) with a first initial thickness and a thick portion (bottom) with a second initial thickness greater than the first initial thickness; (Fig. 6)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Cheng and Lo for the second layer has a thin portion with a first initial thickness and a thick portion with a second initial thickness greater than the first initial thickness because this is an expected result of the manufacturing process.
Cheng in view of Lo do not disclose:
and performing a process to reduce a thickness differential between the thin portion and the thick portion.
However, Landru discloses:
“[0002] In the area of structures of semiconductor-on-insulator type (SOI) it is known to apply thermal treatment to cause diffusion of at least part of the oxygen from the buried oxide layer through the thin semiconductor layer, so as to reduce or eliminate the thickness of this oxide layer.
[0003] This dissolution step can be applied to the entire structure, or it can be applied locally i.e. to dissolve the oxide layer--in whole or in part--in determined regions of the SOI structure, corresponding to a desired pattern, whilst preserving the initial oxide layer in the other regions. This is termed "local dissolution" of the oxide layer.”
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Cheng, Lo and Landru for performing a process to reduce a thickness differential between the thin portion and the thick portion in order to “ to dissolve the oxide layer--in whole or in part--in determined regions of the SOI structure, corresponding to a desired pattern, whilst preserving the initial oxide layer in the other regions.” (Landru, [0003])
Regarding claim 31, Landru discloses the method of claim 29. Landru does not explicitly disclose wherein the process further comprises thinning the additional layer of material to a reduced thickness.
However, Landru discloses:
“[0002] In the area of structures of semiconductor-on-insulator type (SOI) it is known to apply thermal treatment to cause diffusion of at least part of the oxygen from the buried oxide layer through the thin semiconductor layer, so as to reduce or eliminate the thickness of this oxide layer.
[0003] This dissolution step can be applied to the entire structure, or it can be applied locally i.e. to dissolve the oxide layer--in whole or in part--in determined regions of the SOI structure, corresponding to a desired pattern, whilst preserving the initial oxide layer in the other regions. This is termed "local dissolution" of the oxide layer.”
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Cheng, Lo and Landru for the process further comprises thinning the additional layer of material to a reduced thickness in order to “ to dissolve the oxide layer--in whole or in part--in determined regions of the SOI structure, corresponding to a desired pattern, whilst preserving the initial oxide layer in the other regions.” (Landru, [0003])
Regarding claim 32, Cheng discloses the method of claim 29, wherein: the semiconductor device element (110) is a semiconductor fin (110) comprising silicon or comprising a first portion of silicon and a second portion of silicon germanium; (“In this embodiment, the material of the fin 110 is the same as the material of the substrate 100, the material of the fin 110 is silicon. In other embodiments, the material of the fin may also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium arsenide and so on suitable for forming a fin of the semiconductor material, the material of the fin can be different from the material of the substrate.”)
the additional layer of material (120) comprises (at least) silicon (“he material of the buffer layer 120 comprises silicon oxide.”); and
the second layer (140) comprises oxide (“ the sacrificial layer 140 is made of silicon, so that the subsequent formed oxide layer is made of silicon oxide”).
Allowable Subject Matter
Claims 8 and 30 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ASHLEY BLACKWELL whose telephone number is (703)756-1508. The examiner can normally be reached Mon-Fri 8:00-1600.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469-295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ASHLEY NICOLE BLACKWELL/ Examiner, Art Unit 2897
/JACOB Y CHOI/ Supervisory Patent Examiner, Art Unit 2897