DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on April 10, 2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3 and 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over JP 2020-031174 A to Matsubara et al. (hereinafter “Matsubara” – previously cited reference) in further view of JPH 11-8213 A to Okita et al. (hereinafter “Osawa” – previously cited reference).
Regarding claim 1, Matsubara discloses a method of manufacturing chips with laminated die-attach layers (manufacturing method for chips with die attach DA layers 30; abstract; Figs. 1 and 4; paragraph [0028]), comprising:
a preparing step of preparing a wafer unit in which a wafer having a plurality of devices formed in respective areas demarcated on a face side thereof by a plurality of intersecting projected dicing lines established thereon (preparing substrate 10 having plurality of element chips formed on face side in areas separated by regions R2 to be plasma diced; Fig. 1; paragraphs [0010]-[0011]) is affixed to a tape with a die-attach layer being interposed therebetween, the die-attach layer including fillers (substrate 10 attached to adhesive holding sheet 22 with DA Layer 30 disposed therebetween; Fig. 4; paragraphs [0020], [0026]), and the devices are protected by a protective member and the face side of the wafer is exposed along the projected dicing lines (chips have protective film 40 disposed thereover on face side in R1 region but not in plasma dicing region R2 where substrate 10 is exposed; Fig. 7; paragraphs [0010]-[0011], [0033], [0035]);
a wafer processing step of supplying a first gas to the wafer unit and performing plasma etching on the wafer from the face side thereof to form grooves which extend through an entirety of the wafer, such that the grooves divide the wafer and expose the die-attach layer along the projected dicing lines (plasma dicing step where substrate 10 is etched on face side with sulfur hexafluoride gas entirely therethrough only in region R2 down to the DA layer 30 which is thereby exposed in R2; Fig. 9; paragraph [0048]);
after the wafer processing step, a die-attach layer processing step of supplying a second gas to the wafer unit and performing plasma etching on the die-attach layer from the face side of the wafer to extend the grooves formed in the wafer through the entirety of the die-attach layer (DA layer 30 is thereafter plasma etched entirely away on face side using gas containing oxygen and fluorine in the region R2; Fig. 10; paragraphs [0060]-[0061], [0065]); and
after the die-attach layer processing step, a cleaning step of: positioning a nozzle which ejects a cleaning fluid directly above or directly below the grooves formed in the wafer (gas inlet 103 ejects carbon tetrafluoride and oxygen into the vertical grooves formed in region R2 in substrate 10; Fig. 8; paragraphs [0065]-[0066]), and
ejecting the cleaning fluid, via the nozzle, along the grooves formed in the wafer and into the grooves toward a bottom of the grooves formed in the face side of the wafer to remove filler residuals that have remained in the grooves in the die-attach layer processing step from the wafer unit (after DA layer 30 etching, carbon tetrafluoride and oxygen may be applied via gas inlet 103a to entire face side of substrate 10 and in grooves of region R2 which is capable of removing inorganic filler of any residual DA layer 30 material; Fig. 8; paragraphs [0065]-[0066]).
Matsubara fails to disclose after the die-attach layer processing step, a cleaning step of: positioning a nozzle which ejects a cleaning fluid directly above or directly below the grooves formed in the wafer by moving the nozzle to a position directly above or directly below the grooves, and ejecting the cleaning fluid, via the nozzle, along the grooves formed in the wafer and into the grooves toward a bottom of the grooves formed in the face side of the wafer to remove filler residuals that have remained in the grooves in the die-attach layer processing step from the wafer unit while moving the wafer and the nozzle relative to one another.
However, Osawa discloses a cleaning step of: positioning a nozzle which ejects a cleaning fluid directly above or directly below the grooves formed in the wafer by moving the nozzle to a position directly above or directly below the grooves (fluid supply nozzle 6 is moved across a cleaning surface 5 of a semiconductor wafer 3 having a fine pattern of grooves with a high aspect ratio in order to clean the fine pattern; Figs. 1a and 4; paragraphs [0006], [0043]), and ejecting the cleaning fluid, via the nozzle, along the grooves formed in the wafer and into the grooves toward a bottom of the grooves formed in the face side of the wafer to remove filler residuals that have remained in the grooves in the die-attach layer processing step from the wafer unit while moving the wafer and the nozzle relative to one another (fluid supply nozzle 6 ejects water towards bottom of fine pattern of grooves formed in the top side of the wafer 3 to remove a silicon oxide film debris from grooves while nozzle 6 moves relative the wafer 3 along the grooves; Figs. 1a and 4; paragraphs [0033], [0037]).
Matsubara and Osawa are considered to be analogous to the claimed invention because they are in the same field of semiconductor wafer fabrication processes. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Matsubara to incorporate the teachings of Osawa in order to provide cleaner dicing grooves which reduce defects like incomplete cuts or die chipping thereby providing higher yield and increased end-product reliability.
Regarding claim 3, Matsubara in view of Osawa discloses the method of manufacturing chips according to claim 1. Matsubara further discloses wherein the cleaning step includes the step of ejecting the cleaning fluid to the face side of the wafer while the face side of the wafer is facing downwardly (carbon tetrafluoride and oxygen may be applied to entire face side of substrate 10 when in a given orientation; Matsubara paragraphs [0065]-[0066]).
Regarding claim 5, Matsubara in view of Osawa discloses the method of manufacturing chips according to claim 1. Matsubara further discloses wherein the cleaning fluid is a cleaning liquid (washing fluid may be water; paragraph [0067]).
Regarding claim 6, Matsubara in view of Osawa discloses the method of manufacturing chips according to claim 5. Matsubara further discloses wherein the cleaning liquid is water (washing fluid may be water; paragraph [0067]).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Matsubara as modified by Osawa in further view of US 2012/0322238 A1 to Lei et al. (hereinafter “Lei” – previously cited reference).
Regarding claim 4, Matsubara in view of Osawa discloses method of manufacturing chips according to claim 1. Matsubara fails to disclose wherein the die-attach layer includes an acrylic resin or an epoxy resin.
However, Lei discloses wherein the die-attach layer includes an acrylic resin or an epoxy resin (water-soluble die attach film 408 is composed of polyacrylic acid; paragraph [0045]).
Matsubara and Lei are considered to be analogous to the claimed invention because they are in the same field of semiconductor wafer fabrication processes. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Matsubara to incorporate the teachings of Lei in order to provide strong adhesion, high mechanical strength, thermal stability, and low thermal expansion.
Response to Arguments
Applicant's arguments filed March 27, 2026 have been fully considered. Applicant presents amendments to claim 1 and arguments related thereto. Applicant first asserts that Matsubara teaches away from removing the inorganic filler of any residual DA layer 30 material from the grooves. However, claim 1 recites the functional language “to remove filler residuals that have remained in the grooves in the die-attach layer processing step from the wafer unit” which is met by Matsubara in that carbon tetrafluoride and oxygen may be applied via gas inlet 103a to entire face side of substrate 10 and in grooves of region R2 which is capable of removing inorganic filler of any residual DA layer 30 material (see Fig. 8 and paragraphs [0065]-[0066]). Therefore, while Matsubara teaches the content Applicant cites in paragraph [0061], this doesn’t mean Matsubara is incapable of removing inorganic filler of any residual DA layer 30 material via the fluid supplied by gas inlet 103a. Applicant next asserts that Osawa fails to disclose “wafer-dividing dicing-line grooves produced to expose and then etch a die-attach layer including fillers” and “the post die-attach layer etch removal of filler residuals remaining in the wafer-dividing grooves by ejecting cleaning fluid along the grooves and into the grooves toward their bottoms while moving the wafer and nozzle relative to one another” but these limitations are not used in the current 35 USC 103 rejection as modifying Matsubara with Osawa. Rather, given the current language of claim 1, Matsubara only fails to disclose moving the nozzle to a position directly above or directly below the grooves and moving the wafer and the nozzle relative to one another, but this content is disclosed by Osawa and is used to modify Matsubara. Applicant may take issue with the context of the grooves formed by Osawa, but Applicant does not dispute that Osawa discloses the cleaning of grooves on a wafer using a fluid-ejecting nozzle that moves along the grooves and relative the wafer. Therefore, the combination of Matsubara with Osawa discloses amended claim 1.
Conclusion
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/IAN DEGRASSE/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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