DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment/Argument
Applicant’s arguments, see remarks, filed 12/08/2025, with respect to the rejection(s) of claim(s) 1-13 and 21-27 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of an updated prior art search.
Claim Objections
Claim 21 is objected to because of the following informalities: “an electrical connector extending through the layer of molding compound and the third dielectric layer to connect to the first metal pad” should say “an electrical connector extending through the layer of molding compound and the third dielectric layer to connect to the second metal pad”. The drawings depict connectors 152 contacting the second metal pad 110 which is above the first metal pad 109. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1 and 7-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (US-20210098421-A1 – hereinafter Wu) in view of Iwashita et al. (US-20230307396-A1 – hereinafter Iwashita).
Regarding claim 1, Wu teaches a semiconductor package (Fig.3; ¶0054) comprising:
one or more integrated circuit dies (Fig.3 130; ¶0027);
a back-side redistribution structure (Fig.3 150; ¶0033) on a back-side (top side) of the one or more integrated circuit dies (130), the back-side redistribution structure (150) comprising:
a first dielectric layer (Fig.1D 154 bottom; ¶0033);
a first metal pattern (Fig.1D 152 middle; ¶0033) in the first dielectric layer (154 bottom), wherein a first portion of the first metal pattern (152 middle) is a metal pad (¶0033);
a second dielectric layer (Fig.1D 154 middle; ¶0033) over the first metal pattern (152 middle); and
a second metal pattern (Fig.1D 152 top; ¶0033) in the second dielectric layer (154 middle), wherein the first portion of the first metal pattern (152 middle) is connected to the first portion of the second metal pattern (152 top) by one or more metal vias (metal vias connecting these metal patterns are shown in Fig.3) extending through the second dielectric layer (154 middle); and
a third dielectric layer (Fig.1D 154 top; ¶0033) over the second metal pattern (152 top);
a front-side redistribution structure (Fig.3 110; ¶0020) on the front-side (bottom side) of the one or more integrated circuit dies (130):
an encapsulant (Fig.3 140; ¶0031) surrounding the one or more integrated circuit dies (130): and
one or more through vias (Fig.3 120; ¶0025) extending through the encapsulant (140) and electrically connecting the back-side redistribution structure (150) to the front-side redistribution structure (110).
Wu does not teach wherein a first portion of the second metal pattern is a dummy pad, and wherein the first portion of the first metal pattern, the first portion of the second metal pattern, and the one or more metal vias are electrically isolated from remaining portions of the back-side redistribution structure.
Iwashita teaches interconnection structures (Fig.7 41-43; ¶0054 of Iwashita) having dummy pads (Fig.7 41A; ¶0056 of Iwashita), metal pads (Fig.7 43; ¶0055 of Iwashita) and metal interconnects (Fig.7 42; ¶0054 of Iwashita) between both pads, where these interconnection structures (41-43 of Iwashita) are electrically isolated from the other circuity of the device disclosed in Iwashita (¶0053 of Iwashita).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have added the electrically isolated interconnection structures of Iwashita (41A, 42 and 43 of Iwashita) to the redistribution structures of Wu (152 top and middle of Wu) where the dummy pad (41A of Iwashita) is added to 152 top of Wu and the metal pad (43 of Iwashita) is added to 152 middle of Wu with the metal interconnect (or via, 42 of Iwashita) in-between. A practitioner would be motivated to add these features to the structure disclosed by the primary reference for the benefit of mimicking the physical properties of the non-dummy equivalent components for improved reliability.
Regarding claim 7, the aforementioned combination of Wu in view of Iwashita from claim 1 teaches the semiconductor package of claim 1, further comprising an insulating layer (Fig.3 250; ¶0055 of Wu) over the third dielectric layer (154 top of Wu) and an electrical connector (Fig.1E 208; ¶0038 of Wu) extending through the insulating layer (250 of Wu) and the third dielectric layer (154 top of Wu) to contact the first portion of the second metal pattern (152 top of Wu).
Regarding claim 8, the aforementioned combination of Wu in view of Iwashita from claim 7 teaches the semiconductor package of claim 7, wherein the insulating layer (250 of Wu) comprises a molding compound (¶0031 of Wu).
Claim(s) 21-22, 25-26 and 28 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu in view of Hsieh.
Regarding claim 21, Wu teaches a semiconductor package (Fig.3; ¶0054) comprising:
an integrated circuit die (Fig.3 130; ¶0027); and
a redistribution structure (Fig.3 150; ¶0033) over the integrated circuit die (130), the redistribution structure (150) comprising:
a first dielectric layer (Fig.1D 154 bottom; ¶0033);
a first metal pad (Fig.1D 152 middle; ¶0033) in the first dielectric layer (154 bottom);
a second dielectric layer (Fig.1D 154 middle; ¶0033) over the first metal pad (152 middle) and the first dielectric layer (154 bottom);
a second metal pad (Fig.1D 152 top; ¶0033) in the second dielectric layer (154 middle), wherein the second metal pad (152 top) overlaps the first metal pad (152 middle); and
a third dielectric layer (Fig.1D 154 top; ¶0033) over the second metal pad (152 top) and the second dielectric layer (154 middle); and
a layer of molding compound (Fig.3 250; ¶0055) over the third dielectric layer (154 top) and an electrical connector (Fig.1E 208; ¶0038) extending through the layer of molding compound (250) and the third dielectric layer (154 top) to connect to the first metal pad (152 top), the third dielectric layer (154 top) extending between the integrated circuit die (130) and the layer of molding compound (250).
Wu does not teach wherein the first metal pad comprises first openings extending through the first metal pad, and wherein the first openings are filled in by a first material of the first dielectric layer;
wherein the second metal pad comprises second openings extending through the second metal pad, and wherein the second openings are filled in by a second material of the second dielectric layer.
Hsieh teaches a redistribution layer (Fig.7 509; ¶0058 of Hsieh) with mesh holes (Fig.7 701; ¶0058 of Hsieh) that are filled with dielectric material (¶0058).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate the holes of Hsieh (701 of Hsieh) with both metal pads of Wu (152 of Wu) and to fill the holes with dielectric material from the respective dielectric layers (154 of Wu) to reduce high sidewall peeling stresses and cracks (¶0058 of Hsieh).
Regarding claim 22, the aforementioned combination of Wu in view of Hsieh from claim 21 teaches the semiconductor package of claim 21, wherein the first metal pad (152 middle of Wu) and the second metal pad (152 top of Wu) are connected by one or more metal vias (Fig.3 of Wu depicts metal vias connecting both metal layers) extending through the second dielectric layer (154 middle of Wu).
Regarding claim 25, the aforementioned combination of Wu in view of Hsieh from claim 21 teaches the semiconductor package of claim 21, wherein the first metal pad (152 middle of Wu) is disposed at a corner of the redistribution structure (150 of Wu) in a top-down view (Fig.3 of Wu any end metal pad of 152 middle could be in a corner of the structure in a top-down view).
Regarding claim 26, the aforementioned combination of Wu in view of Hsieh from claim 21 teaches the semiconductor package of claim 21.
The aforementioned combination does not teach wherein the first openings are encircled by the second openings in a top-down view.
Shape differences are considered obvious design choices and are not patentable unless unobvious or unexpected results are obtained from these changes. Additionally, the Applicant has presented no discussion in the specification which convinces the Examiner that the particular shape of the layout of the openings is anything more than one of numerous shapes a person of ordinary skill in the art would find obvious for the purpose of filling with dielectric material (In re Dailey, 149 USPQ 47 (CCPA 1976)). It appears that these changes produce no functional differences and therefore would have been obvious.
Regarding claim 28, the aforementioned combination of Wu in view of Hsieh from claim 21 teaches the semiconductor package of claim 21.
The aforementioned combination does not teach wherein the layer of molding compound is a back-side enhancement layer configured to reduce warpage of the redistribution structure, and wherein the back-side enhancement layer has a thickness of between about 25 μm and about 50 μm.
Wu teaches a back-side enhancement layer (Fig.1F 220; ¶0044 of Wu) for preventing package warpage.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the back-side enhancement layer of Fig.1F of Wu (220 of Wu) with the prior art embodiment of Fig.3 of Wu in view of Hsieh to arrive at an obvious variant of the claimed invention. A practitioner would have been motivated to make this modification for the benefit of preventing warpage of the semiconductor device (Fig.3 of Wu).
Claim(s) 2-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu in view of Iwashita, and further in view of Hsieh et al. (US-20210082845-A1 – hereinafter Hsieh).
Regarding claim 2, the aforementioned combination of Wu in view of Iwashita from claim 1 teaches the semiconductor package of claim 1.
The aforementioned combination does not teach wherein the metal pad comprises openings that extend through a thickness of the metal pad.
Hsieh teaches a redistribution layer (Fig.7 509; ¶0058 of Hsieh) with mesh holes (Fig.7 701; ¶0058 of Hsieh).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate the holes of Hsieh (701 of Hsieh) with the metal pad of Wu in view of Iwashita (a pad of 152 middle of Wu) because said holes can be filled with dielectric material to reduce high sidewall peeling stresses and cracks (¶0058 of Hsieh).
Regarding claim 3, the aforementioned combination of Wu in view of Iwashita, and further in view of Hsieh from claim 2 teaches the semiconductor package of claim 2.
The aforementioned combination does not teach wherein the openings are filled in by the first dielectric layer.
Hsieh teaches a redistribution layer (Fig.7 509; ¶0058 of Hsieh) with mesh holes (Fig.7 701; ¶0058 of Hsieh) that are filled with dielectric material (¶0058 of Hsieh).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to fill the mesh holes of Wu in view of Iwashita and further in view of Hsieh from claim 2 with dielectric material to reduce high sidewall peeling stresses and cracks (¶0058 of Hsieh).
Regarding claim 4, the aforementioned combination of Wu in view of Iwashita from claim 1 teaches the semiconductor package of claim 1.
The aforementioned combination does not teach wherein the dummy pad comprises openings that extend through a thickness of the dummy pad.
Hsieh teaches a redistribution layer (Fig.7 509; ¶0058 of Hsieh) with mesh holes (Fig.7 701; ¶0058 of Hsieh).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate the holes of Hsieh (701 of Hsieh) with the dummy pad of Wu in view of Iwashita (a pad of 152 middle of Wu) because said holes can be filled with dielectric material to reduce high sidewall peeling stresses and cracks (¶0058 of Hsieh).
Regarding claim 5, the aforementioned combination of Wu in view of Iwashita, and further in view of Hsieh from claim 4 teaches the semiconductor package of claim 4.
The aforementioned combination does not teach wherein the openings are filled in by the second dielectric layer.
Hsieh teaches a redistribution layer (Fig.7 509; ¶0058 of Hsieh) with mesh holes (Fig.7 701; ¶0058 of Hsieh) that are filled with dielectric material (¶0058 of Hsieh).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to fill the mesh holes of Wu in view of Iwashita and further in view of Hsieh from claim 4 with dielectric material to reduce high sidewall peeling stresses and cracks (¶0058 of Hsieh).
Claim(s) 6, 9 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu in view of Iwashita, and further in view of Kim et al. (US-20230019311-A1 – hereinafter Kim).
Regarding claim 6, the aforementioned combination of Wu in view of Iwashita from claim 1 teaches the semiconductor package of claim 1.
The aforementioned combination does not teach wherein the second metal pattern also comprises a power pad, a ground pad, and a signal pad.
Kim teaches redistribution structures that comprise components for power, signal and ground (¶0056 of Kim).
These components are well-known to be part of the conductive redistribution layers within redistribution structures and claiming these components does not patentably distinguish claim 6 over the art of record.
Regarding claim 9, Wu teaches a semiconductor package (Fig.3; ¶0054) comprising:
an integrated circuit die (Fig.3 130; ¶0027);
a redistribution structure (Fig.3 150; ¶0033) on a back-side (top side) of the integrated circuit die (130), the redistribution structure (150) comprising:
a first insulating layer (Fig.1D 154 bottom; ¶0033);
a first redistribution pattern (Fig.1D 152 middle; ¶0033) in the first insulating layer (154 bottom);
a second insulating layer (Fig.1D 154 middle; ¶0033) over the first redistribution pattern (152 middle); and
a second redistribution pattern (Fig.1D 152 top; ¶0033) in the second insulating layer (154 middle), wherein the second redistribution pattern (152 top) comprises a plurality of contact pads (¶0033);
a third insulating layer (Fig.1D 154 top; ¶0033) over the second redistribution pattern (152 top); and
a fourth insulating layer (Fig.1D 250; ¶0055) over the third insulating layer (154 top) and contact pad connectors (Fig.1E 208; ¶0038) extending through the third insulating layer (250) and fourth insulating layer (154 top) to contact the plurality of contact pads (¶0033), wherein the fourth insulating layer (250) comprises a molding compound (¶0031), wherein the first insulating layer (154 bottom) is between the integrated circuit die (130) and the fourth insulating layer (250).
Wu does not teach wherein the contact pads are comprising:
signal pads;
power pads;
ground pads; and
dummy pads;
wherein first portions of the first redistribution pattern are connected to the dummy pads by vias extending through the second insulating layer;
a heat dissipation system comprising:
the first portions of the first redistribution pattern;
the dummy pads; and
the vias, wherein the heat dissipation system is electrically isolated from circuits of the semiconductor package.
Iwashita teaches interconnection structures (Fig.7 41-43; ¶0054 of Iwashita) having dummy pads (Fig.7 41A; ¶0056 of Iwashita), metal pads (Fig.7 43; ¶0055 of Iwashita) and metal interconnects (Fig.7 42; ¶0054 of Iwashita) between both pads, where these interconnection structures (41-43 of Iwashita) are electrically isolated from the other circuity of the device disclosed in Iwashita (¶0053 of Iwashita).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have added the electrically isolated interconnection structures of Iwashita (41A, 42 and 43 of Iwashita) to the redistribution structures of Wu (152 middle and 152 top of Wu) where the dummy pad (41A of Iwashita) is added to 152 top of Wu and the metal pad (43 of Iwashita) is added to 152 middle of Wu with the metal interconnect (or via, 42 of Iwashita) in-between. A practitioner would be motivated to add these features to the structure disclosed by the primary reference for the benefit of mimicking the physical properties of the non-dummy equivalent components for improved reliability.
Wu in view of Iwashita does not teach wherein the contact pads are comprising:
signal pads;
power pads; and
ground pads.
Kim teaches redistribution structures that comprise components for power, signal and ground (¶0056 of Kim).
These components are well-known to be part of the conductive redistribution layers within redistribution structures and claiming these components does not patentably distinguish claim 6 over the art of record.
Regarding claim 13, the aforementioned combination of Wu in view of Iwashita, and further in view of Kim from claim 9 teaches the semiconductor package of claim 9, wherein the fourth insulating layer (250 of Wu) comprises an epoxy (¶0031 of Wu).
Claim(s) 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu in view of Hsieh, and further in view of Iwashita.
Regarding claim 23, the aforementioned combination of Wu in view of Hsieh from claim 21 teaches the semiconductor package of claim 21.
The aforementioned combination does not teach wherein the first metal pad and the second metal pad are electrically isolated from remaining conductive features of the redistribution structure.
Iwashita teaches interconnection structures (Fig.7 41-43; ¶0054 of Iwashita) having dummy pads (Fig.7 41A; ¶0056 of Iwashita), metal pads (Fig.7 43; ¶0055 of Iwashita) and metal interconnects (Fig.7 42; ¶0054 of Iwashita) between both pads, where these interconnection structures (41-43 of Iwashita) are electrically isolated from the other circuity of the device disclosed in Iwashita (¶0053 of Iwashita).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have added the electrically isolated interconnection structures of Iwashita (41A, 42 and 43 of Iwashita) to the redistribution structures of Wu (152 top and middle of Wu) where the dummy pad (41A of Iwashita) is added to 152 top of Wu and the metal pad (43 of Iwashita) is added to 152 middle of Wu with the metal interconnect (or via, 42 of Iwashita) in-between. A practitioner would be motivated to add these features to the structure disclosed by the primary reference for the benefit of mimicking the physical properties of the non-dummy equivalent components for improved reliability.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu in view of Iwashita, and further in view of Kim, and further in view of Pei et al. (US- 20190148262-A1 – hereinafter Pei).
Regarding claim 10, the aforementioned combination of Wu in view of Iwashita, and further in view of Kim from claim 9 teaches the semiconductor package of claim 9.
The aforementioned combination does not teach wherein the plurality of contact pads are disposed on the semiconductor package in an array comprising columns and rows in a top view, and wherein a center region of the array is free of contact pads.
Pei teaches a semiconductor package having contacts in columns and rows having a center region free of contact pads (Fig.12B; ¶0062 of Pei).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to apply the layout of Pei (Fig.12B of Pei) to the primary reference to save room for other components, like a thermally conductive material (¶0044).
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu in view of Iwashita, and further in view of Kim, and further in view of Park et al. (US- 20110068481-A1 – hereinafter Park).
Regarding claim 11, the aforementioned combination of Wu in view of Iwashita, and further in view of Kim from claim 9 teaches the semiconductor package of claim 9.
The aforementioned combination does not teach wherein the plurality of contact pads are disposed on the semiconductor package in an array comprising columns and rows in a top view, and wherein one or more dummy pads are disposed in a column closest to an edge of the semiconductor package.
Park teaches a semiconductor package having contact pads in an array of columns and rows where the dummy pads are closer to the edge of the semiconductor package (Fig.1D; ¶0066 of Park).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to apply this layout to the primary reference because dummy components for heat dissipation or structural support are better located near the edge to protect the components closer to the center of the package.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu in view of Iwashita, and further in view of Kim, and further in view of Hsieh.
Regarding claim 12, the aforementioned combination of Wu in view of Iwashita, and further in view of Kim from claim 9 teaches the semiconductor package of claim 9.
The aforementioned combination does not teach wherein the dummy pads have openings that extend from top surfaces of the dummy pads to bottom surfaces of the dummy pads.
Hsieh teaches a redistribution layer (Fig.7 509; ¶0058) with mesh holes (Fig.7 701; ¶0058).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate the holes of Hsieh (701 of Hsieh) with the dummy pad of Wu in view of Iwashita (a pad of 152 top of Wu) because said holes can be filled with dielectric material to reduce high sidewall peeling stresses and cracks (¶0058 of Hsieh).
Claim(s) 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu in view of Hsieh, and further in view of Iwashita, and further in view of Kim.
Regarding claim 24, the aforementioned combination of Wu in view of Hsieh, and further in view of Iwashita from claim 23 teaches the semiconductor package of claim 23.
The aforementioned combination does not teach wherein the remaining conductive features of the redistribution structure comprise a power pad, a ground pad (Fig.3A 110B), and a signal pad in the second dielectric layer.
Kim teaches redistribution structures that comprise components for power, signal and ground (¶0056 of Kim).
These components are well-known to be part of the conductive redistribution layers within redistribution structures and claiming these components does not patentably distinguish claim 6 over the art of record.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THADDEUS J KOLB whose telephone number is (571)272-0276. The examiner can normally be reached Monday - Friday, 8:30am - 5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached at (571) 272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/T.J.K./ Examiner, Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817