DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed on Jun. 24th 2026 has been entered. Claims 16-17, 27-28, 33, 37-38, 41-42 and 45-55 remain pending in the application.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 16-17, 27, 37, 46-47 and 53 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 20130062692) in view of Lee et al. (US 20060081895) and Hsu et al. (US 20230197710).
Regarding claim 16, Chen teaches a method (Abstract), comprising:
etching (fig. 3C, etching for source fins 322a-c; para. 0032) a substrate (substrate 304; para. 0028) and in a device region (fig. 1, region of planar topology portion 101, FinFET topology portion 103; para. 0022) of a semiconductor device (half-FinFET semiconductor device 100; para. 0021) to form a first source/drain active region (source region 122; para. 0021);
form a second source/drain active region (continuous drain region 112; para. 0021);
form a channel active region (channel region 150; para. 0021),
wherein the channel active region (150) is between the first source/drain active region (122) and the second source/drain active region (112),
wherein the second source/drain active region (112) comprises a planar active region (112),
and wherein the first source/drain active region (122) comprises a first plurality of fin active regions (source fins 122a-c; para. 0021) and the channel active region (150) comprises a second plurality of fin active regions (P type body well regions 106; para. 0021) connected to the first plurality of fin active regions (112a-c); and
forming a gate structure (gate structure 142; para. 0021) over at least three sides of the channel active region (fig. 3F, gate structure 342/142 over three sides of P type body well 306/106 of 150; para. 0034),
wherein the first plurality of fin active regions (122a-c) and the second plurality of fin active regions (106) extend in an extension direction (fig. 1, horizontal direction) that is approximately perpendicular with the gate structure (142),
wherein the first source/drain active region (122), the channel active region (150), and the second source/drain active region (112) are arranged along the extension direction (horizontal direction),
wherein the channel active region (150) comprises a planar extension region (drain extension well 108 in 150; para. 0021) spaced apart from the planar active region (112) along the extension direction (horizontal direction), and
wherein a portion of the planar extension region (portion of 108 in 150) under the gate structure (142) is in physical contact with end portions of the second plurality of fin active regions (end portion of 106),
wherein the planar active region (fig. 4, continuous drain region 412 as 112; para. 0039) and the planar extension region (N type drain extension well 408 under gate structure 442 as 108 under 142; para. 0039) are separated by a gate shallow trench isolation (STI) region (isolation body 414 as STI; para. 0040),
wherein the gate shallow trench isolation (STI) region (414) is at a first height (0 height) with respect to the substrate (304),
wherein a plurality of additional shallow trench isolation (STI) regions (fig. 1, isolation regions 124; para. 0021) extend along the extension direction (horizontal direction) on opposing sides (right side opposing the left side) of the gate shallow trench isolation (STI) region (414), the planar active region (112), and the planar extension region (108).
Chen fails to teach etching the substrate in the device region to form a second source/drain active region;
etching the substrate in the device region to form a channel active region.
However, Lee teaches etching (Lee: fig. 8, etched using hard mask 104b; para. 0046) the substrate (Lee: substrate 100; para. 0046, similar to 304 of Chen) in the device region (Lee: planar region 55; para. 0046, similar to 101, 103 of Chen) to form a second source/drain active region (Lee: fig. 4, second impurity doped layer 132b; para. 0039, similar to 112 of Chen);
etching the substrate (Lee: fig. 8, etched 100) in the device region (Lee: 55) to form the channel active region (Lee: fig. 4, the region for planar gate electrode 130b; para. 0031, similar to 150 of Chen).
Lee and Chen are considered to be analogous to the claimed invention because they are in the same field of field effect transistors.
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed to add etching the substrate as taught by Lee.
Doing so would realize the planar active region is formed to be lower than the fin active region to prevents damage from occurring in the manufacture of the semiconductor device to preserve the device's electrical characteristics (Lee: para. 0068).
In addition, Chen in view of Lee fails to explicitly teach the planar active region and the planar extension region are at a second height with respect to the substrate that is greater than the first height.
However, Hsu teaches the planar active region (Hsu: fig. 11, source/drain regions 70, similar to 112 of Chen) and the planar extension region (Hsu: region under gate electrode 66, like fin-shaped structures 24; para. 0022, similar to 108 of Chen) are at a second height (Hsu: height higher than shallow trench isolation (STI) 50; para. 0021) with respect to the substrate (Hsu: substrate 12) that is greater than the first height (Hsu: height of 50, similar to 414 of Chen).
Hsu, Lee and Chen are considered to be analogous to the claimed invention because they are in the same field of field effect transistors.
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed to add the planar active region and the planar extension region are at a second height with respect to the substrate that is greater than the first height as taught by Hsu.
Doing so would realize a STI enough for high voltage to improve the current fabrication for improving performance of the device (Hsu: para. 0004). Here the general conditions of a claim are disclosed in the prior art, a change in shape is generally recognized as being within the level of ordinary skill in the art. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Regarding claim 17, Chen in view of Lee and Hsu further teaches the method of claim 16, wherein the gate shallow trench isolation (STI) region (Chen: fig. 4, isolation body 414 as STI; para. 0040) is formed in the substrate (Chen: substrate 404 as 304; para. 0039).
Regarding claim 27, Chen in view of Lee and Hsu further teaches the method of claim 16 wherein the planar active region (Chen: fig. 4, continuous drain region 412 as 1124; para. 0039) and the second plurality of fin active regions (Chen: source fin 422b as 122; para. 0039) are separated by the gate shallow trench isolation (STI) region (Chen: isolation body 414 as STI; para. 0040).
Regarding claim 37, Chen in view of Lee and Hsu further teaches the method of claim 16, wherein the first source/drain active region (Chen: fig. 1, 122) is adjacent to a first side (right side) of the channel active region (Chen: 150), and wherein the second source/drain active region (Chen: 112) is adjacent to a second side (left side) of the channel active region (Chen: 150) opposite to the first side (right side).
Regarding claim 46, Chen in view of Lee and Hsu further teaches the method of claim 16, wherein an additional portion of the planar extension region (Chen: fig. 1, portion of 108 out of 150 additional to the portion of 108 in 150) is disposed on a side (left side) of the gate structure (Chen: 142) along the extension direction (horizontal direction).
Regarding claim 47, Chen in view of Lee and Hsu further teaches the method of claim 16, wherein the second height (Hsu: fig. 11, height of 70) is above the substrate (Hsu: height of 12).
Regarding claim 53, Chen in view of Lee and Hsu further teaches the method of claim 16, wherein the opposing sides (Chen: fig. 1, right side) of the gate shallow trench isolation (STI) region (Chen: 414), the planar active region (Chen: 108, both on left side), and the planar extension region (Chen: 112, both on left side) are along a direction (vertical direction) approximately perpendicular to the extension direction (horizontal direction).
Claims 28, 33, 38, 41-42, 45, 49-52 and 54-55 are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Hsu.
Regarding claim 28, Chen teaches a method (Abstract), comprising:
forming a first source/drain active region (fig. 1, source region 122; para. 0021) in a substrate (fig. 3E, substrate 304; para. 0028) in a device region (fig. 1, region of planar topology portion 101, FinFET topology portion 103; para. 0022) of a semiconductor device (half-FinFET semiconductor device 100; para. 0021);
forming a second source/drain active region (continuous drain region 112; para. 0021) in the substrate (304) in the device region (101, 103),
wherein the second source/drain active region (112) comprises a planar active region (112);
forming a channel active region (channel region 150; para. 0021) in the substrate (304) in the device region (101, 103),
wherein the first source/drain active region (122) comprises a first plurality of fin active regions (source fins 122a-c; para. 0021),
wherein the channel active region (150) comprises a second plurality of fin active regions (P type body well regions 106; para. 0021), and
wherein the first plurality of fin active regions (122a-c) contact the second plurality of fin active regions (106); and
forming a gate structure (gate structure 142; para. 0021) over at least three sides of the channel active region (fig. 3F, gate structure 342/142 over three sides of P type body well 306/106 of 150; para. 0034),
wherein the first plurality of fin active regions (122a-c) and the second plurality of fin active regions (106) extend in an extension direction (fig. 1, horizontal direction) that is approximately perpendicular with the gate structure (142), wherein the first source/drain active region (122), the channel active region (150), and the second source/drain active region (112) are arranged along the extension direction (horizontal direction):
wherein the channel active region (150) comprises a planar extension region (drain extension well 108 in 150; para. 0021) spaced apart from the planar active region (112) along the extension direction (horizontal direction), and
wherein a portion of the planar extension region (portion of 108 in 150) under the gate structure (142) is in physical contact with end portions of the second plurality of fin active regions (end portion of 106),
wherein the planar active region (fig. 4, continuous drain region 412 as 112; para. 0039) and the planar extension region (N type drain extension well 408 under gate structure 442 as 108 under 142; para. 0039) are separated by a gate shallow trench isolation (STI) region (isolation body 414 as STI; para. 0040),
wherein the gate shallow trench isolation (STI) region (414) is at a first height (0 height) with respect to the substrate (304),
wherein a plurality of additional shallow trench isolation (STI) regions (fig. 1, isolation regions 124; para. 0021) extend along the extension direction (horizontal direction) on opposing sides (right side opposing the left side) of the gate shallow trench isolation (STI) region (414), the planar active region (112), and the planar extension region (108).
Chen fails to explicitly teach the planar active region and the planar extension region are at a second height with respect to the substrate that is greater than the first height.
However, Hsu teaches the planar active region (Hsu: fig. 11, source/drain regions 70, similar to 112 of Chen) and the planar extension region (Hsu: region under gate electrode 66, like fin-shaped structures 24; para. 0022, similar to 108 of Chen) are at a second height (Hsu: height higher than shallow trench isolation (STI) 50; para. 0021) with respect to the substrate (Hsu: substrate 12) that is greater than the first height (Hsu: height of 50, similar to 414 of Chen).
Hsu and Chen are considered to be analogous to the claimed invention because they are in the same field of field effect transistors.
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed to add the planar active region and the planar extension region are at a second height with respect to the substrate that is greater than the first height as taught by Hsu.
Doing so would realize a STI enough for high voltage to improve the current fabrication for improving performance of the device (Hsu: para. 0004). Here the general conditions of a claim are disclosed in the prior art, a change in shape is generally recognized as being within the level of ordinary skill in the art. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Regarding claim 33, Chen teaches a method (Abstract), comprising:
forming a first source/drain active region (fig. 1, source region 122; para. 0021) in a substrate (fig. 3E, substrate 304; para. 0028) in a device region (fig. 1, region of planar topology portion 101, FinFET topology portion 103; para. 0022) of a semiconductor device (half-FinFET semiconductor device 100; para. 0021), wherein the first source/drain active region (122) extends above the substrate (lower portion 304);
forming a second source/drain active region (continuous drain region 112; para. 0021) in the substrate (304) in the device region (101, 103), wherein the second source/drain active region (fig. 3E, 312 as 112) extends above the substrate (lower portion 304),
wherein the second source/drain active region (112) comprises a planar active region (112);
forming a channel active region (channel region 150; para. 0021), in the substrate (304) in the device region (101, 103), between the first source/drain active region (122) and the second source/drain active region (112) and extending above the substrate (lower portion 304),
wherein the first source/drain active region (122) and the channel active region (150) comprise a plurality of fin active regions (source fins 122a-c and P type body well regions 106; para. 0021),
wherein the first source/drain active region (122) and the channel active region (150) are directly connected through the plurality of fin active regions (122a-c, 106); and
forming a gate structure (gate structure 142; para. 0021) over at least three sides of the channel active region (fig. 3F, gate structure 342/142 over three sides of P type body well 306/106 of 150; para. 0034),
wherein the plurality of fin active regions (122a-c, 106) extend in an extension direction (fig. 1, horizontal direction) that is approximately perpendicular with the gate structure (142), wherein the first source/drain active region (122), the channel active region (150), and the second source/drain active region (112) are arranged along the extension direction (horizontal direction),
wherein the channel active region (150) comprises a planar extension region (drain extension well 108 in 150; para. 0021) spaced apart from the planar active region (112) along the extension direction (horizontal direction), and
wherein a portion of the planar extension region (portion of 108 in 150) under the gate structure (142) is in physical contact with end portions of the plurality of fin active regions (end portion of 106).
wherein the planar active region (fig. 4, continuous drain region 412 as 112; para. 0039) and the planar extension region (N type drain extension well 408 under gate structure 442 as 108 under 142; para. 0039) are separated by a gate shallow trench isolation (STI) region (isolation body 414 as STI; para. 0040),
wherein the gate shallow trench isolation (STI) region (414) is at a first height (0 height) with respect to the substrate (304),
wherein a plurality of additional shallow trench isolation (STI) regions (fig. 1, isolation regions 124; para. 0021) extend along the extension direction (horizontal direction) on opposing sides (right side opposing the left side) of the gate shallow trench isolation (STI) region (414), the planar active region (112), and the planar extension region (108).
Chen fails to explicitly teach the planar active region and the planar extension region are at a second height with respect to the substrate that is greater than the first height.
However, Hsu teaches the planar active region (Hsu: fig. 11, source/drain regions 70, similar to 112 of Chen) and the planar extension region (Hsu: region under gate electrode 66, like fin-shaped structures 24; para. 0022, similar to 108 of Chen) are at a second height (Hsu: height of 70 higher than shallow trench isolation (STI) 50; para. 0021) with respect to the substrate (Hsu: substrate 12) that is greater than the first height (Hsu: height of 50, similar to 414 of Chen).
Hsu and Chen are considered to be analogous to the claimed invention because they are in the same field of field effect transistors.
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed to add the planar active region and the planar extension region are at a second height with respect to the substrate that is greater than the first height as taught by Hsu.
Doing so would realize a STI enough for high voltage to improve the current fabrication for improving performance of the device (Hsu: para. 0004). Here the general conditions of a claim are disclosed in the prior art, a change in shape is generally recognized as being within the level of ordinary skill in the art. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Regarding claim 38, Chen in view of Hsu further teaches the method of claim 28, wherein the gate shallow trench isolation (STI) region (Chen: fig. 4, isolation body 414 as STI; para. 0040) is formed in the substrate (Chen: substrate 404 as 304; para. 0039).
Regarding claim 41, Chen in view of Hsu further teaches the method of claim 28, wherein the first source/drain active region (Chen: fig. 1, 122) is adjacent to a first side (right side) of the channel active region (Chen: 150), and wherein the second source/drain active region (Chen: 112) is adjacent to a second side (left side) of the channel active region (Chen: 150) opposite to the first side (right side).
Regarding claim 42, Chen in view of Hsu further teaches the method of claim 28, wherein the gate shallow trench isolation (STI) region (Chen: fig. 4, isolation body 414 as STI; para. 0040) is formed in the substrate (Chen: substrate 404 as 304; para. 0039).
Regarding claim 45, Chen in view of Hsu further teaches the method of claim 33 wherein the planar active region (Chen: fig. 4, continuous drain region 412 as 1124; para. 0039) and the planar extension region (Chen: N type drain extension well 408 under gate structure 442 as 108 under 142; para. 0039) are separated by a gate shallow trench isolation (STI) region (Chen: isolation body 414 as STI; para. 0040).
Regarding claim 49, Chen in view of Hsu further teaches the method of claim 28, wherein an additional portion of the planar extension region (Chen: fig. 1, portion of 108 out of 150 additional to the portion of 108 in 150) is disposed on a side (left side) of the gate structure (Chen: 142) along the extension direction (horizontal direction).
Regarding claim 50, Chen in view of Hsu further teaches the method of claim 28, wherein the second height (Hsu: fig. 11, height of 70) is above the substrate (Hsu: height of 12).
Regarding claim 51, Chen in view of Hsu further teaches the method of claim 33, wherein an additional portion of the planar extension region (Chen: fig. 1, portion of 108 out of 150 additional to the portion of 108 in 150) is disposed on a side (left side) of the gate structure (Chen: 142) along the extension direction (horizontal direction).
Regarding claim 52, Chen in view of Hsu further teaches the method of claim 33, wherein the second height (Hsu: fig. 11, height of 70) is above the substrate (Hsu: height of 12).
Regarding claim 54, Chen in view of Hsu further teaches the method of claim 28, wherein the opposing sides (Chen: fig. 1, right side) of the gate shallow trench isolation (STI) region (Chen: 414), the planar active region (Chen: 108, both on left side), and the planar extension region (Chen: 112, both on left side) are along a direction (vertical direction) approximately perpendicular to the extension direction (horizontal direction).
Regarding claim 55, Chen in view of Hsu further teaches the method of claim 33, wherein the opposing sides (Chen: fig. 1, right side) of the gate shallow trench isolation (STI) region (Chen: 414), the planar active region (Chen: 108, both on left side), and the planar extension region (Chen: 112, both on left side) are along a direction (vertical direction) approximately perpendicular to the extension direction (horizontal direction).
Claim 48 is rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Lee and Hsu as applied to claim 16 above, and further in view of Singh et al. (US 20190245080).
Regarding claim 48, Chen in view of Lee and Hsu further teaches the method of claim 16, wherein a dimension of the planar active region (Chen: fig. 1, height of 112) along a direction (vertical direction) approximately perpendicular to the extension direction (horizontal direction) and a dimension of the planar extension region (Chen: height of 108) along the direction (vertical direction) approximately perpendicular to the extension direction (horizontal direction) and a dimension of the gate shallow trench isolation (STI) region (Chen: fig. 1, height of 414 as 108 between 112 and 142) along the direction (vertical direction) approximately perpendicular to the extension direction (horizontal direction).
Chen in view of Lee and Hsu fails to explicitly teach the dimension of the planar active region and the dimension of the planar extension region are approximately equal to the dimension of the gate shallow trench isolation (STI) region.
However, Singh teaches the dimension of the planar active region (Singh: fig. 1C, height of drain region 153; para. 0028, similar to 112 of Chen) and the dimension of the planar extension region (Singh: height of first well region 151; para. 0028, similar to 108 of Chen) are approximately equal to the dimension of the gate shallow trench isolation (STI) region (Singh: height of trench isolation region 103 within rectangle; para. 0033, similar to 414 of Chen).
Singh, Hsu, Lee and Chen are considered to be analogous to the claimed invention because they are in the same field of field effect transistors.
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed to add the dimension of the planar active region and the dimension of the planar extension region are approximately equal to the dimension of the gate shallow trench isolation (STI) region as taught by Singh.
Doing so would realize a STI with increased effective width to improve voltage drop from source to drain and providing a low on-resistance (Singh: para. 0083).
Response to Arguments
Applicant’s arguments with respect to claims 16-17, 27-28, 33, 37-38, 41-42 and 45-55 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZHIJUN XU whose telephone number is (571)270-3447. The examiner can normally be reached Monday-Thursday 9am-5pm ET.
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/ZHIJUN XU/Examiner, Art Unit 2818
/BRIAN TURNER/Primary Examiner, Art Unit 2818
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