DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed on September 30, 2025 in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on September 15, 2025 has been entered.
Response to Arguments
RE: the objection to claim(s) 14, Applicant’s arguments and/or amendments have resolved the typographical issues in these claims. Accordingly, the objection to claim(s) 14 is withdrawn.
RE: the rejection of claim(s) 16, 18, 20 under 35 USC 112(b), Applicant’s arguments and/or amendments have been fully considered and resolve the issues of indefiniteness in claims 18 and 20. Accordingly, the rejection of claim(s) 18 and 20 has been withdrawn. However, as discussed below, Applicant’s amendment to claim 16 introduced a new issue of indefiniteness and the previous rejection of claim 16 is therefore maintained.
RE: the rejection of claim(s) 14-27, 29-33 under 35 USC 103, Applicant’s arguments and/or amendments have been fully considered but are moot as further search and consideration prompted the new grounds of rejection presented herein.
Further, Applicant’s amendment introduced new issues of new matter, indefiniteness, and improper dependency as further discussed below in the rejections under 35 USC 112(a), 35 USC 112(b), and 35 USC 112(d).
Claim Objections
Claims 19, 21 are objected to because of the following informalities:
Claim 19 includes “joining a hybrid bond layer structure of the first portion of the seal ring structure to a hybrid bond layer structure of the second portion of the seal ring structure” which is considered a typographical error of “joining the first hybrid bond layer structure of the first portion of the seal ring structure to the second hybrid bond layer structure of the second portion of the seal ring structure” as these were previously introduced in claim 14.
Claim 21 includes “wherein side surfaces, of a portion of the one or more interconnects structure” which is considered a typographical error of “wherein side surfaces, of a portion of the one or more interconnect structures.”
Claim Rejections - 35 USC § 112(a)
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 14-27 and 29-34 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 14 includes “wherein side surfaces of the first substructure of the first portion of the seal ring structure are free from any material” and “wherein side surfaces of the first substructure of the second portion of the seal ring structure are free from any material” and this has no support in the instant application and is therefore considered new matter, as further discussed below.
Claim 21 includes “wherein side surfaces, of a portion of the one or more interconnects structure extending through the backside of the first substrate, are free from any material” and this has no support in the instant application and this has no support in the instant application and is therefore considered new matter, as further discussed below.
Firstly, it is unclear how there could be support for a surface being free from any material, including being free from the material that forms the surface. A surface without material would not be a surface, it would be empty space.
The above limitations are therefore interpreted to mean the relevant side surfaces are exposed to air or empty space.
This interpretation of the above limitations in claims 14 and 21 may be supported if the below regions in Annotated FIG. 2A are free of any material.
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(Annotated FIG. 2A of the instant application)
However, this interpretation is not supported by the instant application as these regions are not described by the instant specification as being free of any material, and the drawings do not show these regions as being free of any material.
For example, the instant specification states The IC die 205 a may be bonded to the IC die 205 b along a bond line 230, [0030].
FIG. 2A shows the bond line 230 extending into regions that Applicant appears to allege are free of any material.
If Applicant’s allegation was assumed to be true, the bond line 230 in FIG. 2A would not extend into the regions free of any material, as there would be no material present to form the bond line 230 in these regions.
In addition, hybrid bonding is known as including metal-to-metal bonding and dielectric-to-dielectric bonding, as further discussed below.
US 20190214257 A1 (“Lin”) discloses hybrid bonding is an emerging technology, and will become a high yield and high-reliability bonding technology with great potential. The hybrid bonding combines dielectric-dielectric bonding with metal-metal bonding, [0005].
US20210305200A1 (“Lin-2”) discloses Hence, the resulting bonds between the wafers are hybrid bonds that include both dielectric-to-dielectric bonds and metal-to-metal bonds, [0040].
Further, the non-patent literature reference Sharon Nannette Farrens. "Hybrid Wafer Bonding – The Fusion of Low Temperature Dielectric and Metal Bonding Technologies," 2020 ECS Trans. 98 145 (2020) (“Farrens”) discusses various types of bonding including Fusion Bonding (pg. 146), Metal Bonding (pg. 148), Hybrid Bonding (pg. 149-154).
In particular, Farrens discloses Hybrid bonding is a combination of dielectric bonding and metal diffusion bonding (bottom paragraph, pg. 149).
As the instant specification describes elements 235a, 235b as hybrid bond layer structures of conductive material such as various metals, [0030], one of ordinary skill in the art would understand there to be dielectric material along the bond line 230 in FIG. 2A in order to make the hybrid bond between dies 205a and 205b which would include the metal-to-metal bonding between 235a, 235b and dielectric-to-dielectric bonding.
Accordingly, in view of the prior art, there would be dielectric material present in the regions alleged as being free of any material in Annotated FIG. 2A above.
Thus, there is no support for the above limitations in claims 14 and 21, as these are considered to be directed to new matter.
Claim 29 includes “forming a first well structure, over a first substrate, and a second well structure, over a second substrate;
forming a first transistor structure, within a first device region associated with the first substrate, and a second transistor structure within a second device region associated with the second substrate, wherein the first transistor structure comprises a first portion within the first well structure and a second portion above the first well structure, and wherein the second transistor structure comprises a first portion within the second well structure and a second portion above the second well structure, wherein side surfaces of the second portion of the first well structure and the second well structure are free from any material” and this has no support in the instant application and is therefore considered new matter, as further discussed below.
Firstly, it is unclear how there could be support for a surface being free from any material, including being free from the material that forms the surface. A surface without material would not be a surface, it would be empty space.
Secondly, the wording “second portion of the first well structure and the second well structure” has no antecedent basis and it is unclear if this was intended to refer to the first and second well structures or to the first and second transistor structures which have the second portions. Whatever the intended meaning, there is no support in the instant application for side surfaces of any well structure being free of any material.
If the above limitation was intended to mean “wherein side surfaces of the second portions of the first transistor structure and the second transistor structure are free from any material” this also does not have support in the instant application, as this has the same or similar issues as the new limitations in claims 14 and 21 (see above remarks regarding these claims).
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims.
Claim 14 includes “wherein side surfaces of the first substructure of the first portion of the seal ring structure are free from any material” and “wherein side surfaces of the first substructure of the second portion of the seal ring structure are free from any material” and as discussed above in the rejection under 35 USC 112(a) this has no support in the instant application and is not shown in the drawings.
Claim 21 includes “wherein side surfaces, of a portion of the one or more interconnects structure extending through the backside of the first substrate, are free from any material” and as discussed above in the rejection under 35 USC 112(a) this has no support in the instant application and is not shown in the drawings.
Claim 29 includes “wherein side surfaces of the second portion of the first well structure and the second well structure are free from any material” and as discussed above in the rejection under 35 USC 112(a) this has no support in the instant application and is not shown in the drawings.
Therefore, the above features must be shown or the feature(s) canceled from the claim(s). For example, the above features may be shown if regions in the figures are labeled as empty or void regions. However, this may introduce new matter and Applicant is reminded that no new matter should be entered when making amendments to the application.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 14-27 and 29-34 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 14 includes “wherein side surfaces of the first substructure of the first portion of the seal ring structure are free from any material” and “wherein side surfaces of the first substructure of the second portion of the seal ring structure are free from any material” and this is indefinite as it is unclear how a surface would be free from any material, including being free from the material that forms the surface. A surface without material would not be a surface, it would be empty space.
For the purposes of examination, the above limitation will be interpreted to mean “wherein side surfaces of the first substructure of the first portion of the seal ring structure are exposed to air or empty space.”
Claim 16 includes “wherein forming the second substructure of the first portion of the seal ring structure comprises: forming the second hybrid bond contact structure over the plurality of metal layers, and forming the second hybrid bond layer structure over the hybrid bond contact structure” and this is indefinite because the second portion of the seal ring structure has the second hybrid contact structure and the second hybrid bond layer structure in claim 14. Accordingly, it is believed that this was intended to mean “wherein forming the second substructure of the first portion of the seal ring structure comprises: forming the first hybrid bond contact structure over the plurality of metal layers, and forming the first hybrid bond layer structure over the hybrid bond contact structure” and this limitation will be interpreted in this manner for the purposes of examination.
Claim 21 includes “wherein side surfaces, of a portion of the one or more interconnects structure extending through the backside of the first substrate, are free from any material.” and this indefinite as it is unclear how a surface would be free from any material, including being free from the material that forms the surface. A surface without material would not be a surface, it would be empty space.
For the purposes of examination, the above limitation will be interpreted to mean “wherein side surfaces, of a portion of the one or more interconnects structure extending through the backside of the first substrate, are exposed to air or empty space.”
Claim 29 includes “forming a first well structure, over a first substrate, and a second well structure, over a second substrate;
forming a first transistor structure, within a first device region associated with the first substrate, and a second transistor structure within a second device region associated with the second substrate, wherein the first transistor structure comprises a first portion within the first well structure and a second portion above the first well structure, and wherein the second transistor structure comprises a first portion within the second well structure and a second portion above the second well structure, wherein side surfaces of the second portion of the first well structure and the second well structure are free from any material” and the underlined portion has no antecedent basis rendering this limitation indefinite. As the well structures have no second portions, it is unclear if this was intended to refer to the first and second well structures or to the first and second transistor structures which have the second portions.
As the first and second transistor structures have the second portions in this claim, it is believed the limitation was intended to mean “wherein side surfaces of the second portions of the first transistor structure and the second transistor structure are free from any material.”
However, this limitation would still be indefinite as it is unclear how a surface would be free from any material, including being free from the material that forms the surface. A surface without material would not be a surface, it would be empty space.
For the purposes of examination, the above limitation will be interpreted to mean “wherein side surfaces of the second portions of the first transistor structure and the second transistor structure are exposed to air or empty space.”
Claim 30 includes “the first transistor structure comprises a first portion within the first well structure and a second portion above the first well structure, and the second transistor structure comprises a first portion within the second well structure and a second portion above the second well structure” which is previously included in claim 29. It is therefore unclear if the elements from claim 30 refer to the same elements introduced in claim 29, or if they are different elements. For the purposes of examination, these will be interpreted as referring to the same elements.
Claim Rejections - 35 USC § 112(d)
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claims 30, 33 are rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends.
Claim 30 includes “the first transistor structure comprises a first portion within the first well structure and a second portion above the first well structure, and the second transistor structure comprises a first portion within the second well structure and a second portion above the second well structure” which is previously required by claim 29. Therefore, claim 30 does not specify a further limitation of the subject matter in claim 29.
Claim 33 includes “wherein the one or more interconnect structures are formed through the first substrate and the first well structure” which is previously required by claim 29. Therefore, claim 33 does not specify a further limitation of the subject matter in claim 29.
Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 14-18 are rejected under 35 U.S.C. 103 as being unpatentable over US20180269161A1 (“Wu”) in view of US6667552B1 (“Buynoski”), further in view of US20220181313A1 (“Gomes”).
RE: Claim 14, Wu discloses A method (FIGS. 1A-1E are cross-sectional views of various stages of a process for forming a hybrid-bonding structure 600A, [0012]), comprising:
forming, over a first surface (upper surface of 100 in 500a’ as represented for 500a in FIG. 1D; structure 500a′ similar to or the same as the structure 500a formed by the aforementioned processes shown in FIG. 1A to FIG. 1E are bonded to the structure 500a vertically to form the hybrid-bonding structure 600A by performing a hybrid-bonding process, as shown in FIG. 1E, [0035]; Accordingly, 500a’ is formed by the same process used to form 500a) of a first substrate (100 in 500a’), a first substructure (112 for 500a’, FIG. 1D) of a first portion of a seal ring structure (104b including 114; the seal ring structure 114 includes conductive layers 112 and vias 108 formed in the dielectric layer 106, [0018]);
forming, over a second substrate (upper surface of 100 in 500a in FIG. 1D;), a first substructure (112 for 500a; in FIG. 1E, each of 500a and 500a’ include 112 and 100) of a second portion of the seal ring structure (114);
forming, over the first substructure (112 for 500a’) of the first portion of the seal ring structure, a second substructure (128, 132, 134 for 500a’ in FIG. 1D, [0029]; the conductive line 132 (or the conductive line 134) serves as a bonding layer of the seal ring structure 114 of the structure 500 a, [0029]) of the first portion of the seal ring structure;
forming, over the first substructure (112 for 500a) of the second portion of the seal ring structure, a second substructure (128, 132, 134 for 500a, see FIG. 1D, [0029]) of the second portion of the seal ring structure,
wherein at least one of:
the second substructure of the first portion of the seal ring structure comprises a first hybrid bond contact structure (128 for 500a’ in FIG. 1D), in contact with the first substructure of the first portion of the seal ring structure (128 is in direct contact with 112 in FIG. 1D), and a first hybrid bond layer structure (132) in contact with the first hybrid bond contact structure (132 is in direct contact with 128 in FIG. 1D), or
the second substructure of the second portion of the seal ring structure comprises a second hybrid bond contact structure (128 for 500a in FIG. 1D), in contact with the first substructure of the second portion of the seal ring structure (128 is in direct contact with 112 in FIG. 1D), and a second hybrid bond layer structure (132) in contact with the second hybrid bond contact structure (132 is in direct contact with 128 in FIG. 1D; further, this entire limitation is considered optional due to the presence of the word “or” above; it is therefore met when the limitations preceding the “or” are met);
joining the second substructure of the first portion of the seal ring structure to the second substructure of the second portion of the seal ring structure (a structure 500 a′ similar to or the same as the structure 500 a formed by the aforementioned processes shown in FIG. 1A to FIG. 1E are bonded to the structure 500 a vertically to form the hybrid-bonding structure 600A by performing a hybrid-bonding process, as shown in FIG. 1E, [0035]; FIG. 1E shows 128, 132, 134 of 500a’ bonded to 128, 132, 134 of 500a).
Wu does not explicitly disclose wherein side surfaces of the first substructure of the first portion of the seal ring structure are free from any material;
wherein side surfaces of the first substructure of the second portion of the seal ring structure are free from any material; and
forming, through the first substrate, an interconnect structure that connects to the first substructure of the first portion of the seal ring structure,
wherein forming the interconnect structure comprises forming the interconnect structure from a second surface of the first substrate that is opposite the first surface.
However, in the same field of endeavor, Buynoski discloses As shown in FIG. 2, the dielectric material 11 is removed, as with a slightly acidic buffered hydrofluoric acid solution, thereby creating voids or air gaps 20 throughout the interconnection structure. The formation of air gaps 20 significantly reduces the capacitance of the entire interconnection system as the dielectric constant of air is taken as one, Col. 6, lines 35-41.
It would have been obvious to one of ordinary skill in the art to remove the dielectric layer 106 in each of 500, 500’ thereby creating voids or air gaps around the interconnection system (112, 108, 128, 132) as taught by Buynoski in order to reduce the capacitance of the interconnection system. As a result, side surfaces of 112 for 500a and 112 for 500a’ would be exposed to air gaps or voids.
In the same field of endeavor, Gomes discloses that FIG. 11 illustrates some embodiments of the microelectronic assembly 100 where an after-bonding via 140 extends through multiple pairs of IC structures 110 and 120 bonded together. While FIGS. 5-11 illustrate certain arrangements of various components of the IC structures 110 and 120, one or more of the after-bonding interconnects as described with reference to the after-bonding via 140 of FIGS. 5-11 may be provided in any embodiments of the microelectronic assembly 100 as described with reference to FIGS. 1-4, [0094]-[0095].
FIG. 11B shows the after-bonding via extending through two interconnect layers 122 which are part of two respective stacks [0038].
Further, Gomes teaches that Providing one or more after-bonding interconnects may provide significant advantages in terms of its ability to provide electrical connectivity between various components of the microelectronic assembly 100 and/or reduced resistance. Also because of the reduced resistance, the after-bonding interconnects may be referred to as “express interconnects” (e.g., an express via) because they may allow routing power, ground, and/or signals to various components of the microelectronic assembly 100 faster than what would be achieved with the interconnects 112 and 122 that were in the individual IC structures 110, 120 before they were bonded together, [0093].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form at least one after-bonding via 140 extending through structures 500a and 500a’ and through the substrate 100 of 500a’ and connecting to a 112 in 500a and 112 in 500a’ as taught by Gomes in order to reduce resistance and to allow routing power, ground and/or signals to various components faster than would be achieved by 112, 108 in Wu (see Gomes [0093]). As the via 140 is an after-bonding via 140, it would be formed from the top surface of 100 of 500a’ in FIG. 1E of Wu, which would correspond to the bottom surface opposite the top surface of 100 in 500a’ in FIG. 1D.
RE: Claim 15, Wu in view of Buynoski, Gomes discloses The method of claim 14,
wherein forming the first substructure of the first portion of the seal ring structure comprises:
forming a vertical stack of a plurality of metal layers over the first substrate (Wu discloses conductive layers 112 may include multiple metal layers, [0019], see FIG. 1D).
RE: Claim 16, Wu in view of Buynoski, Gomes discloses method of claim 15, wherein forming the second substructure of the first portion of the seal ring structure comprises:
forming the first hybrid bond contact structure over the plurality of metal layers (128 of 500a’ is formed over 112 in Wu FIG. 1D), and
forming the first hybrid bond layer structure over the hybrid bond contact structure (132 of 500a’ is formed over 128 in FIG. 1D of Wu).
RE: Claim 17, Wu in view of Buynoski, Gomes discloses The method of claim 14, wherein forming the first substructure of the second portion of the seal ring structure comprises:
forming a vertical stack of a plurality of metal layers over the second substrate (Wu discloses conductive layers 112 may include multiple metal layers, [0019], see FIG. 1D).
RE: Claim 18, Wu in view of Buynoski, Gomes discloses The method of claim 17, wherein forming the second substructure of the second portion of the seal ring structure comprises:
forming the second hybrid bond contact structure over the plurality of metal layers (128 of 500a would be formed over 112 in Wu, see FIG. 1D), and
forming the second hybrid bond layer structure over the hybrid bond contact structure (132 of 500a would be formed over 128 in Wu, see FIG. 1D).
Claim(s) 19 is rejected under 35 U.S.C. 103 as being unpatentable over Wu in view of Buynoski, further in view of Gomes as applied to claim 14, further in view of US20190164919A1 to Hu et al. (“Hu”).
RE: Claim 19, Wu in view of Buynoski, Gomes does not explicitly disclose The method of claim 14, wherein joining the second substructure of the first portion of the seal ring structure to the second substructure of the second portion of the seal ring structure comprises:
joining a hybrid bond layer structure of the first portion of the seal ring structure to a hybrid bond layer structure of the second portion of the seal ring structure using an eutectic bonding process.
However, in the same field of endeavor, Hu discloses The first semiconductor device 100 and the second semiconductor device 300 may then be subjected to a temperature at or above the eutectic point for material of the first metal pad 121, the second metal pad 122, and the third metal pad 123 of the first semiconductor device 100 and the fourth metal pads 301 of the second semiconductor device 300, e.g., between about 150° C. and about 650° C., to fuse the metal bond pads. In this manner, fusion of the first semiconductor device 100 and the second semiconductor device 300 forms a hybrid bonded device, [0050].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to heat the conductive line 132, 134 in 500, 500’ above the eutectic point as taught by Hu in order to form a hybrid bonded structure including 500a and 500a’ with fused conductive lines which would form a seal against moisture.
Claim(s) 20 is rejected under 35 U.S.C. 103 as being unpatentable over Wu in view of Buynoski, further in view of Gomes, as applied to claim 14 further in view of US20140239411A1 to Brech (hereinafter “Brech”), and further in view of US20090053891A1 to Lin et al. (hereinafter “Lin”).
RE: Claim 20, Wu in view of Buynoski, Gomes does not explicitly disclose The method of claim 14, wherein forming the interconnect structure that connects to the first substructure of the first portion of the seal ring structure comprises:
forming a through-hole that passes through the first substrate and a well structure to expose the first substructure of the first portion of the seal ring structure, and
forming an oxide material within the through-hole.
However, Wu discloses The substrate 100 may include various doped regions such as p-type wells or n-type wells). Doped regions may be doped with p-type dopants, such as boron or BF2, and/or n-type dopants, such as phosphorus (P) or arsenic (As). The doped regions may be formed directly on the substrate 100, in a P-well structure, in an N-well structure or in a dual-well structure [0013].
Additionally, in the same field of endeavor, Brech shows in FIG. 2B a well region 35 extending across a top surface of a substrate 10 for a first transistor 101 and a second transistor 102, [0037],[0045].
It would have been obvious to one of ordinary skill in the art to modify the well region in Wu to extend laterally across the top surface of the substrate as taught by Brech by non-selective deposition of a dopant rather than by selective deposition in specific regions of 100, to simplify manufacturing and to improve the conductivity of the substrate.
Gomes further discloses In some embodiments, the location/depth of the bottom of the after-bonding via 140 extending from the top or from the bottom of the microelectronic assembly 100 may be based on a particular etch process used to form the after-bonding via 140. For example, if an opening for the after-bonding via 140 is formed using a selective etch process with etchants that remove the insulating materials 114, 124, as well as the etch-stop material 123, but do not remove, e.g., the etch-stop material 113, then the after-bonding via 140 may have a bottom aligned with the top of the etch-stop material 113. In another example, if an opening for the after-bonding via 140 is formed using a selective etch process with etchants that remove the insulating materials 114, 124, as well as the etch-stop material 123, but do not remove the bonding material 130, then the after-bonding via 140 may have a bottom aligned with the top of the bonding material 130 [0096].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form an after-bonding via using a selective etching process which forms an opening (i.e., through-hole) extending through 100 in 500a’ to expose 112 in order to reduce resistance and to allow routing power, ground and/or signals to various components faster than would be achieved by 112, 108 in Wu (see Gomes [0093]). The opening would therefore extend through the first substrate 100 in 500a’ and the well structure as the well structure would extend across the substrate, and as the opening is made, portions of a conductive layer 112 would be exposed.
Further, in the same field of endeavor, Lin discloses a liner oxide layer 212 may be formed by chemical vapor deposition on the sidewall and a bottom of the via hole 210, [0018].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form a liner oxide layer in the opening of the after-bonding via as taught by Lin in order to electrically insulate the after-bonding via from the substrate and well structure.
Claims 21-23, 27, 34 are rejected under 35 U.S.C. 103 as being unpatentable over US20210391302A1 to Kao et al. (“Kao”) in view of Gomes, further in view of Buynoski.
RE: Claim 21, Kao discloses A method (method of forming a backside contact on a backside of a substrate and directly over a semiconductor device within the substrate, [0037], FIGs. 7-22), comprising:
forming a first well structure (210 for device 110b, FIG. 2, [0022], [0038]), over a first substrate (108 in FIG. 7, [0038] which becomes 108b in FIG. 22 since structure in FIG. 7 gets flipped in FIG. 8 [0040], and structure in FIG. 21 gets relabeled in FIG. 22 so that device 110 in FIG. 21 is labelled as device 110b in FIG. 22, [0055]-[0056]), and a second well structure (unlabeled darkened region for 110c in FIG. 22, [0014]), over a second substrate (108c, FIG. 22, [0014]);
forming a first transistor structure (110 in FIG. 7; 110 in FIG. 7 becomes 110b in FIG. 22; 110 is a transistor, [0038]; 110b is a metal oxide semiconductor field effect transistor, [0022]), at least partially within the first well structure (Source/drain regions 202 reside in the doped well region 210, [0022]), and a second transistor structure (110c, [0056]; 110 is a transistor, [0038]);
forming one or more first stacks of layers (114 in 112, FIG. 7, [0014]; 112 becomes 112b in FIG. 22, [0056]), above the first transistor structure (114 is in 112 which is above 110 in FIG. 7, [0038]), and one or more second stacks of layers (114 in 112c in FIG. 22; Each of the interconnect structures (e.g., 112 a, 112 b, 112 c) may comprise a network of interconnect wires 114 and interconnect vias 116 surrounded by an interconnect dielectric structure 118, [0014]), above the second transistor structure (FIG. 22 shows interconnect structure 112c is above 110c; FIG. 22 shows unlabelled interconnect wires and interconnect vias above device 110c);
forming at least one of a first hybrid bond layer structure (120 in FIG. 7 [0039]; 120 in FIG. 7 becomes 120b in FIG. 22; bonding structures (e.g., 120 a, 120 b, 120 c) are hybrid bond (HB) structures [0014]) or a first contact structure, over the one or more first stacks of layers, and at least one of a second hybrid bond layer structure (120c in FIG. 22) or a second contact structure, over the one or more second stacks of layers;
joining the at least one of the first hybrid bond layer structure or the first contact structure to the at least one of the second hybrid bond layer structure or the second contact structure (a bonding process 2202 may be conducted to form a 3D IC stack, [0056]; the bonding process 2202 may be a hybrid bonding process [0056]; FIG. 22 shows 120b and 120c during the process of joining; FIG. 1 shows 120b, 120c joined).
Kao does not explicitly disclose the second transistor structure is at least partially within the second well structure;
forming, after joining the at least one of the first hybrid bond layer structure or the first contact structure to the at least one of the second hybrid bond layer structure or the second contact structure, one or more interconnect structures through a backside of the first substrate to a stack of layers of the one or more first stacks of layers,
wherein side surfaces, of a portion of the one or more interconnects structure extending through the backside of the first substrate, are free from any material.
However, Kao discloses the second semiconductor device 110 b may be, for example, a metal oxide semiconductor field effect transistor (MOSFET), and further that the second semiconductor device 110 b may comprise a doped well region 210 within the second substrate 108 b, wherein the doped well region 210 is more heavily doped and/or has a different doping type than the second substrate 108 b. Source/drain regions 202 may reside in the doped well region 210, and a gate electrode 206 over a gate dielectric layer 208 may be arranged on the frontside 108 bf of the second substrate 108 b, [0022]. Kao further teaches that more than one of the semiconductor devices (110 a, 110 b, 110 c) may be arranged on each of the substrates (108 a, 108 b, 108 c). Kao further teaches transistors are examples of semiconductor devices, [0011]. Further, the darkened unlabeled region in device 110c in FIG. 22 looks substantially the same as the labelled well region 210 in FIG. 2 which is also darkened and has a curved edge, indicating that the device 110c and 110b have substantially the same structure.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the third semiconductor device 110c in substantially the same way as the second semiconductor 110b in order to simplify manufacturing, where both are transistors, with a portion of the third device 110c within a second well region and over a second substrate 108c in order to control the conductivity within the portion of the third device 110c.
In the same field of endeavor, Gomes discloses that FIG. 11 illustrates some embodiments of the microelectronic assembly 100 where an after-bonding via 140 extends through multiple pairs of IC structures 110 and 120 bonded together. While FIGS. 5-11 illustrate certain arrangements of various components of the IC structures 110 and 120, one or more of the after-bonding interconnects as described with reference to the after-bonding via 140 of FIGS. 5-11 may be provided in any embodiments of the microelectronic assembly 100 as described with reference to FIGS. 1-4, [0094]-[0095].
FIG. 11B shows the after-bonding via extending through two interconnect layers 122 which are part of two respective stacks [0038].
Further, Gomes teaches that Providing one or more after-bonding interconnects may provide significant advantages in terms of its ability to provide electrical connectivity between various components of the microelectronic assembly 100 and/or reduced resistance. Also because of the reduced resistance, the after-bonding interconnects may be referred to as “express interconnects” (e.g., an express via) because they may allow routing power, ground, and/or signals to various components of the microelectronic assembly 100 faster than what would be achieved with the interconnects 112 and 122 that were in the individual IC structures 110, 120 before they were bonded together, [0093].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form at least one after-bonding via 140 extending through IC dies 102, 104, 106 ([0057] in Kao), through the backside of 108b, and to interconnects 114 in 112b to reduce resistance and to allow additional routing of power, ground and/or signals to various components faster than would be achieved by 114, 116 in Kao (see Gomes [0093]). As the via is an after-bonding via 140, it would be formed after the hybrid bonding process in Kao.
In the same field of endeavor, Buynoski discloses As shown in FIG. 2, the dielectric material 11 is removed, as with a slightly acidic buffered hydrofluoric acid solution, thereby creating voids or air gaps 20 throughout the interconnection structure. The formation of air gaps 20 significantly reduces the capacitance of the entire interconnection system as the dielectric constant of air is taken as one, Col. 6, lines 35-41.
It would have been obvious to one of ordinary skill in the art to remove the dielectric layer 118 in 112b in FIG. 22 thereby creating voids or air gaps around the interconnection system (114, 116) as taught by Buynoski in order to reduce the capacitance of the interconnection system. As a result, side surfaces of a portion of the after bonding via extending through the backside of 108b, would be exposed to air gaps or voids.
RE: Claim 22, Kao in view of Gomes, Buynoski discloses The method of claim 21, wherein:
the first transistor structure comprises a first portion within the first well structure and a second portion above the first well structure (Kao FIG. 7 shows a portion of 110 in the well region 210, and a portion of 110 in 112 which is above the well region 210, [0038]), and
the second transistor structure comprises a first portion within the second well structure and a second portion above the second well structure (Kao FIG. 22 shows a first portion of device 110c in a dark unlabelled region corresponding to the well region, and a second portion of device 110c in 112c which is above the well region, [0057]; As modified, 110c would be formed in the same way as 110b and would have a portion in the second well region 210, and a portion above the well second region 210).
RE: Claim 23, Kao in view of Gomes, Buynoski discloses The method of claim 21, wherein:
the one or more first stacks of layers comprises a plurality of first stacks of layers (Kao FIG. 7 shows at least two stacks of 114, 116 on the left and right of 110),
wherein the first transistor structure is in contact with one of the plurality of first stacks of layers (Kao FIG. 7 shows 110 in contact with the lefthand and righthand stacks 114, 116, [0038]), and
the one or more second stacks of layers comprises a plurality of second stacks of layers (Kao FIG. 22 shows at least two stacks in 112c, one on the left and right of 110c),
wherein the second transistor structure is in contact with one of the plurality of second stacks of layers (FIG. 22 shows 110c in contact with the lefthand and righthand stacks).
RE: Claim 27, Kao in view of Gomes, Buynoski discloses The method of claim 21, wherein the one or more interconnect structures comprises a plurality of interconnect structures in contact with different first stacks of layers of the one or more first stacks of layers (Gomes teaches besides what is shown in FIGS. 11A-11C, other arrangements of a plurality of the IC structures with one or more after-bonding vias 140 are possible and are within the scope of the present disclosure, [0152]. Accordingly, forming two or three after-bonding vias 140 is considered to be disclosed by Gomes. Further, FIG. 11B in Gomes shows 140 connecting to different 122 in different stacks; It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form additional after-bonding vias in contact with different layers 114 in 112b in Kao in order to to further reduce resistance and to allow additional routing of power, ground and/or signals).
RE: Claim 34, Kao in view of Gomes, Buynoski discloses The method of claim 21, wherein the one or more interconnect structures reside over the one or more first stacks of layers (In Gomes FIG. 11B, the after bonding via 140 resides over layers 122 which it makes direct contact with; Accordingly as modified, the after bonding via would be formed over 114 in 112b in Kao), the one or more second stacks of layers, the at least one of the first hybrid bond layer structure or the first contact structure (the remaining limitations in this clause are considered optional and therefore met due to the presence of “or” in this clause), and the at least one of the second hybrid bond layer structure (In Kao FIG. 22, 120b, 120c extend completely from the leftmost edge of 104, 106 to the rightmost edge of 104, 106; Accordingly as modified, the after bonding via 140 would reside over 120b, 120c in FIG. 22 in Kao) or the second contact structure.
Claims 24 and 26 are rejected under 35 U.S.C. 103 as being unpatentable over Kao in view of Gomes, Buynoski as applied to claim 21, and further in view of US20190355692A1 to Yeh et al. (hereinafter “Yeh”).
RE: Claim 24, Kao in view of Gomes, Buynoski does not explicitly disclose The method of claim 21, further comprising: forming, after joining the at least one of the first hybrid bond layer structure or the first contact structure to the at least one of the second hybrid bond layer structure or the second contact structure, a redistribution layer.
However, in the same field of endeavor, Yeh discloses dies 128 are bonded to the dies 28 through a hybrid bonding process, [0053] and After the dies 128 are bonded to the dies 28 and the dielectric layer 37 is formed, processes described in FIG. 1E are performed to form the RDL structure 50, [0055].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form a redistribution layer (RDL) structure after hybrid bonding 120b and 120c as taught by Yeh in order to increase the number of available connections to 102, 104, and/or 106 for improved signal routing.
RE: Claim 26, Kao in view of Gomes, Buynoski, Yeh discloses The method of claim 24, wherein the redistribution layer resides above the one or more interconnect structures, the first substrate, and the first well structure (In FIG. 2 of Yeh, the redistribution layer structure 50 extends completely over all underlying structures, including the hybrid bonded dies 128, 28; Accordingly as modified, the redistribution layer would extend completely over each element in 102, 104, and 106 including each 114, 108b, and the well structure in 108b).
Claim 25 is rejected under 35 U.S.C. 103 as being unpatentable over Kao in view of Gomes, Buynoski as applied to claim 21, and further in view of Brech.
RE: Claim 25, Kao in view of Gomes, Buynoski discloses The method of claim 21, wherein the one or more interconnect structures are formed through the first substrate (As modified, the after bonding via 140 would extend through the IC dies 102, 104, and 106 and so would extend through the substrate 108b).
However, Kao in view of Gomes, Buynoski does not explicitly disclose:
wherein the one or more interconnect structures are formed through the first well structure.
However, in a similar field of endeavor, Brech shows in FIG. 2B a well region 35 extending across a top surface of a substrate 10 for a first transistor 101 and a second transistor 102, [0037],[0045].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form a well layer extending laterally across the substrate 108b (108 in FIG. 7) of Kao by non-selective deposition of a dopant rather than by selective deposition in specific regions above 108b, in order to simplify manufacturing and increase the conductivity of the substrate. As a result, the after bonding via extending though IC dies 102, 104, and 106 would extend through the widened well layer that extends laterally across the substrate 108b.
Claims 29-31, 33 are rejected under 35 U.S.C. 103 as being unpatentable over Kao in view of Buynosk, further in view of Brech, further in view of Gomes.
RE: Claim 29, Kao discloses A method (method of forming a backside contact on a backside of a substrate and directly over a semiconductor device within the substrate, [0037], FIGs. 7-22), comprising:
forming a first well structure (210 for device 110b, FIG. 2, [0022], [0038]), over a first substrate (108 in FIG. 7, [0038] which becomes 108b in FIG. 22 since structure in FIG. 7 gets flipped in FIG. 8 [0040], and structure in FIG. 21 gets relabeled in FIG. 22 so that device 110 in FIG. 21 is labelled as device 110b in FIG. 22, [0055]-[0056]), and a second well structure (unlabeled darkened region for 110c in FIG. 22, [0014]), over a second substrate (108c, FIG. 22, [0014]);
forming a first transistor structure (110 in FIG. 7; 110 in FIG. 7 becomes 110b in FIG. 22; 110 is a transistor, [0038]; 110b is a metal oxide semiconductor field effect transistor, [0022]), within a first device region (104) associated with the first substrate, and a second transistor structure (110c, [0056]; 110 is a transistor, [0038]) within a second device region (106) associated with the second substrate,
wherein the first transistor structure comprises a first portion within the first well structure and a second portion above the first well structure (FIG. 7 shows a portion of 110 in the well region 210, and a portion of 110 in 112 which is above the well region 210, [0038]);
forming one or more first stacks of layers (114 in 112, FIG. 7, [0014]; 112 becomes 112b in FIG. 22, [0056]), in the first device region, and one or more second stacks of layers (114 in 112c in FIG. 22; Each of the interconnect structures (e.g., 112 a, 112 b, 112 c) may comprise a network of interconnect wires 114 and interconnect vias 116 surrounded by an interconnect dielectric structure 118, [0014]), in the second device region;
forming at least one of a first hybrid bond layer structure (120 in FIG. 7 [0039]; 120 in FIG. 7 becomes 120b in FIG. 22; bonding structures (e.g., 120 a, 120 b, 120 c) are hybrid bond (HB) structures [0014]) or a first contact structure, in the first device region, and at least one of a second hybrid bond layer structure (120c in FIG. 22) or a second contact structure, in the second device region;
joining the at least one of the first hybrid bond layer structure or the first contact structure to the at least one of the second hybrid bond layer structure or the second contact structure (a bonding process 2202 may be conducted to form a 3D IC stack, [0056]; the bonding process 2202 may be a hybrid bonding process [0056]; FIG. 22 shows 120b and 120c during the process of joining; FIG. 1 shows 120b, 120c joined).
Kao does not explicitly disclose:
wherein the second transistor structure comprises a first portion within the second well structure and a second portion above the second well structure;
wherein side surfaces of the second portions of the first transistor structure and the second transistor structure are exposed to air or empty space;
forming, after joining the at least one of the first hybrid bond layer structure or the first contact structure to the at least one of the second hybrid bond layer structure or the second contact structure, one or more interconnect structures through a backside of the first well structure and the first substrate to a stack of layers of the one or more first stacks of layers.
However, Kao discloses the second semiconductor device 110 b may be, for example, a metal oxide semiconductor field effect transistor (MOSFET), and further that the second semiconductor device 110 b may comprise a doped well region 210 within the second substrate 108 b, wherein the doped well region 210 is more heavily doped and/or has a different doping type than the second substrate 108 b. Source/drain regions 202 may reside in the doped well region 210, and a gate electrode 206 over a gate dielectric layer 208 may be arranged on the frontside 108 bf of the second substrate 108 b, [0022]. Kao further teaches that more than one of the semiconductor devices (110 a, 110 b, 110 c) may be arranged on each of the substrates (108 a, 108 b, 108 c). Kao further teaches transistors are examples of semiconductor devices, [0011]. Further, the darkened unlabeled region in device 110c in FIG. 22 looks substantially the same as the labelled well region 210 in FIG. 2 which is also darkened and has a curved edge, indicating that the device 110c and 110b have substantially the same structure.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the third semiconductor device 110c in substantially the same way as the second semiconductor 110b in order to simplify manufacturing, where both are transistors, with a portion of the third device 110c within a second well region and over a second substrate 108c in order to control the conductivity within the portion of the third device 110c. As a result, a portion of the second transistor 110c would comprise a first portion within a second well structure 210 in 108c and a second portion above the second well structure and in 118 of 112c in FIG. 22 of Kao.
Further, Kao discloses each 112a, 112b, 112c includes 114, 116 surrounded by dielectric structure 118, [0014].
In the same field of endeavor, Buynoski discloses As shown in FIG. 2, the dielectric material 11 is removed, as with a slightly acidic buffered hydrofluoric acid solution, thereby creating voids or air gaps 20 throughout the interconnection structure. The formation of air gaps 20 significantly reduces the capacitance of the entire interconnection system as the dielectric constant of air is taken as one, Col. 6, lines 35-41.
It would have been obvious to one of ordinary skill in the art to remove the dielectric layer 118 in 112b, 112c in FIG. 22 thereby creating voids or air gaps around the interconnection system (114, 116) in 112b, 112c as taught by Buynoski in order to reduce the capacitance of the interconnection system. As a result, side surfaces of the second portions of 110b, 110c in 112b, 112c would be exposed to air gaps or voids.
In a similar field of endeavor, Brech shows in FIG. 2B a well region 35 extending across a top surface of a substrate 10 for a first transistor 101 and a second transistor 102, [0037],[0045].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form a well layer extending laterally across the substrate 108b (108 in FIG. 7) of Kao by non-selective deposition of a dopant rather than by selective deposition in specific regions above 108b, in order to simplify manufacturing and increase the conductivity of the substrate.
In the same field of endeavor, Gomes discloses that FIG. 11 illustrates some embodiments of the microelectronic assembly 100 where an after-bonding via 140 extends through multiple pairs of IC structures 110 and 120 bonded together. While FIGS. 5-11 illustrate certain arrangements of various components of the IC structures 110 and 120, one or more of the after-bonding interconnects as described with reference to the after-bonding via 140 of FIGS. 5-11 may be provided in any embodiments of the microelectronic assembly 100 as described with reference to FIGS. 1-4, [0094]-[0095].
FIG. 11B shows the after-bonding via extending through two interconnect layers 122 which are part of two respective stacks [0038].
Further, Gomes teaches that Providing one or more after-bonding interconnects may provide significant advantages in terms of its ability to provide electrical connectivity between various components of the microelectronic assembly 100 and/or reduced resistance. Also because of the reduced resistance, the after-bonding interconnects may be referred to as “express interconnects” (e.g., an express via) because they may allow routing power, ground, and/or signals to various components of the microelectronic assembly 100 faster than what would be achieved with the interconnects 112 and 122 that were in the individual IC structures 110, 120 before they were bonded together, [0093].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form at least one after-bonding via 140 extending through IC dies 102, 104, 106 ([0057] in Kao), through the backside of 108b, and to interconnects 114 in 112b to reduce resistance and to allow additional routing of power, ground and/or signals to various components faster than would be achieved by 114, 116 in Kao (see Gomes [0093]). As the via is an after-bonding via 140, it would be formed after the hybrid bonding process in Kao, and would extend through the backside of the widened well layer that extends laterally across the substrate 108b.
RE: Claim 30, Kao in view of Buynosk, Brech, Gomes discloses The method of claim 29, wherein:
the first transistor structure comprises a first portion within the first well structure and a second portion above the first well structure, and the second transistor structure comprises a first portion within the second well structure and a second portion above the second well structure (These limitations are in claim 29; Accordingly, these limitations are met as discussed above for claim 29).
RE: Claim 31, Kao in view of Buynosk, Brech, Gomes discloses The method of claim 29, wherein: the one or more first stacks of layers comprises a plurality of first stacks of layers (Kao FIG. 7 shows at least two stacks of 114, 116 on the left and right of 110),
wherein the first transistor structure is in contact with one of the plurality of first stacks of layers (Kao FIG. 7 shows 110 in contact with the lefthand and righthand stacks 114, 116, [0038]), and
the one or more second stacks of layers comprises a plurality of second stacks of layers (Kao FIG. 22 shows at least two stacks in 112c, one on the left and right of 110c), wherein the second transistor structure is in contact with one of the plurality of second stacks of layers (FIG. 22 shows 110c in contact with the lefthand and righthand stacks).
RE: Claim 33, Kao in view of Buynosk, Brech, Gomes discloses The method of claim 29, wherein the one or more interconnect structures are formed through the first substrate and the first well structure (These limitations are in claim 29; Accordingly, these limitations are met as discussed above for claim 29).
Claim 32 are rejected under 35 U.S.C. 103 as being unpatentable over Kao in view of Buynosk, further in view of Brech, Gomes as applied to claim 29, and further in view of Yeh.
RE: Claim 32, Kao in view of Buynosk, Brech, Gomes does not explicitly disclose The method of claim 29, further comprising:
forming, after joining the at least one of the first hybrid bond layer structure or the first contact structure to the at least one of the second hybrid bond layer structure or the second contact structure, a redistribution layer.
However, in the same field of endeavor, Yeh discloses dies 128 are bonded to the dies 28 through a hybrid bonding process, [0053] and After the dies 128 are bonded to the dies 28 and the dielectric layer 37 is formed, processes described in FIG. 1E are performed to form the RDL structure 50, [0055].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form a redistribution layer (RDL) structure after hybrid bonding 120b and 120c as taught by Yeh in order to increase the number of available connections to 102, 104, and/or 106 for improved signal routing.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL ANGUIANO whose telephone number is (703)756-1226. The examiner can normally be reached Monday through Friday.
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/MICHAEL ANGUIANO/Examiner, Art Unit 2899
/Brent A. Fairbanks/Supervisory Patent Examiner, Art Unit 2899