DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
RE: the objection to the claims, Applicant’s arguments and/or amendments have resolved the prior typographical issues in the claims. Accordingly, the objection to claims 19, 21 is withdrawn.
RE: the objection to the drawings, Applicant’s arguments and/or amendments have resolved the prior issues of claimed subject matter not being shown in the drawings. Accordingly, the objection to the drawings is withdrawn.
RE: the rejection of claim(s) 14-23, 25-27, 29-31, and 33-34 under 35 USC 112(a), Applicant’s arguments and/or amendments have been fully considered and resolve the issues of new matter. Accordingly, the rejection of claim(s) claim(s) 14-23, 25-27, 29-31, and 33-34 has been withdrawn. Claims 24, 28, and 32 are canceled and so the rejection of these claims is moot.
RE: the rejection of claim(s) 14-23, 25-27 and 29-34 under 35 USC 112(b), Applicant’s arguments and/or amendments have been fully considered and resolve the issues of indefiniteness. Accordingly, the rejection of claim(s) 14-23, 25-27, 29-31, and 33-34 has been withdrawn.
RE: the rejection of claim(s) 30, 33 under 35 USC 112(d), Applicant’s arguments and/or amendments have been fully considered and resolve the prior issues of improper dependent claims. Accordingly, the rejection of claim(s) 30, 33 has been withdrawn.
RE: the rejection of claims under 35 USC 103, Applicant’s arguments and/or amendments have been fully considered but are moot as further search and consideration prompted the new grounds of rejection presented herein.
Claim Objections
Claim 31 is objected to because of the following informalities:
Claim 31 includes “wherein the first transistor structure is in contact with [of]]metal layer in of the first stack of metal layers” (which does not include a complete double bracket) which is considered a typographical error of “wherein the first transistor structure is in contact with one metal layer in of the first stack of metal layers.”
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 14-18 are rejected under 35 U.S.C. 103 as being unpatentable over US20180269161A1 (“Wu”) in view of US20190363079A1 (“Thei”), further in view of US20210296281A1 (“Wang”).
RE: Claim 14, Wu discloses A method (FIGS. 1A-1E are cross-sectional views of various stages of a process for forming a hybrid-bonding structure 600A, [0012]), comprising:
forming, over a first surface of a first substrate (upper surface of substrate 100 in 500a’ as represented for 500a in FIG. 1D, which becomes lower surface of 100 in FIG. 1E; structure 500a′ similar to or the same as the structure 500a formed by the aforementioned processes shown in FIG. 1A to FIG. 1E are bonded to the structure 500a vertically to form the hybrid-bonding structure 600A by performing a hybrid-bonding process, as shown in FIG. 1E, [0035]; Accordingly, 500a’ is formed by the same process used to form 500a), a first substructure (112 for 500a’, FIG. 1D) of a first portion of a seal ring structure (104b including 114 in FIG. 1D; the seal ring structure 114 includes conductive layers 112 and vias 108 formed in the dielectric layer 106, [0018]);
forming, over a second substrate (upper surface of substrate 100 in 500a in FIG. 1D), a first substructure (112 for 500a; in FIG. 1E, each of 500a and 500a’ include 112 and 100) of a second portion of the seal ring structure (114);
forming, over the first substructure (112 for 500a’) of the first portion of the seal ring structure, a second substructure (128, 132, 134 for 500a’ in FIG. 1D, [0029]; the conductive line 132 (or the conductive line 134) serves as a bonding layer of the seal ring structure 114 of the structure 500 a, [0029]) of the first portion of the seal ring structure;
forming, over the first substructure (112 for 500a) of the second portion of the seal ring structure, a second substructure (128, 132, 134 for 500a, see FIG. 1D, [0029]) of the second portion of the seal ring structure,
wherein at least one of:
the second substructure of the first portion of the seal ring structure comprises a first hybrid bond contact structure (128 for 500a’ in FIG. 1D), in contact with the first substructure of the first portion of the seal ring structure (128 is in direct contact with 112 in FIG. 1D), and a first hybrid bond layer structure (132) in contact with the first hybrid bond contact structure (132 is in direct contact with 128 in FIG. 1D), or
the second substructure of the second portion of the seal ring structure comprises a second hybrid bond contact structure (128 for 500a in FIG. 1D), in contact with the first substructure of the second portion of the seal ring structure (128 is in direct contact with 112 in FIG. 1D), and a second hybrid bond layer structure (132) in contact with the second hybrid bond contact structure (132 is in direct contact with 128 in FIG. 1D; further, this entire limitation is considered optional due to the presence of the word “or” above; it is therefore met when the limitations preceding the “or” are met);
joining the second substructure of the first portion of the seal ring structure to the second substructure of the second portion of the seal ring structure (a structure 500 a′ similar to or the same as the structure 500 a formed by the aforementioned processes shown in FIG. 1A to FIG. 1E are bonded to the structure 500 a vertically to form the hybrid-bonding structure 600A by performing a hybrid-bonding process, as shown in FIG. 1E, [0035]; FIG. 1E shows 128, 132, 134 of 500a’ bonded to 128, 132, 134 of 500a).
Wu does not explicitly disclose:
forming, after joining the second substructure of the first portion of the seal ring structure to the second substructure of the second portion of the seal ring structure, an interconnect structure comprising:
a first end, extending beyond the first surface of the first substrate, to directly contact the first substructure of the first portion of the seal ring structure, and
a second end, opposite the first end and extending beyond a second surface of the first substrate that is opposite the first surface of the first substrate, to directly contact a redistribution layer.
However, in the same field of endeavor, Thei discloses in FIGs. 13-16:
forming, after joining a second substructure of a first portion of a seal ring structure (118a of seal ring 102, [0020]) to a second substructure of a second portion of the seal ring structure (118b of seal ring 102; FIGs. 12-13 shows second substructures 118a and 118b of seal ring 102 are joined), an interconnect structure (combination of 126, 158a formed in FIGs. 14-16 which is after FIG. 13, [0007], [0021], [0031]) comprising:
a first end (bottom end of 126), extending beyond a first surface (lower surface of substrate 106b, [0020]) of the first substrate (FIG. 16 shows bottom end of 126 extends beyond lower surface of substrate 106b), and
a second end (upper end of 158a), opposite the first end and extending beyond a second surface of the first substrate that is opposite the first surface of the first substrate, to directly contact a redistribution layer (158b; FIG. 16 shows upper end of 158a is opposite bottom end of 126 and extending beyond a top surface of substrate 106b to directly contact a layer 158b; the second pad structure 158 b is/are distinct from, and/or a different material than, the first pad structure 158 a, [0032]).
Thei further discloses The TSV 126 may be further connected to a pad structure 158 in a passivation layer 148 and a solder bump 140 (or other applicable structures) overlying the passivation layer 148 to provide electrical connections and bonding, contacting, or connecting structures. The pad structure 158 may facilitate electrical coupling between the 3D IC 150 and external devices or power source, [0021].
Accordingly, as layer 158b provides electrical connections to external devices or power source, layer 158b functions to redistribute signals or power from external devices or power source and is therefore considered a redistribution layer.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form an interconnect after joining the second substructure of the first portion of the seal ring structure to the second substructure of the second portion of the seal ring structure as taught by Thei in order to provide electrical connections to external devices or power source.
In the same field of endeavor, Wang discloses in FIGs. 2-5:
forming an interconnect (240 in FIG. 4 which is formed after bonding wafers 210, 220 in FIG. 3, [0014]) to directly contact a first substructure (metal layers 212 or 213 or 214, [0023], [0025]) of a first portion of the seal ring structure (the seal ring structure 210 includes the first metal layer 211, the metal layers 212, 213, 214, [0025]; FIG. 4 shows interconnect 240 directly contacting metal layers 212, 213, 214).
Wang further discloses an electrical resistance between the wafers 21, 22 can be decreased via the TSV structure 230 with the conductive filler 240, [0017].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the interconnect to directly contact at least one of the conductive layers 112 in 500a’ in Wu as taught by Wang in order to decrease electrical resistance between 500a and 500a’ as further taught by Wang.
RE: Claim 15, Wu in view of Thei, Wang discloses The method of claim 14, wherein forming the first substructure of the first portion of the seal ring structure comprises:
forming a vertical stack of a plurality of metal layers (In Wu: 112 for 500a’) over the first substrate (Wu discloses conductive layers 112 may include multiple metal layers, [0019], which are formed over 100 in FIG. 1D).
RE: Claim 16, Wu in view of Thei, Wang discloses The method of claim 15,
wherein forming the second substructure of the first portion of the seal ring structure comprises:
forming the first hybrid bond contact structure over the plurality of metal layers (128 of 500a’ is formed over 112 in Wu FIG. 1D), and
forming the first hybrid bond layer structure over the first hybrid bond contact structure (132 of 500a’ is formed over 128 in FIG. 1D of Wu).
RE: Claim 17, Wu in view of Thei, Wang discloses The method of claim 14,
wherein forming the first substructure of the second portion of the seal ring structure comprises:
forming a vertical stack of a plurality of metal layers (In Wu: 112 for 500a) over the second substrate (Wu discloses conductive layers 112 may include multiple metal layers, [0019], which are formed over 100 in FIG. 1D).
RE: Claim 18, Wu in view of Thei, Wang discloses The method of claim 17,
wherein forming the second substructure of the second portion of the seal ring structure comprises:
forming the second hybrid bond contact structure over the plurality of metal layers (128 of 500a would be formed over 112 in Wu, see FIG. 1D), and
forming the second hybrid bond layer structure over the second hybrid bond contact structure (132 of 500a would be formed over 128 in Wu, see FIG. 1D).
Claim(s) 19 is rejected under 35 U.S.C. 103 as being unpatentable over Wu in view of Thei, further in view of Wang as applied to claim 14, further in view of US20190164919A1 (“Hu”).
RE: Claim 19, Wu in view of Thei, Wang does not explicitly disclose The method of claim 14,
wherein joining the second substructure of the first portion of the seal ring structure to the second substructure of the second portion of the seal ring structure comprises:
joining the first hybrid bond layer structure of the first portion of the seal ring structure to the second hybrid bond layer structure of the second portion of the seal ring structure using a eutectic bonding process.
However, in the same field of endeavor, Hu discloses The first semiconductor device 100 and the second semiconductor device 300 may then be subjected to a temperature at or above the eutectic point for material of the first metal pad 121, the second metal pad 122, and the third metal pad 123 of the first semiconductor device 100 and the fourth metal pads 301 of the second semiconductor device 300, e.g., between about 150° C. and about 650° C., to fuse the metal bond pads. In this manner, fusion of the first semiconductor device 100 and the second semiconductor device 300 forms a hybrid bonded device, [0050].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to heat the conductive line 132, 134 in 500, 500’ above the eutectic point as taught by Hu in order to form a hybrid bonded structure including 500a and 500a’ with fused conductive lines which would form a seal against moisture.
Claim(s) 20, 35-36 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu in view of Thei, further in view of Wang as applied to claim 14, further in view of US20140239411A1 (“Brech”).
RE: Claim 20, Wu in view of Thei, Wang does not explicitly disclose The method of claim 14,
wherein forming the interconnect structure comprises:
forming a through-hole that passes through the first substrate and a well structure to expose the first substructure of the first portion of the seal ring structure, and
forming an oxide material within the through-hole.
However, in the same field of endeavor, Brech discloses:
forming an interconnect structure (through-via 50 in FIG. 5D) comprises:
forming a through-hole (80 in FIG. 4C, [0057]) that passes through a first substrate (substrate 10, [0037]) and a well structure (35, [0037]) to expose a conductive layer (60, [0055]), and
forming an oxide material (In FIG. 5D: 155; dielectric liner 155 may comprise an oxide, [0060]) within the through-hole (FIGS. 5A-5D, illustrates a semiconductor device in accordance with an alternative embodiment of the present invention in which the through opening is partially filled, [0059]).
Brech further discloses Embodiments of the present invention minimize parasitic effects significantly by eliminating the parasitic effects associated with the interconnects 55, [0034].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the interconnect by forming a through-hole passing through the first substrate 100 of 500a’ and a well structure, and to form an oxide material in the through hole as taught by Brech in order to minimize parasitic effects significantly as further taught by Brech. As the interconnect would directly contact one of the conductive layers 112 in 500a’, when the through-hole of the interconnect is formed, the through-hole would expose one of the conductive layers 112 in 500a’.
RE: Claim 35, Wu in view of Thei, Wang does not explicitly disclose The method of claim 14, wherein the interconnect structure electrically isolates a well structure of the first substrate from a plurality of metal layers of the first portion of the seal ring structure.
However, in the same field of endeavor, Brech discloses FIG. 11B illustrates an alternative embodiment in which the through vias 50 include an isolation liner 65, [0079].
FIG. 11B shows the isolation liner 65 isolating the well structure 35 and substrate 10 from the conductive fill 150 of the via 50, [0037], [0060], [0079].
Brech further discloses Embodiments of the present invention minimize parasitic effects significantly by eliminating the parasitic effects associated with the interconnects 55, [0034].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the interconnect to include an isolation liner as taught by Brech in order to minimize parasitic effects significantly as further taught by Brech. As a result, the isolation liner would electrically isolate a well structure of the first substrate 100 in 500a’ from a conductive fill of the interconnect, and therefore electrically isolate a well structure of the first substrate from a plurality of metal layers 112 of the first portion of the seal ring structure.
RE: Claim 36, Wu in view of Thei, Wang does not explicitly disclose The method of claim 14, wherein the interconnect structure comprises a dielectric material.
However, in the same field of endeavor, Brech discloses FIG. 5D illustrates a further embodiment including a dielectric liner 155 physically and electrically separating the conductive material in the through via from the substrate 10. The dielectric liner 155 may comprise an oxide or nitride such as silicon oxide or silicon nitride, [0060].
Brech further discloses Embodiments of the present invention minimize parasitic effects significantly by eliminating the parasitic effects associated with the interconnects 55, [0034].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the interconnect to include a dielectric liner as taught by Brech in order to minimize parasitic effects significantly as further taught by Brech.
Claims 21-23, 26-27, and 34 are rejected under 35 U.S.C. 103 as being unpatentable over US20210391302A1 (“Kao”) in view of Thei.
RE: Claim 21, Kao discloses A method (method of forming a backside contact on a backside of a substrate and directly over a semiconductor device within the substrate, [0037], FIGs. 7-22), comprising:
forming a first well structure (210 for device 110b, FIG. 2, [0022], [0038]), over a first surface (interface/boundary between 210 and remaining portions of 108, and upper surface of 108 in FIG. 7) of a first substrate (regions of 108 in FIG. 7 excluding 210, [0038]; 108 in FIG. 7 becomes 108b in FIG. 22 since structure in FIG. 7 gets flipped in FIG. 8 [0040], and structure in FIG. 21 gets relabeled in FIG. 22 so that device 110 in FIG. 21 is labelled as device 110b in FIG. 22, [0055]-[0056]; Accordingly, FIG. 7 shows the first well structure 210 is formed over a first surface of the first substrate 108b), and a second well structure (unlabeled darkened region for 110c in FIG. 22, [0014]), over a second substrate (108c, FIG. 22, [0014]);
forming a first transistor structure (110 in FIG. 7; 110 in FIG. 7 becomes 110b in FIG. 22; 110 is a transistor, [0038]; 110b is a metal oxide semiconductor field effect transistor, [0022]), at least partially within the first well structure (Source/drain regions 202 reside in the doped well region 210, [0022]), and a second transistor structure (110c in FIG. 22, [0056]; 110 is a transistor, [0038]);
forming one or more first stacks of layers (114 in 112, FIG. 7, [0014]; 112 becomes 112b in FIG. 22, [0056]), above the first transistor structure (114 is in 112 which is above 110 in FIG. 7, [0038]), and one or more second stacks of layers (114 in 112c in FIG. 22; Each of the interconnect structures (e.g., 112 a, 112 b, 112 c) may comprise a network of interconnect wires 114 and interconnect vias 116 surrounded by an interconnect dielectric structure 118, [0014]), above the second transistor structure (FIG. 22 shows interconnect structure 112c is above 110c; FIG. 22 shows unlabeled interconnect wires and interconnect vias above device 110c);
forming at least one of a first hybrid bond layer structure (120 in FIG. 7 [0039]; 120 in FIG. 7 becomes 120b in FIG. 22; bonding structures (e.g., 120 a, 120 b, 120 c) are hybrid bond (HB) structures [0014]) or a first contact structure, over the one or more first stacks of layers, and at least one of a second hybrid bond layer structure (120c in FIG. 22) or a second contact structure, over the one or more second stacks of layers;
joining the at least one of the first hybrid bond layer structure or the first contact structure to the at least one of the second hybrid bond layer structure or the second contact structure (a bonding process 2202 may be conducted to form a 3D IC stack, [0056]; the bonding process 2202 may be a hybrid bonding process [0056]; FIG. 22 shows 120b and 120c during the process of joining; FIG. 1 shows 120b, 120c joined).
Kao does not explicitly disclose:
the second transistor structure is formed at least partially within the second well structure;
forming, after joining the at least one of the first hybrid bond layer structure or the first contact structure to the at least one of the second hybrid bond layer structure or the second contact structure, an interconnect structure comprising:
a first end, extending beyond the first surface of the first substrate, to directly contact the one or more first stacks of layers, and
a second end, opposite the first end and extending beyond a second surface of the first substrate that is opposite first surface of the first substrate, to directly contact a redistribution layer.
However, Kao discloses the second semiconductor device 110 b may be, for example, a metal oxide semiconductor field effect transistor (MOSFET), and further that the second semiconductor device 110 b may comprise a doped well region 210 within the second substrate 108 b, wherein the doped well region 210 is more heavily doped and/or has a different doping type than the second substrate 108 b. Source/drain regions 202 may reside in the doped well region 210, and a gate electrode 206 over a gate dielectric layer 208 may be arranged on the frontside 108 bf of the second substrate 108 b, [0022]. Kao further teaches that more than one of the semiconductor devices (110 a, 110 b, 110 c) may be arranged on each of the substrates (108 a, 108 b, 108 c). Kao further teaches transistors are examples of semiconductor devices, [0011]. Further, the darkened unlabeled region in device 110c in FIG. 22 looks substantially the same as the labelled well region 210 in FIG. 2 which is also darkened and has a curved edge, indicating that the device 110c and 110b have substantially the same structure.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the third semiconductor device 110c in substantially the same way as the second semiconductor 110b in order to simplify manufacturing, where both are transistors, with a portion of the third device 110c within a second well region and over a second substrate 108c in order to control the conductivity within the portion of the third device 110c.
In the same field of endeavor, Thei discloses in FIGs. 13-16:
forming, after joining the at least one of the first hybrid bond layer structure (132a, [0018]) or the first contact structure to the at least one of the second hybrid bond layer (132b) structure or the second contact structure (FIGs. 12-13 show the hybrid bonding layers 132a and 132b are hybrid bonded), an interconnect structure (combination of 126, 158a formed in FIGs. 14-16 which is after FIG. 13, [0007], [0021], [0031]) comprising:
a first end (bottom end of 126 in FIG. 16), extending beyond a first surface of a first substrate (lower surface of substrate 106b, [0020]), to directly contact one or more first stacks of layers (112b; FIG. 16 shows bottom end of 126 extends beyond lower surface of substrate 106b to directly contact one or more first stacks of layers 112b, 122t), and
a second end (upper end of 158a), opposite the first end and extending beyond a second surface of the first substrate that is opposite first surface of the first substrate, to directly contact a redistribution layer (158b; FIG. 16 shows upper end of 158a is opposite bottom end of 126 and extending beyond a top surface of substrate 106b to directly contact a layer 158b; the second pad structure 158 b is/are distinct from, and/or a different material than, the first pad structure 158 a, [0032]).
Thei further discloses The TSV 126 may be further connected to a pad structure 158 in a passivation layer 148 and a solder bump 140 (or other applicable structures) overlying the passivation layer 148 to provide electrical connections and bonding, contacting, or connecting structures. The pad structure 158 may facilitate electrical coupling between the 3D IC 150 and external devices or power source, [0021].
Accordingly, as layer 158b provides electrical connections to external devices or power source, layer 158b functions to redistribute signals or power from external devices or power source and is therefore considered a redistribution layer.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form an interconnect after joining the first hybrid bond layer structure and the second hybrid bond layer structure as taught by Thei in order to provide electrical connections to external devices or power source.
RE: Claim 22, Kao in view of Thei discloses The method of claim 21, wherein:
the first transistor structure comprises a first portion within the first well structure and a second portion above the first well structure (Kao FIG. 7 shows a portion of 110 in the well region 210, and a portion of 110 in 112 which is above the well region 210, [0038]), and
the second transistor structure comprises a first portion within the second well structure and a second portion above the second well structure (Kao FIG. 22 shows a first portion of device 110c in a dark unlabelled region corresponding to the well region, and a second portion of device 110c in 112c which is above the well region, [0057]; As modified, 110c would be formed in the same way as 110b and would have a portion in the second well region 210, and a portion above the well second region 210).
RE: Claim 23, Kao in view of Thei discloses The method of claim 21, wherein:
the one or more first stacks of layers comprises a plurality of first stacks of layers (Kao FIG. 7 shows at least two stacks of 114, 116 on the left and right of 110),
wherein the first transistor structure is in contact with one of the plurality of first stacks of layers (Kao FIG. 7 shows 110 in contact with the lefthand and righthand stacks 114, 116, [0038]), and
the one or more second stacks of layers comprises a plurality of second stacks of layers (Kao FIG. 22 shows at least two stacks in 112c, one on the left and right of 110c),
wherein the second transistor structure is in contact with one of the plurality of second stacks of layers (FIG. 22 shows 110c in contact with the lefthand and righthand stacks).
RE: Claim 26, Kao in view of Thei discloses The method of claim 21, wherein the redistribution layer (Thei FIG. 16: 158b) resides above the interconnect structure (Thei FIG. 16: 158a, 126), the first substrate (Thei FIG. 16: 106b; In Thei FIG. 16, 158b resides above 158a, 126 and substrate 106b; Accordingly as modified, the redistribution layer 158b would reside above the interconnect structure and the first substrate 108b in Kao).
Kao in view of Thei does not explicitly disclose wherein the redistribution layer resides above the first well structure.
However, in the same field of endeavor, Brech teaches in FIG. 3B:
wherein a redistribution layer (120, 70, [0052], [0056]) resides above a first well structure (35, [0037]).
Brech further teaches Referring to FIG. 3B, an inter level dielectric layer 110 may be disposed over the gate line 20. Contact plugs 120 may be formed within the inter level dielectric layer 110 to couple the regions of the transistors. Thus, the contact plugs 120 may be coupled to the plurality of source regions 30 and the plurality of drain regions 40 through the contact layer 60, [0052].
Brech further teaches The plurality of through vias 50 may extend through the conductive layer 70. Thus, the conductive layer 70 is electrically coupled to a through via of the plurality of through vias 50. As illustrated in FIG. 3B, the conductive layer 70 extends over the top surface of the contact layer 60 and thus provides a larger contact area between the through via and the contact layer 60. Thus, the conductive layer 70 may reduce the contact resistance between the contact layer 60 and the through via 50, [0051].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the redistribution layer to reside above the first well structure as taught by Brech in order to provide electrical contacts to the source and drain regions of the transistor 110b in Kao.
RE: Claim 27, Kao in view of Thei discloses The method of claim 21,
wherein the interconnect structure comprises a plurality of interconnect structures in contact with different first stacks of layers of the one or more first stacks of layers (Brech teaches The TSV coupling structure 152 also comprises a TSV 126 touching a metal layer 122 t, [0021]; the pad structure 158 comprises a first pad structure 158 a extending through the first passivation sub-layer 148 a to the TSV 126, [0051]; Brech FIGs. 1-4 show a plurality of interconnect structures 158a, 126 in contact with different stacks of layers 122t, 122b; Accordingly, as modified by Brech, the interconnect comprises a plurality of interconnect structures in contact with different first stacks of layers of the one or more first stacks of layers).
RE: Claim 34, Kao in view of Thei discloses The method of claim 21,
wherein the interconnect structure resides over the one or more first stacks of layers, the one or more second stacks of layers, the at least one of the first hybrid bond layer structure or the first contact structure, and the at least one of the second hybrid bond layer structure or the second contact structure (Brech FIGs. 4-5 shows wherein an interconnect structure 158a, 126 resides over one or more first stacks of layers 122t, 122b, one or more second stacks of layers 122t, 122b, at least one of a first hybrid bond layer structure 132a, and at least one of the second hybrid bond layer structure 132b, [0048]; Accordingly, as modified by Brech, the interconnect structure resides over the one or more first stacks of layers in 112b, the one or more second stacks of layers in 112c, the at least one of the first hybrid bond layer structure 120b, and the at least one of the second hybrid bond layer structure 120c in Kao).
Claim 25 is rejected under 35 U.S.C. 103 as being unpatentable over Kao in view of Thei as applied to claim 21, further in view of Brech.
RE: Claim 25, Kao in view of Thei does not explicitly disclose The method of claim 21, wherein the interconnect structure is formed through the first substrate and the first well structure.
However, in the same field of endeavor, Brech discloses:
wherein an interconnect structure (through-via 50 in FIG. 5D) is formed through a first substrate (substrate 10, [0037]) and a first well structure (35, [0037]).
Brech further discloses Embodiments of the present invention minimize parasitic effects significantly by eliminating the parasitic effects associated with the interconnects 55, [0034].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the interconnect through the first substrate 108b and first well structure 210 as taught by Brech in order to minimize parasitic effects significantly as further taught by Brech.
Claims 29-31, 33 are rejected under 35 U.S.C. 103 as being unpatentable over Kao in view of Thei, further in view of Brech.
RE: Claim 29, Kao discloses A method of forming a stacked-die structure (method of forming a backside contact on a backside of a substrate and directly over a semiconductor device within the substrate, [0037], FIGs. 7-22), comprising:
forming a first well structure (210 for device 110b, FIG. 2, [0022], [0038]), over a first surface (interface/boundary between 210 and remaining portions of 108, and upper surface of 108 in FIG. 7) of a first substrate (regions of 108 in FIG. 7 excluding 210, [0038]; 108 in FIG. 7 becomes 108b in FIG. 22 since structure in FIG. 7 gets flipped in FIG. 8 [0040], and structure in FIG. 21 gets relabeled in FIG. 22 so that device 110 in FIG. 21 is labelled as device 110b in FIG. 22, [0055]-[0056]; Accordingly, FIG. 7 shows the first well structure 210 is formed over a first surface of the first substrate 108b), and a second well structure (unlabeled darkened region for 110c in FIG. 22, [0014]), over a second substrate (108c, FIG. 22, [0014]);
forming a first transistor structure (110 in FIG. 7; 110 in FIG. 7 becomes 110b in FIG. 22; 110 is a transistor, [0038]; 110b is a metal oxide semiconductor field effect transistor, [0022]);
forming a second transistor structure (110c in FIG. 22, [0056]; 110 is a transistor, [0038]);
forming a first stack of layers (114 in 112, FIG. 7, [0014]; 112 becomes 112b in FIG. 22, [0056]) above the first transistor structure (114 is in 112 which is above 110 in FIG. 7, [0038]);
forming a second stack of layers (114 in 112c in FIG. 22; Each of the interconnect structures (e.g., 112 a, 112 b, 112 c) may comprise a network of interconnect wires 114 and interconnect vias 116 surrounded by an interconnect dielectric structure 118, [0014]) above the second transistor structure (FIG. 22 shows interconnect structure 112c is above 110c; FIG. 22 shows unlabeled interconnect wires and interconnect vias above device 110c);
forming, above the first stack of layers, at least one of a first hybrid bond layer structure (120 in FIG. 7 which is above 114 in 112 [0039]; 120 in FIG. 7 becomes 120b in FIG. 22; bonding structures (e.g., 120 a, 120 b, 120 c) are hybrid bond (HB) structures [0014]) or a first contact structure;
forming, above the second stack of layers, at least one of a second hybrid bond layer structure (120c in FIG. 22 which is above stacks 114 in 112c) or a second contact structure;
joining the at least one of the first hybrid bond layer structure or the first contact structure to the at least one of the second hybrid bond layer structure or the second contact structure (a bonding process 2202 may be conducted to form a 3D IC stack, [0056]; the bonding process 2202 may be a hybrid bonding process [0056]; FIG. 22 shows 120b and 120c during the process of joining; FIG. 1 shows 120b, 120c joined).
Kao does not explicitly disclose:
the first transistor structure, the second transistor structure, the first stack of layers, the second stack of layers, the first hybrid bond layer structure or the first contact structure, and the second hybrid bond layer structure or the second contact structure are formed within a device region of a stacked die structure;
forming, after joining the at least one of the first hybrid bond layer structure or the first contact structure to the at least one of the second hybrid bond layer structure or the second contact structure, an interconnect structure comprising:
a first end, extending beyond the first surface of the first substrate, to directly contact the first well structure, and
a second end, opposite the first end and extending beyond a second surface of the first substrate that is opposite first surface of the first substrate, to directly contact a redistribution layer.
In the same field of endeavor, Thei discloses in FIG. 5:
a first transistor structure (302a in 108a; 302a, 302b maybe be MOSFETs, [0028]; Kao discloses MOSFETs are transistors, [0022]), a second transistor structure (302b in 108b), a first stack of layers (162a in 108a, [0035]), a second stack of layers (162b in 108b, [0035]), a first hybrid bond layer structure (portion of 132a in 150; 132a, 132b are hybrid bonding layers, [0018]), and a second hybrid bond layer structure (portion of 132b in 150) are formed within a device region (150, [0019]) of a stacked die structure (stacked die of 104a, 104b, [0018]; FIG. 5 shows 302a, 302b, 162a, 162b, and portions of 132a, 132b in integrated circuit region 150).
Thei discloses The seal-ring structure 102 laterally encloses the 3D IC 150 (shown in FIG. 1) of the first and second IC dies 104 a, 104 b, and extends respectively from the first semiconductor substrate 106 a to the second semiconductor substrate 106 b, such that the seal-ring structure 102 defines a wall or barrier protecting the 3D IC 150, [0019].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the first transistor structure 110b, the second transistor structure 110c, the first stack of layers 114 in 112b, the second stack of layers 114 in 112c, the first hybrid bond layer structure 120b, and the second hybrid bond layer structure 120c within a device region of a stacked die structure with a seal ring as taught by Thei in order to define a wall or barrier protecting the first transistor structure, the second transistor structure, the first stack of layers, the second stack of layers, the first hybrid bond layer structure, and the second hybrid bond layer structure.
Thei further discloses in FIGs. 13-16:
forming, after joining the at least one of the first hybrid bond layer structure (132a, [0018]) or the first contact structure to the at least one of the second hybrid bond layer structure (132b) or the second contact structure (FIGs. 12-13 show the hybrid bonding layers 132a and 132b are hybrid bonded), an interconnect structure (combination of 126, 158a formed in FIGs. 14-16 which is after FIG. 13, [0007], [0021], [0031]) comprising:
a first end (bottom end of 126 in FIG. 16), extending beyond the first surface of the first substrate (lower surface of substrate 106b, [0020]), and
a second end (upper end of 158a), opposite the first end and extending beyond a second surface of the first substrate that is opposite first surface of the first substrate, to directly contact a redistribution layer (158b; FIG. 16 shows upper end of 158a is opposite bottom end of 126 and extending beyond a top surface of substrate 106b to directly contact a layer 158b; the second pad structure 158 b is/are distinct from, and/or a different material than, the first pad structure 158 a, [0032]).
Thei further discloses The TSV 126 may be further connected to a pad structure 158 in a passivation layer 148 and a solder bump 140 (or other applicable structures) overlying the passivation layer 148 to provide electrical connections and bonding, contacting, or connecting structures. The pad structure 158 may facilitate electrical coupling between the 3D IC 150 and external devices or power source, [0021].
Accordingly, as layer 158b provides electrical connections to external devices or power source, layer 158b functions to redistribute signals or power from external devices or power source and is therefore considered a redistribution layer.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form an interconnect after joining the first hybrid bond layer structure and the second hybrid bond layer structure as taught by Thei in order to provide electrical connections to external devices or power source.
In the same field of endeavor, Brech discloses in FIG. 5D:
an interconnect (50, [0043]) having a first end, (top end) extending beyond a first surface of a first substrate (top surface of 10, [0031]), to directly contact a first well structure (35, [0037]).
FIG. 5D shows the interconnect 50 extending through the well structure 35 and the substrate 10.
Brech further discloses Embodiments of the present invention minimize parasitic effects significantly by eliminating the parasitic effects associated with the interconnects 55, [0034].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the interconnect to directly contact the first well structure as taught by Brech in order to minimize parasitic effects significantly as further taught by Brech.
RE: Claim 30, Kao in view of Thei, Brech discloses The method of claim 29, wherein:
the first transistor structure comprises a first portion within the first well structure and a second portion above the first well structure (Kao FIG. 7 shows a portion of 110 in the well region 210, and a portion of 110 in 112 which is above the well region 210, [0038]), and
the second transistor structure comprises a first portion within the second well structure and a second portion above the second well structure (Kao discloses the second semiconductor device 110 b may be, for example, a metal oxide semiconductor field effect transistor (MOSFET), and further that the second semiconductor device 110 b may comprise a doped well region 210 within the second substrate 108 b, wherein the doped well region 210 is more heavily doped and/or has a different doping type than the second substrate 108 b. Source/drain regions 202 may reside in the doped well region 210, and a gate electrode 206 over a gate dielectric layer 208 may be arranged on the frontside 108 bf of the second substrate 108 b, [0022]. Kao further teaches that more than one of the semiconductor devices (110 a, 110 b, 110 c) may be arranged on each of the substrates (108 a, 108 b, 108 c). Kao further teaches transistors are examples of semiconductor devices, [0011]. Further, the darkened unlabeled region in device 110c in FIG. 22 looks substantially the same as the labelled well region 210 in FIG. 2 which is also darkened and has a curved edge, indicating that the device 110c and 110b have substantially the same structure.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the third semiconductor device 110c in substantially the same way as the second semiconductor 110b in order to simplify manufacturing, where both are transistors, with a portion of the third device 110c within a second well region and over a second substrate 108c in order to control the conductivity within the portion of the third device 110c. As a result, a portion of the second transistor 110c would comprise a first portion within a second well structure 210 in 108c and a second portion above the second well structure and in 118 of 112c in FIG. 22 of Kao).
RE: Claim 31, Kao in view of Thei, Brech discloses The method of claim 29, wherein:
the first stack of layers comprises a first stack of metal layers (Kao FIG. 7 shows at least two stacks of 114, 116 on the left and right of 110),
wherein the first transistor structure is in contact with [of]]metal layer in of the first stack of metal layers (Kao FIG. 7 shows 110 in contact with the lefthand and righthand stacks 114, 116, [0038]), and
the second stack of layers comprises a second stack of metal layers (Kao FIG. 22 shows at least two stacks in 112c, one on the left and right of 110c),
wherein the second transistor structure is in contact with one metal layer in the second stack of metal layers (FIG. 22 shows 110c in contact with the lefthand and righthand stacks).
RE: Claim 33, Kao in view of Thei, Brech discloses The method of claim 29,
wherein the interconnect structure is formed through the first substrate and the first well structure (Brech FIG. 5D shows the interconnect 50 extending through the well structure 35 and the substrate 10; Accordingly, as modified, the interconnect structure is formed through the first substrate 108b and first well structure 210 in Kao).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL ANGUIANO whose telephone number is (703)756-1226. The examiner can normally be reached Monday through Friday.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brent Fairbanks can be reached at (408) 918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MICHAEL ANGUIANO/Examiner, Art Unit 2899
/Brent A. Fairbanks/Supervisory Patent Examiner, Art Unit 2899
Prosecution Insights