DETAILED ACTION
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 5-7 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claim 5, the limitation “the interface vertically extends across the terminal of the protruding portion of the solder element,” does not appear to have support in the originally filed disclosure. Specifically, it is noted that drawings are not to scale and it can therefore not be ascertained where the interface will lie relative to the terminal of the protruding portion.
Note the dependent claims necessarily inherit the indefiniteness of the claims on which they depend.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 23 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 23, the limitation “the conductive pillars,” is unclear as to how it is related to the singular conductive pillar recited in claim 1.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1 and 3-8, 10-16, 18-21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (US 2016/0056087; herein “Wu”) in view of Funaya et al. (JP 2007-128982, using machine translation previously provided; herein “Funaya”) and Furuichi (US 20190067224; herein “Furuichi”).
Regarding claim 1, Wu discloses in Fig, 12A and related text package structure, comprising:
a first redistribution structure (e.g. 110, see [0040]);
a second redistribution structure (e.g. 402, see [0040) over the first redistribution structure;
a semiconductor chip (302, see [0040]) between the first redistribution structure and the second redistribution structure;
a protective layer (e.g. 204 and portion of 502 surrounding the chip and adjacent to the solder elements, see [0028], [0019]; see also Fig. 4) surrounding the semiconductor chip; and
a conductive structure (e.g. 202 and 414, see [0040]-[0041]) surrounded by the protective layer, wherein the conductive structure comprises a solder element (414, see [0027]) and a conductive pillar (202), the conductive pillar has a first end and a second end, the first end (e.g. top end) is between the second end (e.g. bottom end) and the solder element, the solder element has a protruding portion extending from an interface between the conductive pillar and the solder element towards the second end, and a terminal of the protruding portion is vertically between the first end and the second end (see Fig. 12A), and the protective layer continuously extends along the sidewall of the conductive pillar from the second end of the conductive pillar towards the first end of the conductive pillar (e.g. 204+504 extend continuously from bottom end of 202 towards top end of 202), wherein the protective layer is a single layer (e.g. “layer” interpreted as “thickness of material,” see [0019] and [0028]), and an entirety of the protective layer (204 and 502) is a polymer material (see [0019] and [0028]).
Wu does not disclose
the protruding portion of the solder element has an inner sidewall, the inner sidewall and a sidewall of the conductive pillar define an acute angle, and the acute angle is greater than zero;
the polymer material filled with fillers dispersed in the polymer material.
In the same field of endeavor, Funaya teaches in Fig. 8 and related text a package structure comprising a solder element (3, see abstract at least) wherein
a protruding portion of the solder element has an inner sidewall (inner sidewall at constriction 10, see pg. 7, para. 12), the inner sidewall and a sidewall of the conductive pillar (sidewall of 2/6) define an acute angle, and the acute angle is greater than zero (see Fig. 8).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Wu by having the protruding portion of the solder element has an inner sidewall, the inner sidewall and a sidewall of the conductive pillar define an acute angle, and the acute angle is greater than zero, as taught by Funaya, in order to achieve a solder element with good connection, reduced short circuit, and high reliability (see Funaya pg. 3, para. 7).
In the same field of endeavor, Furuichi teaches in Fig. 1A and related text a package structure comprising a protective layer (24 and 70, see [0066] and [0072]), an entirety of the protective layer is a polymer material (see [0066] and [0072])
the polymer material filled with fillers (see [0066] and [0072]) dispersed in the polymer material.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Wu by having the polymer material filled with fillers dispersed in the polymer material, as taught by Furuichi, in order to alter the characteristics of the protective layer, e.g. to alter the thermal characteristics of the layers.
Regarding claim 3, the combined device shows the protruding portion of the solder element (Wu: 414; Funaya: 8) laterally and partially surrounds a sidewall of the conductive pillar (Wu: 202; Funaya: 2/6) (Wu: see Fig. 12A; Funaya: see Fig. 8).
Regarding claim 4, the combined devices shows wherein the solder element (Wu: 414) has a first side surface extending into the second redistribution structure (e.g. vertical surface of 414 which extends into 402, which is interpreted as a portion of the second redistribution structure, to contact 418; see also Fig. 4 and [0024]), the solder element has a second side surface extending along a bottom surface of the second redistribution structure (e.g. horizontal surface of 414 which is in contact with 418), the first side surface and the second side surface define an angle, and the angle is in a range from about 90 degrees to about 140 degrees (e.g. about 90 degrees, see Fig. 12A).
Regarding claim 5, Wu further discloses
connectors (e.g. 304, see [0020) between the semiconductor chip (302) and the first redistribution structure (110); and
an underfill layer (e.g. portion of 502 between 302 and 110) between the connectors and the protective layer, wherein an interface is between the underfill layer and the protective layer (the interface is interpreted as the boundary between the portion of 502 between 302 and 110 and the portion surrounding the chip; note that Applicant’s disclosure recites the same materials for the underfill layer and the protective layer, see [0057] and [0063], thus the structure taught by the art is understood to be the same as the structure having two contiguous layers of the same material);
and the interface vertically extends across the terminal of the protruding portion of the solder element (note that the underfill layer and protective layer can be chosen as portions of 505 such that the claimed limitation is taught).
Regarding claim 6, Wu further discloses wherein the conductive pillar (202) is between the first redistribution structure (110) and the solder element (414).
Regarding claim 8, the combined device shows a portion of the protective layer is between the protruding portion of the solder element and the conductive pillar, and the portion of the protective layer is vertically between the interface between the conductive pillar and the solder element and the terminal of the protrusion portion (note that the protective layer of Wu would be understood to fill in the space defined by the acute angle of Funaya in the combined device).
Regarding claim 10, the combined device shows wherein the protruding portion of the solder element (Wu: 414; Funaya: 8) continuously surrounds the conductive pillar (Wu: 202; Funaya: 2/6) (in one example interpretation, it would be apparent to one of ordinary skill that the pillar is inset into the solder such that the solder “continuously surrounds” the pillar in a plan view; in another example interpretation the “protruding portion” is interpreted to include the portion directly above 2/6 and the portion extending downward along constriction 10 such that the portion surrounds the end of 2/6 in a continuous fashion, i.e. not discontinuous).
Regarding claim 21, the combined device shows wherein the terminal of the protruding portion is spaced apart from the conductive pillar (Funaya: terminal of portion protruding from constriction 10 is spaced apart from 2/6, see Fig. 8).
Regarding claim 11, Wu discloses in Fig, 12B and related text package structure, comprising:
a first redistribution structure (e.g. 402, see [0040);
a second redistribution structure (e.g. 110, see [0040]) over the first redistribution structure;
a semiconductor chip (302, see [0040]) between the first redistribution structure and the second redistribution structure;
a conductive pillar (e.g. 202, see [0040]-[0041]) bonded with the first redistribution structure;
a solder element (e.g. 414, see [0027, [040]-[0041]) bonded with the second redistribution structure, wherein the solder element has a protruding portion extending towards the first redistribution structure and extending across an end of the conductive pillar; and
a protective layer (e.g. 204 and portion of 502 surrounding the chip and adjacent to the solder elements, see [0028], [0019]; see also Fig. 4) surrounding the semiconductor chip, the solder element, and the conductive pillar, wherein the protective layer continuously extends along the sidewall of the conductive pillar from the second end of the conductive pillar towards the first redistribution structure (e.g. 204+504 extend continuously from bottom end of 202 towards 402), the protective layer is a single layer (e.g. “layer” interpreted as “thickness of material,” see [0019] and [0028]), an entirety of the protective layer (204 and 502) is a polymer material (see [0019] and [0028]), and an entirety of the solder element is embedded in the protective layer.
Wu does not disclose
a portion of the protective layer is between an inner sidewall of the protruding portion of the solder element and the conductive pillar;
the polymer material filled with fillers dispersed in the polymer material.
In the same field of endeavor, Funaya teaches a protruding portion with a nonzero angle between the inner sidewall of the protruding portion of the solder element and the conductive pillar in substantially the same manner and for the same reasons as applied to claim 1 above. The limitation “a portion of the protective layer is between an inner sidewall of the protruding portion of the solder element and the conductive pillar,” is therefore taught because the protective layer of Wu would be understood to fill in the space defined by the acute angle of Funaya in the combined device.
In the same field of endeavor, Furuichi teaches the polymer material filled with fillers dispersed in the polymer material in substantially the same manner and for the same reasons as applied to claim 1 above.
Regarding claim 12, the combined device shows wherein a terminal of the protruding portion is spaced apart from the conductive pillar (Funaya: terminal of portion protruding from constriction 10 is spaced apart from 2/6, see Fig. 8).
Regarding claim 13, Wu further discloses wherein the conductive pillar (202) is closer to the first redistribution structure (402) than the solder element (414).
Regarding claim 14, the combined device shows wherein the protruding portion of the solder element has an inner sidewall, and the inner sidewall and a sidewall of the conductive pillar define an acute angle (Funaya: see Fig. 8).
Regarding claim 15, Wu further discloses wherein the protective layer (502+204) is in direct contact with the solder element (414) and the conductive pillar (202).
Regarding claim 16, Wu discloses in Fig, 12A and related text package structure, comprising:
a first redistribution structure (e.g. 110, see [0040]);
a second redistribution structure (e.g. 402, see [0040) over the first redistribution structure;
a semiconductor chip (302, see [0040]) between the first redistribution structure and the second redistribution structure;
a conductive pillar (e.g. 202, see [0040]-[0041]) bonded with the first redistribution structure; and
a solder element (e.g. 414, see [0027, [040]-[0041]) bonded with the second redistribution structure, wherein the solder element has a protruding portion extending towards the first redistribution structure and extending past an end of the conductive pillar (e.g. extends past the top end of 202) and, and the conductive pillar is closer to the first redistribution structure (110) than the solder element (414) (see Fig. 12A); and
a protective layer (e.g. 204 and portion of 502 surrounding the chip and adjacent to the solder elements, see [0028], [0019]; see also Fig. 4) surrounding the semiconductor chip, wherein the protective layer continuously extends along the sidewall of the conductive pillar from the second end of the conductive pillar towards the first end of the conductive pillar (e.g. 204+504 extend continuously from bottom end of 202 towards top end of 202), and the protective layer is a single layer (e.g. “layer” interpreted as “thickness of material,” see [0019] and [0028]), an entirety of the protective layer (204 and 502) is made of a molding material (see [0019] and [0028]).
Wu does not disclose
a terminal of the protruding portion of the solder element is spaced apart from the conductive pillar;
a portion of the protective layer is between an inner sidewall of the protruding portion of the solder element and the conductive pillar,
the molding with dispersed fillers.
In the same field of endeavor, Funaya and Furuichi teach the remaining limitation in substantially the same manner and for the same reasons as applied to claims 1 and 11 above.
Regarding claim 18, the combined device shows wherein the protective layer (Funaya: 502) is in direct contact with the protruding portion of the solder element (see Fig. 12A).
Regarding claim 19, Wu further discloses wherein the semiconductor chip (302) is bonded with the first redistribution structure (110) (see Fig. 12A).
Regarding claim 20, the combined device shows wherein the protruding portion of the solder element has an inner sidewall, and the inner sidewall and a sidewall of the conductive pillar define an acute angle (Funaya: see Fig. 8).
Regarding claim 22, the combined device shows wherein the solder element has a first portion (Funaya: e.g. portion in contact with 2 in the interpretation where the solder element further comprises 4) and a second portion (e.g. remaining portion), the first portion of the solder element is laterally surrounded by the second redistribution structure (1 and 2), the second portion of the solder element is laterally surrounded by the protective layer, and the second portion of the solder element extends across an interface between the first portion of the solder element and the second redistribution structure (e.g. the widest portion of 3/4 extends laterally across the interface between 2 and 4).
Regarding claims 1 (second interpretation), 5 (second interpretation) and 7, Wu discloses in Fig. 7 and related text package structure, comprising:
a first redistribution structure (e.g. 110, see [0013]);
a second redistribution structure (e.g. 402, see [0021]) over the first redistribution structure;
a semiconductor chip (302, see [0020]) between the first redistribution structure and the second redistribution structure;
a protective layer (e.g. 204 and portion of 502 surrounding the chip and adjacent to the solder elements, see [0028], [0019]; see also Fig. 4) surrounding the semiconductor chip; and
a conductive structure (e.g. 202/416 and 414, see [0017], [0021] and [0027]) surrounded by the protective layer, wherein the conductive structure comprises a solder element (414, see [0027]) and a conductive pillar (202), the conductive pillar has a first end and a second end, the first end (e.g. top end) is between the second end (e.g. bottom end) and the solder element, the solder element has a protruding portion extending from an interface between the conductive pillar and the solder element towards the second end, and a terminal of the protruding portion is vertically between the first end and the second end (see Fig. 7), wherein the protective layer is a single layer, and the protective layer continuously extends along the sidewall of the conductive pillar from the second end of the conductive pillar towards the first end of the conductive pillar (e.g. 204+504 extend continuously from bottom end of 202 towards top end of 202), wherein the protective layer is a single layer (e.g. “layer” interpreted as “thickness of material,” see [0019] and [0028]), and an entirety of the protective layer (204 and 502) is a polymer material (see [0019] and [0028]).
In the same field of endeavor, Funaya and Furuichi teach the remaining limitation in substantially the same manner and for the same reasons as applied to claim 1 above.
Regarding claim 5, Wu further discloses
connectors (e.g. 304, see [0020) between the semiconductor chip (302) and the first redistribution structure (110); and
an underfill layer (e.g. portion of 502 between 302 and 110) between the connectors and the protective layer, wherein an interface is between the underfill layer and the protective layer (the interface is interpreted as the boundary between the portion of 502 between 302 and 110 and the portion surrounding the chip; note that Applicant’s disclosure recites the same materials for the underfill layer and the protective layer, see [0057] and [0063], thus the structure taught by the art is understood to be the same as the structure having two contiguous layers of the same material);
and the interface vertically extends across the terminal of the protruding portion of the solder element (note that the underfill layer and protective layer can be chosen as portions of 505 such that the claimed limitation is taught).
Regarding claim 7, Wu further discloses wherein the interface between the conductive pillar and the solder element (between 202 and between 414 or 416 and 414) is vertically between a top surface of the semiconductor chip and a bottom surface of the semiconductor chip (see Fig. 7).
Claim(s) 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu in view of Funaya and Furuichi, as applied to claim 1 (second interpretation) above, and further in view of Yu et al. (US 20140131894; herein “Yu”).
Regarding claim 23, the combined device shows wherein the first redistribution structure has a plurality of first conductive vias, each of the conductive vias has a top and a bottom, and the second end of the conductive pillar is vertically between the top and the solder element, wherein the first end and the second end of the conductive pillars (are vertically between opposite surfaces of the protective layer (see Fig. 7), but does not explicitly show a wider top and a narrower bottom.
In the same field of endeavor, Yu teaches in Fig. 2 and related text a semiconductor device having a first redistribution structure with a plurality of first conductive vias (14, see [0012]), each of the conductive vias a wider top and a narrower bottom (see Fig. 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Wu by having each of the conductive vias with a wider top and a narrower bottom, as shown by Yu, in order to employ a well-known tapered shape of the vias and to allow for improved fill and reduced voids in the vias. Additionally, it would have been an obvious matter of design choice to have the tapered shape, since such a modification would have involved a mere change in the shape of a component. A change in shape is generally recognized as being within the level of ordinary skill in the art. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). See MPEP 2144.04
Response to Arguments
Applicant's arguments filed 1/30/2026 have been fully considered but are moot in view of the new grounds of rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Lauren R Bell whose telephone number is (571)272-7199. The examiner can normally be reached M-F 8am-5pm.
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/LAUREN R BELL/Primary Examiner, Art Unit 2896 2/27/2026