DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 8/18/2025 has been entered.
Claim status
Prior rejection of Claims 1-3, 5-6 and 28-29 under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, are withdrawn in view of applicant’s amendments to claims 1, 8 and 21.
Claims 1, 3, 5-8, 10, 12-13, 21-22, and 24-36 are being examined in this office action.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1, 3, 5-6 and 30-32 rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 recite the limitation wherein “a sacrificial layer comprising a second semiconductor material dissimilar from the first semiconductor material over the first surface of the structured substrate to fill in the patterned structure”. The original application does not teach that the sacrificial layer (142, Fig. 2f) fills in the pattern structure (pattern structure on the surface 128 of the substrate 122, Figs. 2b/c and 2f). There is no disclosure or figure that supports that the sacrificial structure fills in the patterned structure, hence introducing “new matter”, and therefore rejected.
Claims 3, 5-6 and 30-32 depend from claim 1 and are rejected at least for the reasons above.
Claim Rejections - 35 USC § 102
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Preble et al. (US 2010/0327291 A1, newly cited).
Re Claim 1, Preble teaches a method of making a semiconductor device comprising:
providing a structured substrate (904+908+912, Fig. 9, para [0086]) comprising a first semiconductor material (908 is AlN, Fig. 9) and a patterned structure over a first surface of the structured substrate (pitted top surface of 904+908+912, see Fig. 9);
forming a sacrificial layer (916, Fig. 9, para [0086]) comprising a second semiconductor material (916 is GaN layer) dissimilar from the first semiconductor material (1st material is AlN) over the first surface of the structured substrate (pitted top surface of 904+908+912) to fill in the patterned structure (916 GaN layer fills in the pitted surface, see Fig. 9, para [0086]) and provide a planar surface (top planar surface of 916 GaN layer);
forming a first semiconductor layer (920 GaN layer, Fig. 9, para [0086]) comprising the second semiconductor material (2nd material is GaN) dissimilar from the first semiconductor material (1st material is AlN) over the planar surface of the sacrificial layer (top planar surface of 916 GaN layer) with defects induced from the dissimilar first semiconductor material and second semiconductor material being formed in the sacrificial layer (lateral cracks are formed in the 916 GaN layer, para [0096]) by nature of the patterned structure (see para [0093]); and
removing the structured substrate (904+908+912, see Fig. 9) and sacrificial layer (916, see Fig. 9) leaving the first semiconductor layer (940, which is initially part of 920 GaN layer, see paras [0086] – [0087]) substantially defect-free as the patterned structure removed defects (layer 940 is substantially crack-free, para [0087]).
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 7-8 and 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Mishra et al. (US 2008/0296617 A1, newly cited), and further in view of Preble et al. (US 2010/0327291 A1, newly cited).
Re Claim 7, Mishra teaches a method of making a semiconductor device, comprising:
forming a first semiconductor layer (202, GaN layer, Fig. 2, para [0038]) comprising a second semiconductor material (2nd material is GaN);
forming a second semiconductor layer (212 SiGe layer, Fig. 2, paras [0038] – [0039]) over the first semiconductor layer (202); and
forming an electrical component in the second semiconductor layer (transistor device is formed in layer 212).
Mishra discloses that that 202 GaN layer is wafer bonded to the 212 SiGe layer but does not disclose how the GaN layer is made.
In a related semiconductor art, Preble teaches a process of making high quality GaN layer:
providing a structured substrate (904+908+912, Fig. 9, para [0086]) comprising a first semiconductor material (908 is AlN, Fig. 9) and a patterned structure over a first surface of the structured substrate (pitted top surface of 904+908+912, see Fig. 9);
forming a first semiconductor layer (920 GaN layer, Fig. 9, para [0086]) comprising a second semiconductor material (2nd material is GaN) dissimilar from the first semiconductor material (1st material is AlN) over the structured substrate (pitted top surface of 904+908+912);
removing the structured substrate (904+908+912, see Fig. 9) leaving the first semiconductor layer substantially defect-free (940, which is initially part of 920 GaN layer, is substantially crack-free, see paras [0086] – [0087]);
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to make the GaN layer of Mishra using the method disclosed by of Preble, as it is a well-known process of making a high quality GaN layer for a transistor device. The use of a known process for its known purpose to yield predictable results is prima facie obvious. Also see KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007). Additionally, the selection of a known process based on its suitability for its intended use supports a prima facie obviousness determination as established in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945), see MPEP 2144.07.
Re Claim 8, Mishra modified by Preble teaches the method of claim 7, further including forming a sacrificial layer (916, Fig. 9, para [0086], Preble) comprising the second semiconductor material (916 is GaN layer, Preble) dissimilar from the first semiconductor material (1st material is AlN) over the first surface of the structured substrate (pitted top surface of 904+908+912, Fig. 9, Preble).
Re Claim 21, Mishra teaches a method of making a semiconductor device, comprising:
forming a first semiconductor layer (202, GaN layer, Fig. 2, para [0038]) comprising a second semiconductor material (2nd material is GaN);
forming a second semiconductor layer (212 SiGe layer, Fig. 2, paras [0038] – [0039]) over the first semiconductor layer (202); and
forming an electrical component in the second semiconductor layer (transistor device is formed in layer 212).
Mishra discloses that that 202 GaN layer is wafer bonded to the 212 SiGe layer but does not disclose how the GaN layer is made.
In a related semiconductor art, Preble teaches a process of making high quality GaN layer:
providing a structured substrate (904+908+912, Fig. 9, para [0086]) comprising a first semiconductor material (908 is AlN, Fig. 9) and a patterned structure over a first surface of the structured substrate (pitted top surface of 904+908+912, see Fig. 9);
forming a sacrificial layer (916, Fig. 9, para [0086]) comprising a second semiconductor material (916 is GaN layer) dissimilar from the first semiconductor material (1st material is AlN) over the first surface of the structured substrate (pitted top surface of 904+908+912);
forming a first semiconductor layer (920 GaN layer, Fig. 9, para [0086]) comprising the second semiconductor material (2nd material is GaN) over the sacrificial layer (top planar surface of 916 GaN layer), wherein the first semiconductor layer is substantially defect-free (940, which is initially part of 920 GaN layer, is substantially crack-free, see paras [0086] – [0087]);
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to make the GaN layer of Mishra using the method disclosed by of Preble, as it is a well-known process of making a high quality GaN layer for a transistor device. The use of a known process for its known purpose to yield predictable results is prima facie obvious. Also see KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007). Additionally, the selection of a known process based on its suitability for its intended use supports a prima facie obviousness determination as established in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945), see MPEP 2144.07.
Re Claim 22, Mishra modified by Preble teaches The method of claim 21, further including removing the structured substrate (904+908+912, see Fig. 9, Preble) and sacrificial layer (916, see Fig. 9, Preble) leaving the first semiconductor layer (940, which is initially part of 920 GaN layer, see paras [0086] – [0087]) substantially defect-free (layer 940 is substantially crack-free, para [0087]).
Rejection 2
Claims 1, 3, 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Eriksen et al. (US 2003/0036247 A1, of record), and further in view of Miura et al. (US 2006/0169987 A1, of record).
Re Claim 1, Eriksen teaches a method of making a semiconductor device, comprising:
providing a substrate (202, Figs. 2A-2E, para [0030]) comprising a first semiconductor material (202 is a Si wafer, para [0030]);
forming a sacrificial layer (103, Fig. 2B, para [0030]) comprising a second semiconductor material (103 is part of 104 layer which is a SiC layer, para [0030]) dissimilar from the first semiconductor material (202 is a Si) over the first surface of the substrate (top surface of 202) and provide a planar surface (103 provides a top planar surface, see Fig. 2B);
forming a first semiconductor layer (105, Fig. 2B, para [0030]) comprising the second semiconductor material (105 is SiC, para [0030]) dissimilar from the first semiconductor material (202 is Si) over the planar surface of the sacrificial layer (103); and
removing (Figs. 2F-2G, para [0035]) the substrate (202) and sacrificial layer (103) leaving the first semiconductor layer (110; note that 110 is the portion of 105 that is separated from the substrate and sacrificial layers, para [0032], Figs. 2D-2G) substantially defect-free as the structure removed defects (para [0023]).
Eriksen does not disclose a structured substrate and a patterned structure over a first surface of the structured substrate, and the sacrificial layer filling in the patterned structure, and that the defects induced from the dissimilar first semiconductor material and second semiconductor material being formed in the sacrificial layer by nature of the patterned structure.
However, in a related semiconductor field of art, Miura discloses a two-dimensional array of inverted-pyramid-structure patterned on the surface of the Si substrate (Fig. 12, para [0062]) which will allow further decrease in density of defects in the SiC layer that would be grown on top of the Si substrate (para [0062]). The patterned grooves comprise of mirror-symmetrical facets which lead to the defects themselves being mirror-symmetrical to each other, and the paired defects meeting together and disappearing, thus realizing a high-quality SiC layer with extremely low defects (paras [0047] - [0049]). Additionally, Miura also discloses a buffer layer, “4”, (made of SiC, para [0054]), which fills in the patterned structure and inhibits the spread of the defects to the top layer “5” (para [0056]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to modify the first substrate of Eriksen by patterning a two-dimensional array of inverted-pyramid-structure on the surface of the Si substrate as disclosed by Miura, for realizing a high-quality SiC layer with extremely low defects (paras [0047] - [0049]). Additionally, the sacrificial layer of Eriksen will fill in the patterned structure, similar to the buffer layer of Miura, which will inhibit the spread of the defects to the top layer (para [0056], Miura).
Eriksen modified by Miura also teaches that the defects induced from the dissimilar first semiconductor material (202 is Si, Fig. 2B, Eriksen, similar Silicon layer “1” of Fig. 1 of Miura) and second semiconductor material are formed in the sacrificial layer (sacrificial layer 103 is SiC, Eriksen, which is similar to the SiC buffer layer “4” of Miura, where the majority of the defects are induced, see Fig. 1 and paras [0054]-[0055] of Miura) by nature of the patterned structure (top surface of 202, Eriksen modified by Miura).
Re Claim 3, Eriksen modified by Miura teaches the method of claim 1, further including forming a compliant layer (204, Fig. 2B, para [0030], Eriksen) over a second surface of the structured substrate (bottom surface of 202, Fig. 2B, Eriksen modified by Miura) opposite the first surface of the structured substrate (top surface of 202, Fig. 2B, Eriksen modified by Miura).
Re Claim 5, Eriksen modified by Miura teaches the method of claim 1, wherein the patterned structure includes forming an inverted pyramid structure (inverted-pyramid-structure, Fig. 12, para [0062], Miura) over the first surface of the structured substrate (top surface of 202, Fig. 2B, Eriksen modified by Miura).
Re Claim 6, Eriksen modified by Miura teaches the method of claim 1, wherein the first semiconductor material includes silicon (202 is Si, para [0030], Eriksen) and the second semiconductor material includes silicon carbide or cubic silicon carbide (103/105 is SiC, para [0023], Eriksen).
Claims 7-8, 10, 12-13, 21-22, 24-29 and 33-36 are rejected under 35 U.S.C. 103 as being unpatentable over Zeng et al. (US 2018/0366569 A1, newly cited), and further in view of Eriksen et al. (US 2003/0036247 A1, of record) and Miura et al. (US 2006/0169987 A1, of record).
Re Claim 7, Zeng teaches a method of making a semiconductor device, comprising:
forming a first semiconductor layer (102, Fig. 27A, para [0084]) comprising a second semiconductor material (102 is SiC, Fig. 27A); and
forming a second semiconductor layer (144’, Fig. 27A, para [0084]) over the first semiconductor layer (102); and
forming an electrical component (transistor device, Fig. 27A, para [0084]) in the second semiconductor layer (144’).
Zeng teaches that the first semiconductor layer 102 is formed from an epitaxial process. Hence, it does not teach that the layer is formed separately on a different substrate.
However, related art Eriksen teaches a method of making an improved SiC layer with low defect density, which can then be bonded to fabricate integrated electronics, temperature sensors and other electronics (para [0017]). Eriksen teaches:
providing a substrate (202, Figs. 2A-2E, para [0030]) comprising a first semiconductor material (202 is a Si wafer, para [0030]);
forming a first semiconductor layer (105, Fig. 2B, para [0030]) comprising a second semiconductor material (105 is SiC, para [0030]) dissimilar from the first semiconductor material (202 is Si) over the substrate (202); and
removing (Figs. 2F-2G, para [0035]) the substrate (202) leaving the first semiconductor layer (110; note that 110 is the portion of 105 that is separated from the substrate and sacrificial layers, para [0032], Figs. 2D-2G) substantially defect-free (para [0023]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to replace the epitaxially grown SiC layer of Zeng with the SiC layer of Eriksen, as they are art recognized well-known alternative processes of making SiC layer for a transistor device. The substitution of a known process for its known purpose to yield predictable results is prima facie obvious. Also see KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007). Additionally, the selection of a known process based on its suitability for its intended use supports a prima facie obviousness determination as established in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945), see MPEP 2144.07.
Eriksen does not disclose a structured substrate and a patterned structure over a first surface of the structured substrate.
However, in a related semiconductor field of art, Miura discloses a two-dimensional array of inverted-pyramid-structure patterned on the surface of the Si substrate (Fig. 12, para [0062]) which will allow further decrease in density of defects in the SiC layer that would be grown on top of the Si substrate (para [0062]). The patterned grooves comprise of mirror-symmetrical facets which lead to the defects themselves being mirror-symmetrical to each other, and the paired defects meeting together and disappearing, thus realizing a high-quality SiC layer with extremely low defects (paras [0047] - [0049]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to modify the first substrate of Eriksen by patterning a two-dimensional array of inverted-pyramid-structure on the surface of the Si substrate as disclosed by Miura, for realizing a high-quality SiC layer with extremely low defects (paras [0047] - [0049]).
Re Claim 8, Zeng modified by Eriksen and Miura teaches the method of claim 7, further including forming a sacrificial layer (103, Fig. 2B, para [0030], Eriksen) comprising the second semiconductor material (103 is part of 104 layer which is a SiC layer, para [0030], Eriksen) dissimilar from the first semiconductor material (202 is a Si, para [0030], Eriksen) over the first surface of the structured substrate (top surface of 202, Eriksen modified by Miura).
Re Claim 10, Zeng modified by Eriksen and Miura teaches the method of claim 7, further including forming a compliant layer (204, Fig. 2B, para [0030], Eriksen) over a second surface of the structured substrate (bottom surface of 202, Fig. 2B, Eriksen modified by Miura) opposite the first semiconductor layer (105, Fig. 2B. Eriksen).
Re Claim 12, Zeng modified by Eriksen and Miura teaches the method of claim 7, further including wherein the patterned structure includes forming an inverted pyramid structure (inverted-pyramid-structure, Fig. 12, para [0062], Miura) over the first surface of the structured substrate (top surface of 202, Eriksen modified by Miura).
Re Claim 13, Zeng modified by Eriksen and Miura teaches the method of claim 7, wherein the first semiconductor material includes silicon (202 is Si, para [0030], Eriksen) and the second semiconductor material includes silicon carbide or cubic silicon carbide (103/105 is SiC, para [0023], Eriksen).
Re Claim 21, Zeng teaches a method of making a semiconductor device, comprising:
forming a first semiconductor layer (102, Fig. 27A, para [0084]) comprising a second semiconductor material (102 is SiC, Fig. 27A),
forming a second semiconductor layer (144’, Fig. 27A, para [0084]) over the first semiconductor layer (102); and
forming an electrical component (transistor device, Fig. 27A, para [0084]) in the second semiconductor layer (144’).
Zeng teaches that the first semiconductor layer 102 is formed from an epitaxial process. Hence, it does not teach that the layer is formed separately on a different substrate.
However, related art Eriksen teaches a method of making an improved SiC layer with low defect density, which can then be bonded to fabricate integrated electronics, temperature sensors and other electronics (para [0017]). Eriksen teaches:
providing a substrate (202, Figs. 2A-2E, para [0030]) comprising a first semiconductor material (202 is a Si wafer, para [0030]);
forming a sacrificial layer (103, Fig. 2B, para [0030]) comprising a second semiconductor material (103 is SiC, para [0030]) dissimilar from the first semiconductor material (202 is Si) over the first surface of the substrate (top surface of 202); and
forming a first semiconductor layer (105, Fig. 2B, para [0030]) comprising the second semiconductor material (105 is SiC, para [0030]) over the sacrificial layer (103), wherein the first semiconductor layer (105) is substantially defect-free (para [0023]).
Eriksen teaches that a portion of the substantially defect-free semiconductor layer (110, where 110 is a portion of substantially defect-free semiconductor layer 105) can be separated from the substrate and sacrificial layers (Figs. 2D-2G, para [0032]) and can be used to fabricate integrated electronics, temperature sensors and other electronics (para [0017]). It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to replace the epitaxially grown SiC layer of Zeng with the SiC layer of Eriksen, as they are art recognized well-known alternative processes of making SiC layer for a transistor device. The substitution of a known process for its known purpose to yield predictable results is prima facie obvious. Also see KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007). Additionally, the selection of a known process based on its suitability for its intended use supports a prima facie obviousness determination as established in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945), see MPEP 2144.07.
Eriksen does not disclose a structured substrate and a patterned structure over a first surface of the structured substrate.
However, in a related semiconductor field of art, Miura discloses a two-dimensional array of inverted-pyramid-structure patterned on the surface of the Si substrate (Fig. 12, para [0062]) which will allow further decrease in density of defects in the SiC layer that would be grown on top of the Si substrate (para [0062]). The patterned grooves comprise of mirror-symmetrical facets which lead to the defects themselves being mirror-symmetrical to each other, and the paired defects meeting together and disappearing, thus realizing a high-quality SiC layer with extremely low defects (paras [0047] - [0049]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to modify the first substrate of Eriksen by patterning a two-dimensional array of inverted-pyramid-structure on the surface of the Si substrate as disclosed by Miura, for realizing a high-quality SiC layer with extremely low defects (paras [0047] - [0049]).
Re Claim 22, Zeng modified by Eriksen and Miura teaches the method of claim 21, further including removing (Figs. 2F-2G, para [0035], Eriksen) the structured substrate (202, Eriksen modified by Miura) and sacrificial layer (103, Eriksen) leaving the first semiconductor layer (110; note that 110 is the portion of 105 that is separated from the substrate and sacrificial layers, para [0032], Figs. 2D-2G) substantially defect-free (para [0023], Eriksen) substantially defect-free (para [0023]).
Re Claim 24, Zeng modified by Eriksen and Miura teaches the method of claim 21, wherein the first semiconductor material (202 is Si, para [0030], Eriksen) is dissimilar from the second semiconductor material (103/105 is SiC, para [0023], Eriksen).
Re Claim 25, Zeng modified by Eriksen and Miura teaches the method of claim 21, further including forming a compliant layer (204, Fig. 2B, para [0030], Eriksen) over a second surface of the structured substrate (bottom surface of 202, Fig. 2B, Eriksen modified by Miura) opposite the first surface of the structured substrate (top surface of 202, Fig. 2B, Eriksen modified by Miura).
Re Claim 26, Zeng modified by Eriksen and Miura teaches the method of claim 21, further including wherein the patterned structure includes forming an inverted pyramid structure (inverted-pyramid-structure, Fig. 12, para [0062], Miura) over the first surface of the structured substrate (top surface of 202, Fig. 2B, Eriksen modified by Miura).
Re Claim 27, Zeng modified by Eriksen and Miura teaches the method of claim 21, wherein the first semiconductor material includes silicon (202 is Si, para [0030], Eriksen) and the second semiconductor material includes silicon carbide or cubic silicon carbide (103/105 is SiC, para [0023], Eriksen).
Re Claim 28, Zeng modified by Eriksen and Miura teaches the method of claim 24, wherein defects induced from the dissimilar first semiconductor material (202 is Si, Fig. 2B, Eriksen, similar Silicon layer “1” of Fig. 1 of Miura) and second semiconductor material are formed in the sacrificial layer (sacrificial layer 103 is SiC, Eriksen, which is similar to the SiC buffer layer “4” of Miura, where the majority of the defects are induced, see Fig. 1 and paras [0054]-[0055] of Miura) by nature of the patterned structure (top surface of 202, Eriksen modified by Miura).
Re Claim 29, Zeng modified by Eriksen and Miura teaches the method of claim 8, wherein defects induced from the dissimilar first semiconductor material (202 is Si, Fig. 2B, Eriksen, similar Silicon layer “1” of Fig. 1 of Miura) and second semiconductor material are formed in the sacrificial layer (sacrificial layer 103 is SiC, Eriksen, which is similar to the SiC buffer layer “4” of Miura, where the majority of the defects are induced, see Fig. 1 and paras [0054]-[0055] of Miura) by nature of the patterned structure (top surface of 202, Eriksen modified by Miura).
Re Claim 33, Zeng modified by Eriksen and Miura teaches the method of claim 7, further including:
forming a trench (gate trench 110, Fig. 27A, also see Fig. 4, para [0045], Zeng) formed through the second semiconductor layer (144’, Fig. 27A, Zeng) and extending into the first semiconductor layer (102, Fig. 27A, Zeng);
forming a first column of semiconductor material having a first conductivity type (marked “1st column” in annotated Fig. 27A below, n- type conductivity, Zeng) adjacent to the trench (110);
forming a second column of semiconductor material having a second conductivity type (146, Fig. 27A, p type region, para [0047], Zeng) opposite the first conductivity type (n-type) adjacent to the first column of semiconductor material (“1st column”) opposite the trench (110); and
forming a source region (142, Fig. 27A, para [0034], Zeng) over the first column of semiconductor material (“1st column”).
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Re Claim 34, Zeng modified by Eriksen and Miura teaches the semiconductor device of claim 33, further including forming a gate structure (112+118, Fig. 27A, para [0034], also see Fig. 1 where layer 118 is marked, Zeng) over the second semiconductor layer (144’).
Re Claim 35, Zeng modified by Eriksen and Miura teaches the method of claim 21, further including:
forming a trench (gate trench 110, Fig. 27A, also see Fig. 4, para [0045], Zeng) formed through the second semiconductor layer (144’, Fig. 27A, Zeng) and extending into the first semiconductor layer (102, Fig. 27A, Zeng);
forming a first column of semiconductor material having a first conductivity type (marked “1st column” in annotated Fig. 27A above, n- type conductivity, Zeng) adjacent to the trench (110);
forming a second column of semiconductor material having a second conductivity type (146, Fig. 27A, p type region, para [0047], Zeng) opposite the first conductivity type (n-type) adjacent to the first column of semiconductor material (“1st column”) opposite the trench (110); and
forming a source region (142, Fig. 27A, para [0034], Zeng) over the first column of semiconductor material (“1st column”).
Re Claim 36, Zeng modified by Eriksen and Miura teaches the semiconductor device of claim 35, further including forming a gate structure (112+118, Fig. 27A, para [0034], also see Fig. 1 where layer 118 is marked, Zeng) over the second semiconductor layer (144’).
Rejection 3
Claims 1 and 30-32 are rejected under 35 U.S.C. 103 as being unpatentable over Zeng et al. (US 2018/0366569 A1, newly cited), and further in view of Eriksen et al. (US 2003/0036247 A1, of record) and Miura et al. (US 2006/0169987 A1, of record).
Re Claims 1 and 30, Zeng teaches a method of making a semiconductor device, comprising:
forming a first semiconductor layer (102, Fig. 27A, para [0084]) comprising the second semiconductor material (102 is SiC, Fig. 27A);
the method of claim 1, further including: forming a second semiconductor layer (144’, Fig. 27A, para [0084]) over the first semiconductor layer (102); and
forming an active electrical component (transistor device, Fig. 27A, para [0084]) in the second semiconductor layer (144’).
Zeng teaches that the first semiconductor layer 102 is formed from an epitaxial process. Hence, it does not teach that the layer is formed separately on a different substrate.
However, related art Eriksen teaches a method of making an improved SiC layer with low defect density, which can then be bonded to fabricate integrated electronics, temperature sensors and other electronics (para [0017]). Eriksen teaches:
providing a substrate (202, Figs. 2A-2E, para [0030]) comprising a first semiconductor material (202 is a Si wafer, para [0030]);
forming a sacrificial layer (103, Fig. 2B, para [0030]) comprising a second semiconductor material (103 is part of 104 layer which is a SiC layer, para [0030]) dissimilar from the first semiconductor material (202 is a Si) over the first surface of the substrate (top surface of 202) and provide a planar surface (103 provides a top planar surface, see Fig. 2B);
forming a first semiconductor layer (105, Fig. 2B, para [0030]) comprising the second semiconductor material (105 is SiC, para [0030]) dissimilar from the first semiconductor material (202 is Si) over the planar surface of the sacrificial layer (103); and
removing (Figs. 2F-2G, para [0035]) the substrate (202) and sacrificial layer (103) leaving the first semiconductor layer (110; note that 110 is the portion of 105 that is separated from the substrate and sacrificial layers, para [0032], Figs. 2D-2G) substantially defect-free as the structure removed defects (para [0023]),
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to replace the epitaxially grown SiC layer of Zeng with the SiC layer of Eriksen, as they are art recognized well-known alternative processes of making SiC layer for a transistor device. The substitution of a known process for its known purpose to yield predictable results is prima facie obvious. Also see KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007). Additionally, the selection of a known process based on its suitability for its intended use supports a prima facie obviousness determination as established in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945), see MPEP 2144.07.
Eriksen does not disclose a structured substrate and a patterned structure over a first surface of the structured substrate, and the sacrificial layer filling in the patterned structure, and that the defects induced from the dissimilar first semiconductor material and second semiconductor material being formed in the sacrificial layer by nature of the patterned structure.
However, in a related semiconductor field of art, Miura discloses a two-dimensional array of inverted-pyramid-structure patterned on the surface of the Si substrate (Fig. 12, para [0062]) which will allow further decrease in density of defects in the SiC layer that would be grown on top of the Si substrate (para [0062]). The patterned grooves comprise of mirror-symmetrical facets which lead to the defects themselves being mirror-symmetrical to each other, and the paired defects meeting together and disappearing, thus realizing a high-quality SiC layer with extremely low defects (paras [0047] - [0049]). Additionally, Miura also discloses a buffer layer, “4”, (made of SiC, para [0054]), which fills in the patterned structure and inhibits the spread of the defects to the top layer “5” (para [0056]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to modify the first substrate of Eriksen by patterning a two-dimensional array of inverted-pyramid-structure on the surface of the Si substrate as disclosed by Miura, for realizing a high-quality SiC layer with extremely low defects (paras [0047] - [0049]). Additionally, the sacrificial layer of Eriksen will fill in the patterned structure, similar to the buffer layer of Miura, which will inhibit the spread of the defects to the top layer (para [0056], Miura).
Eriksen modified by Miura also teaches that the defects induced from the dissimilar first semiconductor material (202 is Si, Fig. 2B, Eriksen, similar Silicon layer “1” of Fig. 1 of Miura) and second semiconductor material are formed in the sacrificial layer (sacrificial layer 103 is SiC, Eriksen, which is similar to the SiC buffer layer “4” of Miura, where the majority of the defects are induced, see Fig. 1 and paras [0054]-[0055] of Miura) by nature of the patterned structure (top surface of 202, Eriksen modified by Miura).
Re Claim 31, Zeng modified by Eriksen and Miura teaches the method of claim 30, further including:
forming a trench (gate trench 110, Fig. 27A, also see Fig. 4, para [0045], Zeng) formed through the second semiconductor layer (144’, Fig. 27A, Zeng) and extending into the first semiconductor layer (102, Fig. 27A, Zeng);
forming a first column of semiconductor material having a first conductivity type (marked “1st column” in annotated Fig. 27A above, n- type conductivity, Zeng) adjacent to the trench (110);
forming a second column of semiconductor material having a second conductivity type (146, Fig. 27A, p type region, para [0047], Zeng) opposite the first conductivity type (n-type) adjacent to the first column of semiconductor material (“1st column”) opposite the trench (110); and
forming a source region (142, Fig. 27A, para [0034], Zeng) over the first column of semiconductor material (“1st column”).
Re Claim 32, Zeng modified by Eriksen and Miura teaches the semiconductor device of claim 31, further including forming a gate structure (112+118, Fig. 27A, para [0034], also see Fig. 1 where layer 118 is marked, Zeng) over the second semiconductor layer (144’).
Response to Arguments
Applicant’s arguments with respect to claims 1, 7 and 21 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Regarding clam 1, applicant argues that Miura et al. “shows Si buffer layer 4 (see paragraph [0051]) formed in facets 2 and SiC layer 5 formed over the buffer layer and extending into the facets, see FIG. 10. At no point does Miura form a sacrificial layer comprising a second semiconductor material dissimilar from the first semiconductor material over the first surface of the structured substrate to fill in the patterned structure and provide a planar surface.” Examiner respectfully disagrees with the applicant. Miura does teach that the buffer layer “4” can be made of SiC (see Fig. 1 and paras [0054] – [0055]), dissimilar semiconductor material from the silicon substrate “1”, and the buffer layer fills in the patterned top layer of substrate “1”, and that the defects are concentrated in this layer (see Fig. 1). The buffer layer is similar to the sacrificial layer of Eriksen et al., as explained in the rejection of claim 1 above.
Conclusion
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/P.D./Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898