Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed on 04/29/2026 have been fully considered but they are not persuasive.
Regarding claim 1, Applicant argues that “a passivation layer extending along the intermediate surface of the silicon layer from a sidewall of the first trench to a sidewall of the second trench” is not taught by Macelwee. However, the office respectfully disagrees with this argument for the following reasons:
Claim 1 merely requires the passivation layer to extend along the intermediate surface of the silicon layer from a sidewall of the first trench to a sidewall of the second trench. As shown in Fig. 14 of Macelwee, layer 1090 clearly extends from the sidewall of the first trench to (towards) the sidewall of the second trench. The claim does not require the passivation layer to extend directly/contacting to the sidewall of the second trench.
Moreover, assuming arguendo, applicant amends claim 1 to require the passivation layer to extend from sidewall of the first trench directly to a sidewall of the second trench; this would still not be deemed to patentably distinguish the applicant’s claimed semiconductor wafer from that of Macelwee because, in column 14 lines 60-66, Macelwee teaches that if required, the trench can extend over a substantial amount of the dicing street 1088 in each side of the scribe line 1016 (see fig. 14), making the passivation layer to extend laterally from the sidewall of the first trench directly to the sidewall of the second trench. In light of this teaching, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the passivation layer could extend along the intermediate surface from a sidewall of the first trench directly to a sidewall of the second trench without any intermediate layer exposed.
Further, the office notes that the prior art made of record and not relied upon are considered pertinent to current application disclosure is the newly cited reference Zundel (US 20200135564 A1) which clearly teaches, in Fig. 3, passivation layer 136 extending along the intermediate surface of the silicon layer from a sidewall of the first trench to a sidewall of the second trench.
Hence, the rejection of claim 1 is maintained in the basis of the revised mapping necessitated by the amendment.
Regarding claim 15, Applicant argues that claim 15 overcomes the rejection for the same reasons as discussed above with respect to claim 1. However, the rejection of claim 15 is maintained in the basis of the revised mapping necessitated by the amendment for the same reason as explained above with respect to claim 1 above.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 5 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Macelwee (US 10283501 B2).
Re: Independent Claim 1 (Previously Presented), Macelwee discloses a semiconductor wafer comprising:
a silicon layer (Macelwee, Fig 6, #302, also Fig. 14 lowest layer);
and a gallium nitride (GaN) layer) disposed on the silicon layer (Macelwee, Fig 6, GaN layer #312, also in Fig. 14 Macelwee teaches GaN-on-Si wafer) wherein the GaN layer and at least a portion of the silicon layer define a first trench extending through a thickness of the GaN layer and extending through at least a portion of a thickness of the silicon layer to define an intermediate surface of the silicon layer, the first trench having a first width (Macelwee, in Fig. 14 teaches pre-dicing trench with a width i.e., trench 1088 that is etched through GaN layer and extending through a portion of silicon substrate that is below the GaN layer, thereby defining an intermediate surface of the silicon layer); and
wherein the silicon layer defines a second trench having a second width, the second trench extending through the thickness of the silicon layer, wherein the second trench is aligned within the first width and wherein the first width is greater than the second width (Macelwee, in Fig. 14, teaches individual die are then singulated using any suitable dicing process, e.g. laser grooving through the substrate within the pre-dicing trench 1088. Thus, Macelwee teaches forming a second trench with second width (laser groove) through the silicon substrate and doing so within the first trench (1088) satisfies the “aligned with” relationship. Fig. 14 also shows that width of first trench is greater than the second width); and
a passivation layer extending along the intermediate surface of the silicon layer from a sidewall of the first trench to a sidewall of the second trench (Macelwee, in Fig 14 and column 5, lines 1-8, teaches trench cladding 1090 layer that contains at least one overlying passivation layer extending along the intermediate surface of silicon layer from a sidewall of the first trench 1088 to a sidewall of the second trench).
Re: Claim 2 (Original), Macelwee discloses all the limitations of claim 1 on which this claim depends. Macelwee further discloses,
wherein the GaN layer comprises one or more gallium nitride layers of different compositions (Macelwee, Fig 6., column 11 lines 59-60, #312 includes a GaN/AlGaN heterostructure).
Re: Claim 3 (Original), Macelwee discloses all the limitations of claim 1 on which this claim depends. Macelwee further discloses,
further comprising a plurality of dielectric layers (Macelwee, Fig 6, #336 and #338 are dielectric layers) disposed on the GaN layer.
Re: Claim 5 (Previously Presented), Macelwee discloses all the limitations of claim 1 on which this claim depends. Macelwee further discloses,
wherein the first trench is formed at front-end-of-line (FEOL) (Macelwee, column 6 lines 30-column 7 line 4, the first trench is formed before metallization and device wiring steps, which are front-end processes).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 15-18 is rejected under 35 U.S.C. 103 as being unpatentable over Macelwee (US 10283501 B2)
Re: Independent Claim 15 (Previously Presented), Macelwee discloses a semiconductor die (Macelwee, Fig 6, #110) comprising:
a silicon layer (Macelwee, Fig 6, #302) defining an outer periphery of the semiconductor die (Macelwee, Fig 6, surface 318 is outer periphery with silicon layer);
and a gallium nitride (GaN) layer (Macelwee, Fig 6, #312) disposed on the silicon layer, wherein the GaN layer and at least a portion of the silicon layer define a first trench extending through a thickness of the GaN layer and extending through at least a portion of a thickness of the silicon layer to define an intermediate surface of the silicon layer, the first trench having a first width (Macelwee, in Fig. 14 teaches pre-dicing trench with a width i.e., trench 1088 that is etched through GaN layer and extending through a portion of silicon substrate that is below the GaN layer, thereby defining an intermediate surface of the silicon layer); and
wherein the silicon layer defines a second trench having a second width, the second trench extending through the thickness of the silicon layer, wherein the second trench is aligned within the first width and wherein the first width is greater than the second width (Macelwee, in Fig. 14, teaches individual die are then singulated using any suitable dicing process, e.g. laser grooving through the substrate within the pre-dicing trench 1088. Thus, Macelwee teaches forming a second trench with second width (laser groove) through the silicon substrate and doing so within the first trench (1088) satisfies the “aligned with” relationship. Fig. 14 also shows that width of first trench is greater than the second width); and
a passivation layer extending along the intermediate surface of the silicon layer from a sidewall of the first trench to a sidewall of the second trench (Macelwee, in Fig 14 and column 5, lines 1-8, teaches trench cladding 1090 layer that contains at least one overlying passivation layer extending along the intermediate surface of silicon layer from a sidewall of the first trench 1088 to a sidewall of the second trench).
Macelwee does not explicitly disclose gallium nitride (GaN) layer recessed from the outer periphery. However, Macelwee teaches GaN is not present in the outer periphery surface of the pre-dicing trench (Macelwee, Fig 14, #1088), since GaN layer is recessed during trench forming step. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of figure 14 showing GaN layer recessed from the outer periphery, to figure 6 in order to provide stress-relief across the wafer (Macelwee, Column 7, lines 7-15).
Re: Claim 16 (Original), Macelwee discloses all the limitations of claim 15 on which this claim depends. Macelwee further discloses,
wherein the GaN layer comprises one or more gallium nitride layers of different compositions (Macelwee, Fig 6., column 11 lines 59-60, #312 includes a GaN/AlGaN heterostructure).
Re: Claim 17 (Original), Macelwee discloses all the limitations of claim 15 on which this claim depends. Macelwee further discloses,
further comprising a plurality of dielectric layers disposed on the GaN layer (Macelwee, Fig 6, #336 and #338 are dielectric layers).
Re: Claim 18 (Original), Macelwee discloses all the limitations of claim 15 on which this claim depends. Macelwee further discloses,
wherein the recess in the GaN layer is formed at front-end-of-line (FEOL) (Macelwee, column 6 lines 30-column 7 line 4, trenches are formed before metallization and device wiring steps, which are front-end processes).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Macelwee (US 10283501 B2) in view of Zechmann (US 20180247869 A1).
Re: Claim 4 (Currently Amended), Macelwee discloses all the limitations of claim 3 on which this claim depends. Macelwee is silent regarding:
wherein the first trench has a depth that is equal to a sum of a thickness of the GaN layer and a thickness of the plurality of the dielectric layers.
However, Zechmann discloses the first trench has a depth that is equal to a sum of a thickness of the GaN layer and a thickness of the plurality of the dielectric layers (Zechmann, ¶ [0037], Fig 5, trenches 124, 126 are formed to vertically extend from the upper surface 108 of the first type III-V semiconductor layer 104 at least to the growth surface 102 of the base substrate 100. It means the trench can end right at the start of silicon surface, resulting in depth of trenches equal to a sum of thickness of the GaN layer and a thickness of the plurality of the dielectric layers). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to implement Zechmann teaching to stop the trench at the GaN/Si interface resulting in depth of trenches equal to a sum of thickness of the GaN layer and a thickness of the plurality of the dielectric layers to the disclosure of Macelwee in order to prevent cracks from propagating into the active area of semiconductor dies during the die singulation process (Zechmann, ¶ [0026], lines1-4).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BIPANA ADHIKARI DAWADI whose telephone number is (571)272-4149. The examiner can normally be reached Monday-Friday 11:30am-7:30pm.
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/BIPANA ADHIKARI DAWADI/Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898
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