DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, where the spacer partially extends through the second substrate, as found in claim 2 must be shown or the feature(s) canceled from the claim(s). The drawings only appear to show the spacer extending completely through the second substrate, as the isolation member 102k is a feature distinct from the second substrate as claimed and described. No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 3 and 16 rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
A bottom surface of a spacer and a top surface of an isolation member were nowhere described to be substantially coplanar, and the drawings do not unambiguously depict a relationship between these elements that would be generally recognized as substantially coplanar. Therefore, describing a bottom surface of the spacer a top surface of the isolation member as substantially coplanar, now recited in claims 3 and 16, introduces new matter.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2-3 and 16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
(Re Claim 2) As the spacer is not described as extending partially through the second substrate and the drawings appear only to show a spacer extending completely through the second substrate, the relationship between the spacer and the second substrate is unclear.
During examination, “partially extends” was read as “extends”.
Claim 3 inherits this rejection for indefiniteness.
(Re Claim 3 and 16) As a bottom of the spacer and a top of the isolation member were never described as substantially coplanar, and the drawings do not unambiguously show such a relationship, the relationship between the bottom of the spacer and the top of the isolation member is unclear.
During examination, “substantially coplanar” was read as “aligned with”.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-12 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (US 2020/0365514), Park et al. (US 2022/0020667), Kao et al. (US 2017/0154850), and Lin (US 2015/0021789), all of record.
(Re Claim 1) Yang teaches a semiconductor structure, comprising: a first die structure (Fig. 5B markup) including a first substrate (110 within first die structure; Fig. 1E and Fig. 5B markup), a first bonding dielectric (140 with first die structure; Fig. 1E and Fig. 5B markup) disposed over the first substrate, and a first bonding pad (152 within first die structure; Fig. 5B markup) surrounded by the first bonding dielectric; a second die structure (Fig. 5B markup) including a second substrate (110 within second die structure; Fig. 1E and Fig. 5B markup), a second bonding dielectric (140 within second die structure) bonded with the first bonding dielectric (at the bonding interface IF; ¶47), and a second bonding pad (152 within the second die structure; Fig. 5B markup) surrounded by the second bonding dielectric and bonded with the first bonding pad (¶47); a conductive via (70; Fig. 5B) extending through the second substrate (Fig. 5B); and a conductive member (lower 84; Fig. 5B) at least partially in contact with the conductive via (Fig. 5B).
Yang does not explicitly teach a semiconductor structure comprising an isolation member extending into the second substrate;
a dielectric member disposed over the second die structure;a conductive via extending through the dielectric member and the isolation member;
a conductive member disposed over the dielectric member;
wherein a first interface between the conductive via and the conductive member is substantially coplanar with a second interface between the conductive member and the dielectric member, and
wherein the conductive via is partially surrounded by a spacer.
Park teaches forming an isolation member (144a; Fig. 9) within a substrate (110; Fig. 9) having a via (168; Fig. 13) extending through it (Fig. 12 and 13).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to introduce an isolation member into the second substrate of Yang, such that it extends into the second substrate as taught by Park (compare the orientation of the semiconductor device 152 of Park with the devices 112 of Yang) to relieve stress generated by the via of Yang (Park: ¶¶82-83).
Kao teaches forming a dielectric member (202+204+206; Fig. 8) on the backside of a die structure (elements below 202 in Fig. 8) before forming a via extending through the dielectric member and a substrate (102; Fig. 9 to 12).
A PHOSITA would find it obvious to form a dielectric member on the backside of the second die structure, before forming the conductive via 70 of modified Yang such that via 70 extends through the dielectric member taught by Kao, in order to reduce the surface roughness of the backside as a result of thinning the second substrate 110 to reduce thickness before further processing. Doing so reduces device leakage (Kao: ¶24).
Modified Yang then teaches a semiconductor structure additionally comprising an isolation member extending into the second substrate (modified Fig. 5B markup);
a dielectric member disposed over the second die structure (modified Fig. 5B markup);
a conductive via (70) extending through the dielectric member and the isolation member (modified Fig. 5B markup);
wherein a first interface between the conductive via and the conductive member is substantially coplanar with a second interface between the conductive member and the dielectric member (modified Fig. 5B markup).
PNG
media_image1.png
972
816
media_image1.png
Greyscale
PNG
media_image2.png
527
1047
media_image2.png
Greyscale
Lin teaches forming a conductive via (420+420; Fig. 4) surrounded by a spacer (410; Fig. 4).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to form the conductive via 70 of Yang such that it is surrounded by a spacer as taught by Lin to electrically isolate the conductive via 70 from the material of the second die structure (Lin: ¶26). Furthermore, a PHOSITA would find it obvious to form the conductive via 70 of Yang such that it has a diffusion barrier 420 as taught by Lin in order to prevent diffusion of the conductive material of the conductive via (Lin: ¶26).
Doing so results in modified Yang teaching a semiconductor structure wherein the conductive via is partially surrounded by a spacer (Lin: neither the top nor the bottom of the conductive via 420+430 from Lin is surrounded by the spacer 410; Fig. 4).
(Re Claim 2) Modified Yang teaches the semiconductor structure of Claim 1, wherein the spacer partially extends through the second substrate (Fig. 5 markup) and extends through the dielectric member (as the spacer from Lin is along the full extent of the conductive via; Fig. 5B markup).
(Re Claim 3) Modified Yang teaches the semiconductor structure of Claim 2, wherein a bottom of the spacer is substantially coplanar with a top of the isolation member (Fig. 5B markup; see also the 112(a) and 112(b) rejections).
(Re Claim 4) Modified Yang teaches the semiconductor structure of Claim 2, wherein a third interface between the conductive member and the spacer is substantially coplanar with the first interface and the second interface (due to planarization; Fig. 5B markup; Lin: ¶29).
(Re Claim 5) Modified Yang teaches the semiconductor structure of Claim 4, wherein the third interface is disposed between and coupled with the first interface and the second interface (Fig. 5B markup).
(Re Claim 6) Modified Yang teaches the semiconductor structure of Claim 1, wherein the first die structure includes a first dielectric (124 within first die structure; Fig. 1E and Fig. 5B markup) disposed between the first substrate and the first bonding dielectric, and a first interconnect structure (122; Fig. 5B) within the first dielectric, the first interconnect structure is coupled with the first bonding pad (Fig. 5B).
(Re Claim 7) Modified Yang teaches the semiconductor structure of Claim 1, wherein the second die structure includes a second dielectric (124 within second die structure; Fig. 1E and Fig. 5B) disposed between the second substrate and the second bonding dielectric, and a second interconnect structure (122; Fig. 5B) within the second dielectric.
(Re Claim 8) Modified Yang teaches the semiconductor structure of Claim 7, wherein the conductive via extends at least partially through the second dielectric and coupled with the second interconnect structure (Fig. 5B).
(Re Claim 9) Modified Yang teaches the semiconductor structure of Claim 7, wherein the second interconnect structure is coupled with the second bonding pad (Fig. 5B).
(Re Claim 10) Modified Yang teaches the semiconductor structure of Claim 1, further comprising a passivation (82; Fig. 5B) disposed over the dielectric member and the conductive member, wherein the conductive member is at least partially exposed through the passivation (Fig. 5B).
(Re Claim 11) Modified Yang teaches the semiconductor structure of Claim 10, wherein a fourth interface (top side of conductive member 84; Fig. 5B) between the passivation and the conductive member is substantially planar (Fig. 5B).
(Re Claim 12) Modified Yang teaches the semiconductor structure of Claim 10, wherein the fourth interface is substantially parallel to the first interface and the second interface (Fig. 5B markup).
Claims 13-18 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (US 2020/0365514), Kao et al. (US 2017/0154850), and Lin (US 2015/0021789), all of record.
(Re Claim 13) Yang teaches a semiconductor structure, comprising: a first die structure (Fig. 5B markup); a second die structure (Fig. 5B markup) bonded (¶47) over the first die structure; a conductive via (70; Fig. 5B) extending partially through the second die structure (Fig. 5B); and a conductive member (lower 84; Fig. 5B) coupled with the conductive via (Fig. 5B), wherein a first outer surface (lower side; Fig. 5B) of the conductive member contacting the conductive via is substantially planar (Fig. 5B).
Yang does not explicitly teach a semiconductor structure comprising:
a dielectric member disposed over the second die structure; a conductive via extending through the dielectric member;
a spacer extending through the dielectric member and partially through the second die structure; and
a conductive member disposed over the dielectric member, wherein the first outer surface of the conductive member contacting the dielectric member and the spacer is substantially planar, and
wherein the conductive via is partially surrounded by a the spacer.
Kao teaches forming a dielectric member (202+204+206; Fig. 8) on the backside of a die structure (elements below 202 in Fig. 8) before forming a via extending through the dielectric member and a substrate (102; Fig. 9 to 12).
A PHOSITA would find it obvious to form a dielectric member on the backside of the second die structure, before forming the conductive via 70 of modified Yang such that via 70 extends through the dielectric member taught by Kao, in order to reduce the surface roughness of the backside as a result of thinning the second substrate 110 to reduce thickness before further processing. Doing so reduces device leakage (Kao: ¶24).
This results in modified Yang teaches a dielectric member disposed over the second die structure, and the conductive via extending through the dielectric member (Fig. 5B markup).
Lin teaches forming a conductive via (420+430; Fig. 4) surrounded by a spacer (410; Fig. 4).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to form the conductive via 70 of Yang such that it is surrounded by a spacer as taught by Lin to electrically isolate the conductive via 70 from the material of the second die structure (Lin: ¶26). Furthermore, a PHOSITA would find it obvious to form the conductive via 70 of Yang such that it has a diffusion barrier 420 as taught by Lin in order to prevent diffusion of the conductive material of the conductive via (Lin: ¶26).
This results in modified Yang teaches a spacer surrounding the conductive via and extending through the dielectric member and partially through the second die structure; and the first outer surface of the conductive member contacting the dielectric member and the spacer is substantially planar (Fig. 5B markup), and
wherein the conductive via is partially surrounded by the spacer (Lin: neither the top nor the bottom of the conductive via 420+420 from Lin is surrounded by the spacer 410; Fig. 4).
PNG
media_image1.png
972
816
media_image1.png
Greyscale
PNG
media_image3.png
527
865
media_image3.png
Greyscale
(Re Claim 14) Modified Yang semiconductor structure of Claim 13, further comprising a passivation (82; Fig. 5B) disposed over the dielectric member and covering at least a portion of the conductive member, wherein the first outer surface of the conductive member and an interface between the passivation and the dielectric member are at a same level (Fig. 5B markup).
(Re Claim 15) Modified Yang teaches the semiconductor structure of Claim 14, further comprising a conductive bump (90; Fig. 5B) disposed over the conductive member and protruded from the passivation (Fig. 5B).
(Re Claim 16) Modified Yang teaches the semiconductor structure of Claim 13, wherein a top surface of the spacer is substantially coplanar with the first outer surface of the conductive member (due to planarization; Lin: ¶29), and a bottom of the spacer is substantially coplanar with a top of the isolation member (Fig. 5B markup; see also the 112(a) and 112(b) rejections).
(Re Claim 17) Modified Yang teaches the semiconductor structure of Claim 13, wherein a second outer surface (top surface; Fig. 5B) of the conductive member contacting the passivation and disposed above the first outer surface is substantially planar (Fig. 5B).
(Re Claim 18) Modified Yang teaches the semiconductor structure of Claim 17, wherein the first outer surface is substantially parallel to the second outer surface (Fig. 5B).
(Re Claim 21) Yang semiconductor structure, comprising: a die structure (first and second die structures of Fig. 5B markup); a conductive via extending partially through the die structure; and a conductive member (lower 84; Fig. 5B) coupled with the conductive via, wherein the conductive member is in contact with the conductive via (Fig. 5B).
Yang does not explicitly teach a semiconductor structure comprising:
a dielectric member disposed over the die structure; the conductive via extending through the dielectric member,
a spacer extending through the dielectric member and partially through the die structure; and
the conductive member disposed over the dielectric member, wherein the conductive member is in contact with the spacer, and
wherein the conductive via is partially surrounded by the spacer.
Kao teaches forming a dielectric member (202+204+206; Fig. 8) on the backside of a die structure (elements below 202 in Fig. 8) before forming a via extending through the dielectric member and a substrate (102; Fig. 9 to 12).
A PHOSITA would find it obvious to form a dielectric member on the backside of the second die structure, before forming the conductive via 70 of modified Yang such that via 70 extends through the dielectric member taught by Kao, in order to reduce the surface roughness of the backside as a result of thinning the second substrate 110 to reduce thickness before further processing. Doing so reduces device leakage (Kao: ¶24).
This results in modified Yang teaches a dielectric member disposed over the second die structure, and the conductive via extending through the dielectric member (Fig. 5B markup).
Lin teaches forming a conductive via (420+430; Fig. 4) surrounded by a spacer (420; Fig. 4).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to form the conductive via 70 of Yang such that it is surrounded by a spacer as taught by Lin to electrically isolate the conductive via 70 from the material of the second die structure (Lin: ¶26). Furthermore, a PHOSITA would find it obvious to form the conductive via 70 of Yang such that it has a diffusion barrier 420 as taught by Lin in order to prevent diffusion of the conductive material of the conductive via (Lin: ¶26).
This results in modified Yang teaches a spacer surrounding the conductive via and extending through the dielectric member and partially through the die structure; and the conductive member disposed over the dielectric member, wherein the conductive member is in contact with the spacer and the conductive via (Fig. 5B markup), and
wherein the conductive via is partially surrounded by the spacer (Lin: neither the top nor the bottom of the conductive via 420+430 from Lin is surrounded by the spacer 410; Fig. 4).
PNG
media_image1.png
972
816
media_image1.png
Greyscale
PNG
media_image2.png
527
1047
media_image2.png
Greyscale
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (US 2020/0365514), Kao et al. (US 2017/0154850), and Lin (US 2015/0021789) as applied to claim 21 above, and further in view of Park et al. (US 2022/0020667), all of record.
(Re Claim 22) Modified Yang teaches the semiconductor structure of Claim 21, wherein the conductive via is partially surrounded by the spacer (Lin: neither the top nor the bottom of the conductive via 420+430 from Lin is surrounded by the spacer 410; Fig. 4)
Modified Yang has not been shown to explicitly teach the semiconductor structure further comprising an isolation member disposed within the die structure, surrounding the conductive via, and contacting the spacer, wherein the conductive via is partially surrounded by the isolation member.
Park teaches forming an isolation member (144a; Fig. 9) within a substrate (110; Fig. 9) having a via (168; Fig. 13) extending through it (Fig. 12 and 13).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to introduce an isolation member into the die structure of Yang, such that it extends into a substrate (Yang: 110 of second die structure; Fig. 5B markup) as taught by Park (compare the orientation of the semiconductor device 152 of Park with the devices 112 of Yang) to relieve stress generated by the via of Yang (Park: ¶¶82-83).
As spacer of modified Yang is deposited after forming the via hole for the conductive via 70 of modified Yang, modified Yang then teaches the semiconductor structure further comprising an isolation member disposed within the die structure (Fig. 5B markup), surrounding the conductive via (Fig. 5B markup), and contacting the spacer (Lin: Fig. 4; Fig. 5B markup for modified Yang), wherein the conductive via is partially surrounded by the isolation member (Fig. 5B markup).
Response to Arguments
Applicant's arguments filed 10/1/2025 have been fully considered but they are not persuasive.
Applicant appears to argue a narrower interpretation of “partially” than is justified by the instant disclosure (remarks, p. 1). “the conductive via is partially surrounded by a spacer” does not require that only material flanking the conductive via is taken into account when determining whether a spacer partially surrounds a conductive via. “partially surrounded” is met when the conductive via is not covered by the spacer somewhere. In the case of the current rejection, the conductive via of modified Yang is not surrounded by the spacer at a top or bottom part of the conductive via, and so it may be said to be only partially surrounded by the spacer.
The remainder of Applicant’s arguments are moot in view of the new rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Christopher A Schodde whose telephone number is (571)270-1974. The examiner can normally be reached M-F 1000-1800 EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at (571)272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/CHRISTOPHER A. SCHODDE/Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898