DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 5/7/2026 has been entered.
Claim Objections
Claim 22 is objected to because of the following informalities: “the spacer, wherein the spacer comprises:” should likely read --wherein the spacer comprises:-- Appropriate correction is required.
Drawings
In view of Applicant’s amendments, the prior drawing objection is withdrawn.
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the spacer extending through the isolation member as found in claim 13 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
In view of Applicant’s amendments, the prior 112(a) and 112(b) rejections are withdrawn.
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 13-18 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Nowhere was a spacer shown or described “extending through…the isolation member”. This amended limitation of claim 13 introduces new matter.
Claims 14-18 inherit this rejection for new matter.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 13-18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
(Re Claim 13) As nowhere does a spacer appear to have been described in the specification or drawings “extending through…the isolation member”, the relationship between parts is unclear.
During examination “extending through the dielectric member and the isolation member and partially through the second die structure” was read as “extending through the dielectric member, partially through the second die structure, and to the isolation member”.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-18 and 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (US 2020/0365514), Park et al. (US 2022/0020667), Kao et al. (US 2017/0154850), and Tsai et al. (US 2015/0348874), all of record, and Shih (US 2023/0377885) and Gambino et al. (US 2021/0111102), both newly cited.
(Re Claim 1) Yang teaches a semiconductor structure, comprising: a first die structure (Fig. 5B markup) including a first substrate (110 within first die structure; Fig. 1E and Fig. 5B markup), a first bonding dielectric (140 with first die structure; Fig. 1E and Fig. 5B markup) disposed over the first substrate, and a first bonding pad (152 within first die structure; Fig. 5B markup) surrounded by the first bonding dielectric; a second die structure (Fig. 5B markup) including a second substrate (110 within second die structure; Fig. 1E and Fig. 5B markup), a second bonding dielectric (140 within second die structure) bonded with the first bonding dielectric (at the bonding interface IF; ¶47), and a second bonding pad (152 within the second die structure; Fig. 5B markup) surrounded by the second bonding dielectric and bonded with the first bonding pad (¶47); a conductive via (70; Fig. 5B) extending through the second substrate (Fig. 5B); and a conductive member (lower 84; Fig. 5B) at least partially in contact with the conductive via (Fig. 5B).
Yang does not explicitly teach a semiconductor structure comprising an isolation member extending into the second substrate;
a dielectric member disposed over the second die structure;a conductive via extending through the dielectric member and the isolation member;
a conductive member disposed over the dielectric member;
wherein a first interface between the conductive via and the conductive member is substantially coplanar with a second interface between the conductive member and the dielectric member, and
wherein the conductive via is partially surrounded by a spacer.
Park teaches forming an isolation member (144a; Fig. 9) within a substrate (110; Fig. 9) having a via (168; Fig. 13) extending through it (Fig. 12 and 13).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to introduce an isolation member into the second substrate of Yang, such that it extends into the second substrate as taught by Park (compare the orientation of the semiconductor device 152 of Park with the devices 112 of Yang) to relieve stress generated by the via of Yang (Park: ¶¶82-83).
Kao teaches forming a dielectric member (202+204+206; Fig. 8) on the backside of a die structure (elements below 202 in Fig. 8) before forming a via extending through the dielectric member and a substrate (102; Fig. 9 to 12).
A PHOSITA would find it obvious to form a dielectric member on the backside of the second die structure, before forming the conductive via 70 of modified Yang such that via 70 extends through the dielectric member taught by Kao, in order to reduce the surface roughness of the backside as a result of thinning the second substrate 110 to reduce thickness before further processing. Doing so reduces device leakage (Kao: ¶24).
Modified Yang then teaches a semiconductor structure additionally comprising an isolation member extending into the second substrate (modified Fig. 5B markup);
a dielectric member disposed over the second die structure (modified Fig. 5B markup);
a conductive via (70) extending through the dielectric member and the isolation member (modified Fig. 5B markup);
wherein a first interface between the conductive via and the conductive member is substantially coplanar with a second interface between the conductive member and the dielectric member (modified Fig. 5B markup).
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Shih teaches utilizing an isolation member (212; Fig. 7) as an etch stop for forming an opening that is eventually used to form a conductive via (230+260; Fig. 14).
A PHOSITA would find it obvious to stop the etch when forming the opening ultimately used for forming the conductive via of modified Yang, in the manner taught by Shih, as a consequence of different materials used for the isolation member and the second substrate (Shih: ¶24; Yang: ¶13; Park: ¶40), and in order to allow for other, smaller openings formed at the same time, such as for signal routing, to have a difference in their etch rate reduced (Shih: ¶24).
Tsai teaches forming a spacer (114; Fig. 1B) after utilizing an isolation member as an etch stop (Fig. 1B, ¶28).
A PHOSITA would find it obvious to deposit a spacer within the opening used to form the conductive via of modified Yang after the isolation member has been utilized as an etch stop, before punching through the isolation member as taught by Tsai, to provide passivation and insulation between the conductive via and both the devices within the second substrate and the isolation member (Tsai: ¶31).
Gambino teaches forming a multilayered spacer (30+80; Fig. 4C) within an opening used for a conductive via (70; Fig. 4E), before punching through to an interconnect structure (21; Fig. 4D). The conductive via partially contacts the spacer (Fig. 4E).
A PHOSITA would find it obvious to form the spacer of Gambino within the opening used to form the conductive via of modified Yang, instead of that taught by Tsai, to allow for the spacer to provide a self-alignment function for forming an opening to the underlying interconnect layers of the second substrate (Gambino: “Spacer 80S may be self-aligned with metal pad 21 in insulator layer 20” (¶43)).
Due to the conformal deposition of the spacer of Gambino above the isolation member of modified Yang, modified Yang further teaches a semiconductor structure wherein the conductive via is partially surrounded by a spacer (Gambino: 30+80; Fig. 4C), and wherein the spacer is disposed on the isolation member so that a sidewall (left) of the conductive via partially contacts the spacer and the partially contacts the isolation member (modified Yang’s Fig. 5B markup below; note that the conductive via is now surrounded by Gambino’s spacer 30+80).
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(Re Claim 2) Modified Yang teaches the semiconductor structure of Claim 1, wherein a length of the conductive via is greater than a total length of a length of the spacer and a length of the isolation member (The conductive via goes through both a length of the spacer and a length of the isolation member in a top to bottom direction, and then continues on).
(Re Claim 3) Modified Yang teaches the semiconductor structure of Claim 2, wherein the spacer comprises:
a first liner (Gambino: 30; Fig. 4D) comprising:
a bottom portion (Gambino’s Fig. 4D markup) disposed on the isolation member (modified Yang’s Fig. 5B markup showing the incorporation of Gambino’s teachings); and
an extending portion (Gambino’s Fig. 4D markup) extending from the bottom portion of the first liner to the conductive member (modified Yang’s Fig. 5B markup showing the incorporation of Gambino’s teachings); and
a second liner (Gambino: 80; Fig. 4D) disposed on the bottom portion of the first liner and between the extending portion of the first liner and the conductive via (Gambino’s Fig. 4D, and modified Yang’s Fig. 5B markup showing the incorporation of Gambino’s teachings).
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(Re Claim 4) Modified Yang teaches the semiconductor structure of Claim 2, but has not explicitly been shown to teach a third interface between the conductive member and the spacer is substantially coplanar with the first interface and the second interface.
Kao teaches planarizing the surface of the dielectric member after forming a conductive via (Fig. 11, ¶50).
A PHOSITA would find it obvious to planarize the surface of the dielectric member as taught by Kao after forming the conductive via of modified Yang, to prevent irregular geometry of the top surface from interfering with subsequent film deposition, and to electrically isolate the via from the rest of the top surface of the dielectric member.
Doing so results in modified Yang teaching a third interface (area of contact between the conductive member and the spacer; modified Yang’s Fig. 5B markup) between the conductive member and the spacer is substantially coplanar with the first interface and the second interface, as a result of planarization.
(Re Claim 5) Modified Yang teaches the semiconductor structure of Claim 4, wherein the third interface is disposed between and coupled with the first interface and the second interface (Fig. 5B markup).
(Re Claim 6) Modified Yang teaches the semiconductor structure of Claim 1, wherein the first die structure includes a first dielectric (124 within first die structure; Fig. 1E and Fig. 5B markup) disposed between the first substrate and the first bonding dielectric, and a first interconnect structure (122; Fig. 5B) within the first dielectric, the first interconnect structure is coupled with the first bonding pad (Fig. 5B).
(Re Claim 7) Modified Yang teaches the semiconductor structure of Claim 1, wherein the second die structure includes a second dielectric (124 within second die structure; Fig. 1E and Fig. 5B) disposed between the second substrate and the second bonding dielectric, and a second interconnect structure (122; Fig. 5B) within the second dielectric.
(Re Claim 8) Modified Yang teaches the semiconductor structure of Claim 7, wherein the conductive via extends at least partially through the second dielectric and coupled with the second interconnect structure (Fig. 5B).
(Re Claim 9) Modified Yang teaches the semiconductor structure of Claim 7, wherein the second interconnect structure is coupled with the second bonding pad (Fig. 5B).
(Re Claim 10) Modified Yang teaches the semiconductor structure of Claim 1, further comprising a passivation (82; Fig. 5B) disposed over the dielectric member and the conductive member, wherein the conductive member is at least partially exposed through the passivation (Fig. 5B).
(Re Claim 11) Modified Yang teaches the semiconductor structure of Claim 10, wherein a fourth interface (top side of conductive member 84; Fig. 5B) between the passivation and the conductive member is substantially planar (Fig. 5B).
(Re Claim 12) Modified Yang teaches the semiconductor structure of Claim 10, wherein the fourth interface is substantially parallel to the first interface and the second interface (Fig. 5B markup).
(Re Claim 13) Yang teaches a semiconductor structure, comprising: a first die structure (Fig. 5B markup); a second die structure (Fig. 5B markup) bonded (¶47) over the first die structure; a conductive via (70; Fig. 5B) extending partially through the second die structure (Fig. 5B); and a conductive member (lower 84; Fig. 5B) coupled with the conductive via (Fig. 5B), wherein a first outer surface (lower side; Fig. 5B) of the conductive member contacting the conductive via is substantially planar (Fig. 5B).
Yang does not explicitly teach a semiconductor structure comprising:
the second die structure bonded over the first die structure and including an isolation member;
a dielectric member disposed over the second die structure; a conductive via extending through the dielectric member;
a spacer extending through the dielectric member and the isolation member and partially through the second die structure; and
a conductive member disposed over the dielectric member, wherein the first outer surface of the conductive member contacting the dielectric member and the spacer is substantially planar, and
wherein the conductive via is partially surrounded by the spacer, and wherein the spacer is disposed on the isolation member so that a sidewall of the conductive via partially contacts the spacer and partially contacts the isolation member.
Park teaches forming an isolation member (144a; Fig. 9) within a substrate (110; Fig. 9) having a via (168; Fig. 13) extending through it (Fig. 12 and 13).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to introduce an isolation member into the second die structure of Yang, such that it extends into the second die structure as taught by Park (compare the orientation of the semiconductor device 152 of Park with the devices 112 of Yang) to relieve stress generated by the via of Yang (Park: ¶¶82-83).
Kao teaches forming a dielectric member (202+204+206; Fig. 8) on the backside of a die structure (elements below 202 in Fig. 8) before forming a via extending through the dielectric member and a substrate (102; Fig. 9 to 12).
A PHOSITA would find it obvious to form a dielectric member on the backside of the second die structure, before forming the conductive via 70 of modified Yang such that via 70 extends through the dielectric member taught by Kao, in order to reduce the surface roughness of the backside as a result of thinning the second die structure 110 to reduce thickness before further processing. Doing so reduces device leakage (Kao: ¶24).
This results in modified Yang teaches a dielectric member disposed over the second die structure, and the conductive via extending through the dielectric member (Fig. 5B markup).
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Shih teaches utilizing an isolation member (212; Fig. 7) as an etch stop for forming an opening that is eventually used to form a conductive via (230+260; Fig. 14).
A PHOSITA would find it obvious to stop the etch when forming the opening ultimately used for forming the conductive via of modified Yang, in the manner taught by Shih, as a consequence of different materials used for the isolation member and the second die structure (Shih: ¶24; Yang: ¶13; Park: ¶40), and in order to allow for other, smaller openings formed at the same time, such as for signal routing, to have a difference in their etch rate reduced (Shih: ¶24).
Tsai teaches forming a spacer (114; Fig. 1B) after utilizing an isolation member as an etch stop (Fig. 1B, ¶28).
A PHOSITA would find it obvious to deposit a spacer within the opening used to form the conductive via of modified Yang after the isolation member has been utilized as an etch stop, before punching through the isolation member as taught by Tsai, to provide passivation and insulation between the conductive via and both the devices within the second die structure and the isolation member (Tsai: ¶31).
Gambino teaches forming a multilayered spacer (30+80; Fig. 4C) within an opening used for a conductive via (70; Fig. 4E), before punching through to an interconnect structure (21; Fig. 4D). The conductive via partially contacts the spacer (Fig. 4E).
A PHOSITA would find it obvious to form the spacer of Gambino within the opening used to form the conductive via of modified Yang, instead of that taught by Tsai, to allow for the spacer to provide a self-alignment function for forming an opening to the underlying interconnect layers of the second die structure (Gambino: “Spacer 80S may be self-aligned with metal pad 21 in insulator layer 20” (¶43)).
Due to the conformal deposition of the spacer of Gambino above the isolation member of modified Yang, modified Yang further teaches a semiconductor structure wherein the conductive via is partially surrounded by a spacer (Gambino: 30+80; Fig. 4C), and wherein the spacer is disposed on the isolation member so that a sidewall (left) of the conductive via partially contacts the spacer and the partially contacts the isolation member (modified Yang’s Fig. 5B markup below; note that the conductive via is now surrounded by Gambino’s spacer 30+80).
This results in modified Yang teaching a spacer (Gambino: 30+80) extending through the dielectric member and the isolation member (see 112(b) rejection above) and partially through the second die structure (modified Yang’s Fig. 5B markup).
Furthermore, Kao teaches planarizing the surface of the dielectric member after forming a conductive via (Fig. 11, ¶50).
A PHOSITA would find it obvious to planarize the surface of the dielectric member as taught by Kao after forming the conductive via of modified Yang, to prevent irregular geometry of the top surface from interfering with subsequent film deposition, and to electrically isolate the via from the rest of the top surface of the dielectric member.
Doing so results in modified Yang teaching the first outer surface of the conductive member contacting the dielectric member, the spacer, and the conductive via is substantially planar.
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(Re Claim 14) Modified Yang semiconductor structure of Claim 13, further comprising a passivation (82; Fig. 5B) disposed over the dielectric member and covering at least a portion of the conductive member, wherein the first outer surface of the conductive member and an interface between the passivation and the dielectric member are at a same level (Fig. 5B markup).
(Re Claim 15) Modified Yang teaches the semiconductor structure of Claim 14, further comprising a conductive bump (90; Fig. 5B) disposed over the conductive member and protruded from the passivation (Fig. 5B).
(Re Claim 16) Modified Yang teaches the semiconductor structure of Claim 13, wherein the spacer comprises:
a first liner (Gambino: 30; Fig. 4D) comprising:
a bottom portion (Gambino’s Fig. 4D markup) disposed on the isolation member (modified Yang’s Fig. 5B markup showing the incorporation of Gambino’s teachings); and
an extending portion (Gambino’s Fig. 4D markup) extending from the bottom portion of the first liner to the conductive member (modified Yang’s Fig. 5B markup showing the incorporation of Gambino’s teachings); and
a second liner (Gambino: 80; Fig. 4D) disposed on the bottom portion of the first liner and between the extending portion of the first liner and the conductive via (Gambino’s Fig. 4D, and modified Yang’s Fig. 5B markup showing the incorporation of Gambino’s teachings).
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(Re Claim 17) Modified Yang teaches the semiconductor structure of Claim 13, wherein a second outer surface (top surface; Fig. 5B) of the conductive member contacting the passivation and disposed above the first outer surface is substantially planar (Fig. 5B).
(Re Claim 18) Modified Yang teaches the semiconductor structure of Claim 17, wherein the first outer surface is substantially parallel to the second outer surface (Fig. 5B).
(Re Claim 21) Yang semiconductor structure, comprising: a die structure (first and second die structures of Fig. 5B markup); a conductive via extending partially through the die structure; and a conductive member (lower 84; Fig. 5B) coupled with the conductive via, wherein the conductive member is in contact with the conductive via (Fig. 5B).
Yang does not explicitly teach a semiconductor structure comprising:
a dielectric member disposed over the die structure; the conductive via extending through the dielectric member;
an isolation member disposed within the die structure;
a spacer disposed on the isolation member and extending through the dielectric member and partially through the die structure; and
the conductive member disposed over the dielectric member, wherein the conductive member is in contact with the spacer, and
wherein the conductive via is partially surrounded by the spacer so that a sidewall of the conductive via partially contacts the spacer and partially contacts the isolation member.
Park teaches forming an isolation member (144a; Fig. 9) within a substrate (110; Fig. 9) having a via (168; Fig. 13) extending through it (Fig. 12 and 13).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to introduce an isolation member into the die structure of Yang, such that it is disposed with the die structure as taught by Park (compare the orientation of the semiconductor device 152 of Park with the devices 112 of Yang) to relieve stress generated by the via of Yang (Park: ¶¶82-83).
Kao teaches forming a dielectric member (202+204+206; Fig. 8) on the backside of a die structure (elements below 202 in Fig. 8) before forming a via extending through the dielectric member and a substrate (102; Fig. 9 to 12).
A PHOSITA would find it obvious to form a dielectric member on the backside of the second die structure, before forming the conductive via 70 of modified Yang such that via 70 extends through the dielectric member taught by Kao, in order to reduce the surface roughness of the backside as a result of thinning the die structure 110 to reduce thickness before further processing. Doing so reduces device leakage (Kao: ¶24).
This results in modified Yang teaches a dielectric member disposed over the second die structure, and the conductive via extending through the dielectric member (Fig. 5B markup).
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Shih teaches utilizing an isolation member (212; Fig. 7) as an etch stop for forming an opening that is eventually used to form a conductive via (230+260; Fig. 14).
A PHOSITA would find it obvious to stop the etch when forming the opening ultimately used for forming the conductive via of modified Yang, in the manner taught by Shih, as a consequence of different materials used for the isolation member and the die structure (Shih: ¶24; Yang: ¶13; Park: ¶40), and in order to allow for other, smaller openings formed at the same time, such as for signal routing, to have a difference in their etch rate reduced (Shih: ¶24).
Tsai teaches forming a spacer (114; Fig. 1B) after utilizing an isolation member as an etch stop (Fig. 1B, ¶28).
A PHOSITA would find it obvious to deposit a spacer within the opening used to form the conductive via of modified Yang after the isolation member has been utilized as an etch stop, before punching through the isolation member as taught by Tsai, to provide passivation and insulation between the conductive via and both the devices within the die structure and the isolation member (Tsai: ¶31).
Gambino teaches forming a multilayered spacer (30+80; Fig. 4C) within an opening used for a conductive via (70; Fig. 4E), before punching through to an interconnect structure (21; Fig. 4D). The conductive via partially contacts the spacer (Fig. 4E).
A PHOSITA would find it obvious to form the spacer of Gambino within the opening used to form the conductive via of modified Yang, instead of that taught by Tsai, to allow for the spacer to provide a self-alignment function for forming an opening to the underlying interconnect layers of the die structure (Gambino: “Spacer 80S may be self-aligned with metal pad 21 in insulator layer 20” (¶43)).
Due to the conformal deposition of the spacer of Gambino above the isolation member of modified Yang, modified Yang further teaches a semiconductor structure wherein the conductive via is partially surrounded by a spacer (Gambino: 30+80; Fig. 4C), and wherein the spacer is disposed on the isolation member so that a sidewall (left) of the conductive via partially contacts the spacer and the partially contacts the isolation member (modified Yang’s Fig. 5B markup below; note that the conductive via is now surrounded by Gambino’s spacer 30+80).
This results in modified Yang teaching a spacer (Gambino: 30+80) disposed on the isolation member and extending through the dielectric member and partially through the second die structure and partially through the die structure (modified Yang’s Fig. 5B markup).
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(Re Claim 22) Modified Yang teaches the semiconductor structure of Claim 21, the spacer, wherein the spacer comprises:
a first liner (Gambino: 30; Fig. 4D) comprising:
a bottom portion (Gambino’s Fig. 4D markup) disposed on the isolation member (modified Yang’s Fig. 5B markup showing the incorporation of Gambino’s teachings); and
an extending portion (Gambino’s Fig. 4D markup) extending from the bottom portion of the first liner to the conductive member (modified Yang’s Fig. 5B markup showing the incorporation of Gambino’s teachings); and
a second liner (Gambino: 80; Fig. 4D) disposed on the bottom portion of the first liner and between the extending portion of the first liner and the conductive via (Gambino’s Fig. 4D, and modified Yang’s Fig. 5B markup showing the incorporation of Gambino’s teachings).
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Response to Arguments
Applicant's arguments filed 5/7/2026 have been fully considered but they are moot in view of the new rejection.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Christopher A Schodde whose telephone number is (571)270-1974. The examiner can normally be reached M-F 1000-1800 EST.
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/CHRISTOPHER A. SCHODDE/Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898
Prosecution Insights