Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 02/11/2026 has been entered.
Response to Arguments/Amendments
Applicant's amendments to claim 1 and corresponding arguments, pages 8-9 of the remarks, filed 02/11/2026, with respect to the 35 U.S.C 103 rejection of claim 1 as unpatentable over US 2021/0098376 A1; Lin et al.; (hereinafter “Lin”) in view of US 2019/0067097 A1; Wang et al.; (hereinafter “Wang”) have been fully considered and are not found persuasive.
Applicant argues that the references used in Office Action, filed 11/12/2025, do not teach the limitation: “the first protrusion has a first width in the plan view, the recess has a second width in the plan view and the second protrusion has a third width in the plan view, wherein the first width and the third width are greater than the second width” recited in the amended claim 1. However, examiner respectfully disagrees. Lin in view of Wang does provide a clear teaching of the amended claimed limitations. (See 35 U.S.C. 103 rejection of amended claim 1 below).
Applicant's amendments to claim 9 and corresponding arguments, pages 9-10 of the remarks, filed 02/11/2026, with respect to the 35 U.S.C 103 rejection of claim 9 as unpatentable over Lin in view of Wang have been fully considered and are not found persuasive.
Applicant argues that the references used in Office Action, filed 11/12/2025, do not teach all of the limitations as recited in the amended claim 9. However, examiner respectfully disagrees. Lin in view of Wang does provide a clear teaching of the amended claimed limitations. (See 35 U.S.C. 103 rejection of amended claim 9 below).
Applicant's amendments to claim 21 and corresponding arguments, page 10 of the remarks, filed 02/11/2026, with respect to the 35 U.S.C 103 rejection of claim 21 as unpatentable over Lin in view of Wang have been fully considered and are not found persuasive.
Applicant argues that the references used in Office Action, filed 11/12/2025, do not teach the limitations: “the first contact structure includes a first terminal end interfacing the dielectric layer and the second contact structure includes a first terminal end interfacing the dielectric layer” and “the non-linear shape being disposed vertically over and covering the first terminal end of each of the first contact structure and the second contact structure in the top view” as recited in the amended claim 21. However, examiner respectfully disagrees. Lin in view of Wang does provide a clear teaching of the amended claimed limitations. (See 35 U.S.C. 103 rejection of amended claim 21 below).
Claim Objections
Claim 21 is objected to because of the following informalities:
Claim 21, ln. 6: “over the gate” should read “over the first gate”
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-15 and 21-25 are rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Wang.
Regarding Claim 1 (currently amended), Lin teaches method of manufacturing a semiconductor structure ([0010], method for fabricating vias within interconnect structure to reduce contact resistance), comprising:
providing a substrate (#210, Figure 2, substrate) having a first source/drain feature (#240B, source/drain feature) formed over the substrate (#210);
forming a first contact structure (#282A, Figure 4, source/drain contact) on the first source/drain feature (#240B);
forming a second contact structure (#282B, source/drain contact), the second contact structure being a next adjacent contact structure to the first contact structure in a first direction in a top view (from a top view of Figure 4, #282A and #282B are adjacent structures in both #X and #Y directions);
depositing a dielectric layer (#292, Figure 5, interlayer dielectric layer or ILD) over the first contact structure (#282A) and the second contact structure (#282B);
etching an opening (#300A, Figure 6, interconnect opening) in the dielectric layer to define a via opening ([0034], using mask layer #308, #292 is etched to define #300A), wherein the second direction is perpendicular to the first direction in the top view (directions #X-Z are perpendicular in any views);
filling the opening (#300A, Figure 7A, interconnect openings) with conductive material (#330, Figure 8A, bulk material includes tungsten or other metals is used to fill #300A, see also [0041]) to form a via (#350A, Figure 15, a via) connected to the first contact structure (Figure 15, #350A connects to #282A); and
forming a metal line (#394A, Figure 16, conductive line) above the via (Figure 16, #394A forms above #350A).
Lin does not explicitly teach the opening in the dielectric layer has a non-linear shape in a plan view, the non-linear shape has a first protrusion in a second direction in the top view and disposed over the first contact structure and a second protrusion in the second direction in the top view and disposed over the second contact structure, and the non-linear shape includes a recess in the second direction in the top view between the first protrusion and the second protrusion, and wherein the first protrusion has a first width in the plan view, the recess has a second width in the plan view and the second protrusion has a third width in the plan view, wherein the first width and the third width are greater than the second width, and to form the via connected to the second contact structure.
However, Wang teaches a method of manufacturing a semiconductor structure ([0051], method of fabricating integrated circuit includes at least forming conductive contact on active regions), wherein the opening (#308, Figure 3A of Wang annotated (1) below, conductive via feature) in the dielectric layer (#103, isolation feature) has a non-linear shape in a plan view (#308 has a curved shape), the non-linear shape has a first protrusion in a second direction in the top view and disposed over the first contact structure (protrusion #P2 along direction #Y over contact #106A), and a second protrusion in the second direction in the top view and disposed over the second contact structure (protrusion #P3 along direction #Y over contact #106C), and the non-linear shape includes a recess in the second direction (recess #I1 of via #308 extends along direction #Y) in the top view between the first protrusion and the second protrusion (#I1 between #P2 and #P3), and wherein the first protrusion has a first width (#W1) in the plan view, the recess has a second width (#W2) in the plan view and the second protrusion has a third width (#W3) in the plan view, wherein the first width and the third width are greater than the second width (#W1 and #W3 is greater than #W2) and to form a via connected to the second contact structure (via #308 connects to contact features #106A and #106E).
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It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teaching of Lin with Wang in order to increase contact area and clearance between features which minimize the risk of shorting and negative effect of high resistance and speed degradation according to [0002] and [0023] of Wang.
Regarding Claim 2, Lin in view of Wang teaches the method as described in claim 1, wherein Lin further teaches the providing the substrate (#210, Figure 2, substrate) includes epitaxially growing the first source/drain feature (#240A-#240D, epitaxial source/drain features) on a fin extending from the substrate (Figure 2, [0021], a portion of #210 is a fin structure extending and wrapping the recesses of #240A-#240D).
Regarding Claim 3, Lin in view of Wang teaches the method as described in claim 2, wherein Lin further teaches the forming the first contact structure (#282A, Figure 4, source/drain contact) includes:
depositing a metal layer (#286, Figure 4, contact bulk layer contains metal such as tungsten according to [0030]) on the epitaxially grown first source/drain feature (#286 disposes in region above epitaxial source/drain feature #240B); and
forming a silicide (#280, Figure 4, silicide layer) between the epitaxially grown first source/drain feature and the metal layer (#280 forms between #240B and #286).
Regarding Claim 4, Lin in view of Wang teaches the method as described in claim 1, wherein Lin further teaches the depositing the dielectric layer (#292, Figure 5, interlayer dielectric layer or ILD layer) includes depositing an etch stop layer (#294, contact etch stop layer or CESL) and an interlayer dielectric (ILD) layer (#292, ILD layer).
Regarding Claim 5, Lin in view of Wang teaches the method as described in claim 1, wherein Lin further teaches the filling the opening (#300A, Figure 7A, interconnect openings) with conductive material (#330, Figure 8A, bulk material includes tungsten or other metals is used to fill #300A, see also [0041]) includes depositing a metal (Figure 8A, #330 is of metal material) directly on the first contact structure (Figure 8A, #330 disposes over the metal contact bulk layer #286) by a bottom-up deposition process (according to [0041], a bottom-up deposition process is used to fill the opening with #330).
Regarding Claim 6, Lin in view of Wang teaches the method as described in claim 5, wherein Lin further teaches the filling the opening (#300B, Figure 7A, interconnect openings) includes completely filling the opening with the metal (#330, Figure 8A, bulk material includes tungsten or other metals, see also [0041], wherein #330 fills #300B completely).
Regarding Claim 7 (currently amended), Lin in view of Wang teaches the method as described in claim 1.
Lin does not teach the etching the opening having the non-linear shape includes forming the recess over a gate structure in the plan view.
However, Wang teaches the etching the opening having the non-linear shape (Figure 3A of Wang annotated (1), conductive via feature #308 has a curved shape) includes forming the recess over a gate structure in the plan view (#308 has recess over gate stacks #104B-C).
It would have been obvious to one of ordinary skill in the art prior to effective filling date of the claimed invention to combine the teaching of Wang with Lin so that the etching the opening having the non-linear shape includes forming a shape having a protrusion over the first contact structure in a plan view for the reason set forth in the rejection of claim 1.
Regarding Claim 8 (currently amended), Lin in view of Wang teaches the method as described in claim 7, wherein Lin further teaches the via (#350A-B, Figure 16) interfaces an upper surface of the first contact structure (#282A), and upper surface of the second contact structure (#282B), and an upper surface of another dielectric layer (#254) extending between the first contact structure and the second contact structure
Lin does not teach the etching the opening having the non-linear shape disposes the first protrusion covering a first end region of the first contact structure and the second protrusion is at a second end region of the second contact structure.
However, Wang teaches the etching the opening having the non-linear shape (see rejection of claim 7) disposes the first protrusion covering a first end region of the first contact structure (Figure 3A of Wang annotated (1) above, curved via #308 has protrusion #P1 at end portion of contact #106E) and the second protrusion is at a second end region of the second contact structure (#308 has protrusion #P2 at end portion of contact #106A).
It would have been obvious to one of ordinary skill in the art prior to effective filling date of the claimed invention to combine the teaching of Wang with Lin for the reason set forth in the rejection of claim 1.
Regarding Claim 9 (currently amended), Lin teaches a method of manufacturing a semiconductor structure ([0010], method for fabricating vias within interconnect structure to reduce contact resistance), comprising:
forming a first gate structure (#230A, Figure 2, gate structure) and a second gate structure (#230B, gate structure) each extending in a first direction (#230A and #230B extends in direction #X) in a plan view;
providing a first source/drain feature (#240B, source/drain feature) between the first gate structure and a first side of the second gate structure (#240B disposes between #230A and #230B) and a second source/drain feature (#240C, source/drain feature) adjacent a second side of the second gate structure (#240C is adjacent or on the right side of #230B);
providing a first contact structure (#282A, Figure 4, source/drain contact) extending in the first direction, the first contact structure interfacing the first source/drain feature (Figure 4, #282A connects to #240B) and providing a second contact structure (#282B, source/drain contact) extending in the second direction (#282B extends in direction #Z), the second contact structure interfacing the second source/drain feature (#282B connects to #240C); wherein a first end of the first contact structure is collinear with a first end of the second contact structure (Figure 5, contacts #282A and #282B have collinear top surfaces) in the second direction of the plan view and a dielectric layer extends between the first contact structure (#282A) and the second contact structure (dielectric layer #254 extends between contacts #282A-B);
a via structure (#350A-B, Figure 16) covers the first end of the first contact structure (#282A), the second end of the second contact structure (#282B), and the dielectric layer (#350A-B covers dielectric layer #254 extending along direction #Y).
depositing a metal line (#394A-C, Figure 3A-B, conductive line) over the via structure (#350A-B).
Lin does not teach forming a via structure extending in the second direction from an interface with the first contact structure to an interface with the second contact structure, wherein the via structure is an undulating-shape in a top view; and the undulating-shape is within a width of the metal line in the top view.
However, Wang teaches a method of manufacturing a semiconductor structure ([0051], method of fabricating integrated circuit includes at least forming conductive contact on active regions), wherein the method comprises forming a via structure (#308, Figure 3A, curved conductive via feature) extending in the first direction from an interface with the first contact structure (#106A, conductive contact feature, wherein #308 is in contact with #106A) to an interface with the second contact structure (#106B, conductive contact feature, wherein #308 is in contact with #106B), wherein the via structure is an undulating-shape in a top view (#308 has a curved shape); and the undulating-shape is within a width of the metal line in the top view (#308 is within width of metal line #110).
It would have been obvious to one of ordinary skill in the art prior to effective filling date of the claimed invention to combine Wang with Lin in order to increase contact area and clearance between features which minimize the risk of shorting and negative effect of high resistance and speed degradation according to [0002] and [0023] of Wang.
Regarding Claim 10 (currently amended), Lin in view of Wang teaches the method as described in claim 1, wherein Lin further teaches the forming the via structure (see the rejection of claim 9) includes:
depositing another dielectric layer (#292, Figure 5, ILD layer) over the first contact (#282A) structure and the second contact structure (#282B) and the dielectric layer (#254);
defining a masking element (#308, Figure 6, mask layer) on the another dielectric layer (#292);
etching an opening (#300A, interconnect openings) having the undulating-shape (see the rejection of claim 9 for forming an undulating shape via structure) in the another dielectric layer (#292); and filling the undulating-shape opening with a metal (Figure 8A, metal bulk material #330 including tungsten or other metals is used to filled #300A, see also [0041]), wherein the metal filling the undulating-shape opening interfaces an upper surface of the first contact structure, an upper surface of the second contact structure, and an upper surface of the dielectric layer (#330 interfaces upper surface of contacts #282A-B and dielectric #254).
Lin does not explicitly teach the masking element defines the undulating-shape.
However, Wang teaches the masking element defines the undulating-shape (according to [0031], photomasks are used to define an S-curved shape for the conductive via feature #308).
It would have been obvious to one of ordinary skill in the art prior to effective filling date of the claimed invention to combine Wang with Lin so that the masking element defined the undulating-shape, as it would merely combine prior art elements according to known methods (using a mask layer to transfer the pattern to a subsequent layer, see also [0031] of Wang) to yield predictable results (transferred pattern defines the S-curved shape of the opening) (See MPEP 2143(I)).
Regarding Claim 11 (currently amended), Lin in view of Wang teaches the method as described in claim 10, wherein Lin further teaches the filling the undulating-shape opening with the metal (see the rejection of claim 10) includes a bottom-up deposition process of the metal (according to [0041] of Lin, a bottom-up deposition process is used to fill the opening with metal bulk material #330) directly on the upper surfaces of each of the first contact structure (#282A, Figure 8A) and the second contact structure (#282B).
Regarding Claim 12 (currently amended), Lin in view of Wang teaches the semiconductor structure as described in claim 9.
Lin does not teach the forming the via structure includes forming the via structure having a first convex portion extending over the first end of the first contact structure and a second convex portion over the first end of the second contact structure in the plan view.
However, Wang teaches the forming the via structure (see the rejection of claim 9) includes forming the via structure (#308, Figure 3A annotated (2) below, conductive via feature) having a first convex portion (portion #CV1 of #308 has convex portion) extending over the first end of the first contact structure (#106E, conductive contact feature, wherein the convex portion of #CV1 disposes over #106E) and a second convex portion (Figure 3A annotated (2), according to [0048] of Wang, #308 can further extend to cover additional contact features on either sides #R1/#R2. Therefore, a portion #CV2 or #CV3 of #308 can have convex portion) over the first end of the second contact structure (#106A or #106C, conductive contact feature, wherein the convex portion of #CV2 or #CV3 disposes over #106A or #106C respectively).
It would have been obvious to one of ordinary skill in the art prior to effective filling date of the claimed invention to combine Lin with Wang so that the forming the via structure includes forming the via structure having a first convex portion over the first contact structure and a second convex portion over the second contact structure for the reason set forth in the rejection of claim 9.
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Regarding Claim 14, Lin in view of Wang teaches the method as described in claim 12.
Lin does not explicitly teach the forming the via structure includes forming the via structure having a concave portion between the first convex portion and the second convex portion having a smaller thickness in the plan view than the first convex portion and the second convex portion.
However, Wang teaches the forming the via structure (see the rejection of claim 9) includes forming the via structure (#308, Figure 3A annotated (2), conductive via feature) having a concave portion (#CV1 have a concave portion) between the first convex portion and the second convex portion (concave portion of #CV1 locates between the convex portion of #CV1 and the convex portion of #CV2) having a smaller thickness in the plan view than the first convex portion and the second convex portion (concave portion thickness #W2 is smaller than thickness #W1 and #W3 of first and second convex portion ).
It would have been obvious to one of ordinary skill in the art prior to effective filling date of the claimed invention to combine Wang with Lin so that the forming the via structure includes forming the via structure having a concave portion between the first convex portion and the second convex portion for the reason set forth in the rejection of claim 9.
Regarding Claim 15, Lin in view of Wang teaches the method as described in claim 14.
Lin does not explicitly teach forming a third contact structure extending in the first direction, wherein the concave portion is aligned with the third contact structure in the first direction.
However, Wang teaches forming a third contact structure (#106E, Figure 3A annotated (2), conductive contact feature) extending in the first direction (#106E extends along Y-direction), wherein the concave portion (Figure 3A annotated (2), #CV1 has a concave portion) is aligned with the third contact structure in the first direction (concave portion of #CV1 aligns with #106E along the Y-direction).
It would have been obvious to one of ordinary skill in the art prior to effective filling date of the claimed invention to combine Wang with Lin so that the method comprises forming a third contact structure extending in the first direction, wherein the concave portion is aligned with the third contact structure in the first direction for the reason set forth in the rejection of claim 9.
Regarding Claim 21 (currently amended), Lin teaches a method of fabricating a semiconductor device ([0010], method for fabricating vias within interconnect structure to reduce contact resistance), comprising:
providing a first active region and a second active region extending in a first direction in a top view (not explicitly shown in Figure 2, according to [0016], multiple active device regions form in the substrate #210 and are separated by isolation features, wherein from a top view, #210 forms to extend in all directions #X/#Y);
forming a first gate (#230A, Figure 2) and a second gate (#230B) each extending in a second direction in the top view;
forming a dielectric layer (#254) over the gate and the second gate;
forming a first contact structure (#282A, Figure 4, source/drain contact) extending in a second direction in the top view (from top view, #282A extends in all directions #X/#Y), the first contact structure interfacing a first source/drain feature (#240B, source/drain contact #282A connects to #240B) on the first active region (active region of #210) and a second contact structure (#282B, source/drain contact) extending in the second direction (#282B extends in direction #Z), the second contact structure interfacing a second source/drain feature (#240C, source/drain contact #282B connects to #240C) of the second active region (active region of #210), wherein the second direction is perpendicular the first direction in the top view (directions #X-#Z are perpendicular in any views), wherein the first contact structure includes a first terminal end interfacing the dielectric layer and the second contact structure includes a first terminal end interfacing the dielectric layer (Figure 4, top surface of contacts #282A-B interface dielectric #254).
Lin does not teach forming a via structure extending in the first direction, wherein the via structure interfaces the first contact structure and the second contact structure, wherein the via structure is a non-linear shape in a top view, the non-linear shape including a concave portion extending from over the first gate to over the second gate in the top view and the non-linear shape being disposed vertically over and covering the first terminal end of each of the first contact structure and the second contact structure in the top view.
However, Wang teaches a method of manufacturing a semiconductor structure ([0051], method of fabricating integrated circuit includes at least forming conductive contact on active regions), wherein the method comprises forming a via structure extending in the first direction (#308, Figure 3A, a curved conductive via feature extends in X-direction), wherein the via structure interfaces the first contact structure (#106A, conductive contact feature) and the second contact structure (#106B, conductive contact feature), wherein the via structure is a non-linear shape in a top view (#308 has a curved shape), the non-linear shape including a concave portion extending from over the first gate to over the second gate in the top view (Figure 3A of Wang annotated (2) above, concave portion #CV1 extends over gate stacks #104B and #104C) and the non-linear shape being disposed vertically over and covering the first terminal end of each of the first contact structure and the second contact structure in the top view (Figure 3A-B, #308 covers at least an end portion of contacts #106A-C).
It would have been obvious to one of ordinary skill in the art prior to effective filling date of the claimed invention to combine Wang with Lin so that the method comprises forming a via structure extending in the first direction, wherein the via structure interfaces the first contact structure and the second contact structure, wherein the via structure is a non-linear shape in a top view in order to increase contact area and clearance between features which minimize the risk of shorting and negative effect of high resistance and speed degradation according to [0002] and [0023] of Wang.
Regarding Claim 22 (currently amended), Lin in view of Wang teaches the method as described in claim 21, wherein Lin further teaches the forming the via structure (see rejection of claim 21) includes:
etching an opening (#300A-B, Figure 6, interconnect openings) in the dielectric layer (#292, ILD layer) extending in a third direction and the first direction to contact an upper surface of the first contact structure and the second contact structure (Figure 6, #300A-B extend directions #X-Z contacting top surfaces of contacts #282A and #282B);
the third direction perpendicular to the first direction and the second direction (directions #X-Z are perpendicular).
Lin does not teach the opening has the non-linear shape including a plurality of convex regions and a plurality of concave regions in the top view.
However, Wang teaches the opening (#308, Figure 3A, conductive via feature) has the non-linear shape (Figure 3A, #308 has a curved shape) including a plurality of convex regions and a plurality of concave regions in the top view (Figure 3A annotated (2), #308 includes portions #CV1, #CV2 and #CV3 with multiple convex and concave regions).
It would have been obvious to one of ordinary skill in the art prior to effective filling date of the claimed invention to combine Wang with Lin for the reason set forth in the rejection of claim 21.
Regarding Claim 23 (currently amended), Lin in view of Wang teaches the method as described in claim 22, wherein Lin further teaches the first terminal end of the first contact structure interfacing the dielectric layer, and the first terminal end of the second contact structure interfacing the dielectric layer (Figure 4, top surfaces of contacts #282A-B interface dielectric #254).
Lin does not explicitly teach a first convex region of the plurality of convex regions of the opening exposes the first contact structure, and a second convex region of the plurality of convex regions of the opening exposes the second contact structure.
However, Wang teaches a first convex region of the plurality of convex regions of the opening (Figure 3A annotated (2), convex portion of #CV1 of the multiple convex portions of #CV1, #CV2 and #CV3 of #308) exposes the first contact structure (#106E, conductive contact feature, wherein convex portion of #CV1 only covers a portion of and exposes the remaining of #106E) and a second convex region of the plurality of convex regions of the opening (convex portion of #CV2 of the multiple convex portions of #CV1, #CV2 and #CV3 of #308) exposes the second contact structure (#106A, conductive contact feature, wherein convex portion of #CV2 only covers a portion of and exposes the remaining of #106A).
It would have been obvious to one of ordinary skill in the art prior to effective filling date of the claimed invention to combine Wang with Lin so that a first convex region of the plurality of convex regions of the opening exposes the first contact structure and a second convex region of the plurality of convex regions of the opening exposes the second contact structure for the reason set forth in the rejection of claim 21.
Regarding Claim 24, Lin in view of Wang teaches the method as described in claim 23.
Lin does not explicitly teach at least one convex region of the plurality of convex regions of the opening interposes the first and second convex regions in the first direction in the top view.
However, Wang teaches at least one convex region of the plurality of convex regions of the opening (Figure 3A of Wang annotated (2) above, convex portion of #CV1 of the multiple convex portions of #CV1, #CV2 and #CV3 of #308) interposes the first and second convex regions in the first direction in the top view (#CV1 disposes between #CV2 and #CV3 along direction #X).
It would have been obvious to one of ordinary skill in the art prior to effective filling date of the claimed invention to combine Wang with Lin for the reason set forth in the rejection of claim 21.
Regarding Claim 25 (currently amended), Lin in view of Wang teaches the method as described in claim 22, wherein Lin further teaches the forming the via structure (see the rejection of claim 21) includes filling the opening (#300B, Figure 8A, interconnect openings) in the dielectric layer (#292, ILD layer) with a conductive material (#330, bulk material includes tungsten or other metals, see also [0041]) filling the plurality of convex region and the plurality of concave regions (see the rejection of claim 22. Figure 8A, #330 fills #300B completely, therefore, the convex and concave regions of the via structure are also filled observing from a top view), the conductive material interfacing an uppermost surface of the dielectric layer interfacing the first terminal end of the first contact structure (Figure 8A, bulk material #330 interfaces top surface of dielectric #254 and an end portion of contact #282A).
Allowable Subject Matter
Claim 13 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 13, the most relevant prior arts of record, Lin in view of Wang discloses a method of manufacturing a semiconductor structure as described in claim 12.
Wang further discloses convex portions of a via structure having different distances to their respective apex (Figure 11B of Wang), and the via structure having a same thickness over a first and second contact structures in a plan view.
None of the prior art of record discloses or makes obvious the limitations: “providing a different thickness in the via structure in the plan view over the first contact structure than over the second contact structure” recited in claim 13, in combination with the other claimed method steps.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US20220301932A1 – Figure 20A and [0020]
US20220223517A1 – Figures 18-21
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