DETAILED ACTION
This application, 17/813,592, attorney docket 8017-939-DIV, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This application is assigned Samsung Display Co, and claims foreign priority to 10-2019-0003450, filed 01/10/2019. A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/11/2025 has been entered. Claims 1, 2 and 4-7 are pending and are considered below. Note that examiner will use numbers in parentheses to indicate numbered elements in prior art figures, and brackets to point to paragraph numbers where quoted material or specific teachings can be found.
This is a corrected final action that acknowledged the foreign priority in the PTO326 summary form and responds to the after final request filed 9/9/2025.
Response to Arguments
Applicant argues in his response filed 11/17/2025, applicant has amended drawings 13 15 and 29 to effectively show the boundaries of the electrodes by changing the linewidths of the electrodes and lightening the remaining lines, and additionally shading the transistor semiconductor layers which define the boundaries of the transistors. Examiner agrees that the amendments overcome the drawing objection issued in the office action 9/17/25. Applicant has amended his claims to remove the limitation “light transmissive region, so the §112b rejection based on that limitation is moot and withdrawn.
Examiner notes that the previous office action did not include a rejection on the merits, but the amended claims have clarified the invention, and a new rejection is presented below.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. A voltage line formed in a same layer as the plurality of pixel electrodes recited in at least claim 1 and claim 5 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. Although the specification mentions “the second pixel region might not include voltage line disposed on a same layer as the pixel electrodes” [0023], it provides no guidance as to where it might be, and the only embodiment describes “A third conductive layer including the pixel electrodes 191a, 191b, and 191c and the voltage line 192 may be disposed on the passivation layer 180,” which is shown in figure 14.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1, 2, 4-7 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1 and 5 recite “plurality of second pixels in each of which a pixel circuit and a pixel electrode of the plurality of pixel electrodes are disposed … wherein a part of each of the plurality of pixel electrodes overlaps the third transistor in a plan view…” It is not clear whether the claim requires one pixel electrode overlapping each third transistor in each pixel circuit, or that all of the pixel electrodes must overlap the third transistor.
Claims 2 and 7 recite, “the second pixel”, which lacks antecedent. Claims 1 and 5 recite “a plurality of second pixels”, so it is not clear which second pixel is being limited.
Claims 4 and 7 recite, “the first pixel electrode and the third pixel electrode have a planar shape having a maximum width in the first direction between the first scan line and the control line, (both have a maximum width that extends beyond the control line 153 in figure 29) and the second pixel electrode has a planar shape having a maximum width in the first direction in a region overlapping the second scan line.
It is not clear how the widths are being limited by the control and scan lines, and it is not clear what the term planar shape means in reference to the width in the first direction, which is assumed by the examiner to be DR2 in figure 29.
Dependent claims include the defect of the parent.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1,2, 5 and 6 are rejected under 35 U.S.C. 102a1/a2 as being anticipated by Ota et al. (U.S. 2016/8/0064467).
As for claim 1,
Ota teaches a display device comprising:
a first display area including a plurality of first pixels (furthest line of pixels Pd from the signal line driving circuit 34 in figure 1);
and a second display area (third line of pixels Pe) including a plurality of pixel electrodes (E1, figure 4),
the second display area further including a plurality of second pixels (Pd) in each of which a pixel circuit (lower layers of figure 4 including transistors Tcmp, Tsl Tdr and Tel) and a pixel electrode (E1) of the plurality of pixel electrodes are disposed,
and a plurality of first regions adjacent to the second pixels (far left and far right of figure 4 at 65), wherein none of the plurality of pixel electrodes are disposed in the first regions, and
wherein the pixel circuit of each of the second pixels includes a plurality of transistors (Tcmp, Tsl Tdr and Tel), wherein the plurality of transistors includes:
a first transistor (Tdr) including a first electrode and a second electrode (above and below the gate figure 8),
a second transistor (Tsl) connected to the first electrode of the first transistor and connected to a data line, and
a third transistor (Tel) connected to the second electrode of the first transistor (connections shown in figure 3),
wherein a part of each of the plurality of pixel electrodes overlaps the third transistor in a plan view (shown in cross section figure 4, plan view, overlay figure 8 with figure 13) ,
and wherein the display device does not include a voltage line formed in a same layer as the plurality of pixel electrodes. (41, 43-0 and 43-1 are all in layers below the pixel electrode E1 in figure 4)
As for claim 2,
Ota teaches display device of claim 1, wherein none of the plurality of pixel electrodes overlap the first regions. (They are offset to not overlap in figure 1).
As for Claim 5,
Ota teaches an electronic device comprising:
a first display area; including a plurality of first pixel regions (furthest line of pixels Pd from the signal line driving circuit 34 in figure 1);
and a second display area including a plurality of pixel electrodes (third line of pixels Pe) including a plurality of pixel electrodes (E1, figure 4),
the second display area including a plurality of second pixels (Pd) in each of which a pixel circuit (lower layers of figure 4 including transistors Tcmp, Tsl Tdr and Tel) and a pixel electrode (E1) of the plurality of pixel electrodes are disposed,
and a plurality of first regions adjacent to the second pixels wherein none of the plurality of pixel electrodes are disposed in the first regions (far left and far right of figure 4 at 65).
wherein the pixel circuit of each of the second pixels includes a plurality of transistors, wherein the plurality of transistors include:
a first transistor (Tdr) including a first electrode and a second electrode (above and below the gate figure 8),
a second transistor (Tel) connected to the first electrode of the first transistor and further connected to a data line (26 shown in figure 8), and
a third transistor connected to the second electrode of the first transistor (connections shown in figure 3),
and wherein a part of each of the plurality of pixel electrodes overlaps the third transistor in a plan view (shown in cross section figure 4, plan view, overlay figure 8 with figure 13), and
wherein the electronic device does not include a voltage line formed in a same layer as the plurality of pixel electrodes. (41, 43-0 and 43-1 are all in layers below the pixel electrode E1 in figure 4)
As for claim 6,
Ota teaches the electronic device of claim 5, wherein none of the plurality of pixel electrodes overlap the first regions. (They are offset to not overlap in figure 1).
Allowable Subject Matter
Claims 4 and 7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and if rewritten or amended to overcome the rejection under 35 U.S.C. 112(b) set forth in this Office action.
The following is a statement of reasons for the indication of allowable subject matter:
As for claim 4 and 7,
the prior art does not teach or make obvious the display of the parent claim the further includes a pixel circuit of the second pixel is connected to a first scan line, a second scan line, and a control line, which are disposed side by side in a first direction, the first pixel electrode and the third pixel electrode have a planar shape having a maximum width in the first direction between the first scan line and the control line, and the second pixel electrode has a planar shape having a maximum width in the first direction in a region overlapping the second scan line.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN A BODNAR whose telephone number is (571)272-4660. The examiner can normally be reached M-Th and every other Friday 7:30-5:30 Central time.
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/JOHN A BODNAR/Primary Examiner, Art Unit 2893