DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed on 03/04/2026 has been entered. Claims 1-20, remain pending in the application. Applicant’s amendments have overcome each and every 112(b) rejections previously set forth in the Non-Final Office Action mailed on 11/06/2025.
Drawings
Applicant amended the drawings in the amendment filed on 03/04/2026. Therefore, the drawings objections are withdrawn.
Claim Objections
Claim 4 is objected to because of the following informalities: “is respectively covered” should read “are respectively covered”. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4 and 6-20 are rejected under 35 U.S.C. 103 as being unpatentable over Gulbagh Singh et al., (United States Patent Application Publication Number, US 2018/0315723 A1), hereinafter referenced as Singh, in view of Eto, (United States Patent Number US 8344484 B2) hereinafter referenced as Eto.
Regarding claim 1, Singh teaches a semiconductor assembly comprising: a semiconductor die (Fig.3F, element #310 is part of the circuit region of a die, paragraph [0030], row 6; full circuit region is shown as element #110 of Fig.1, and is formed by all the elements in that region as shown in Fig.1, from element #162 down to element #120, including them) and a seal ring disposed adjacent to the semiconductor die (Fig.3F, formed by the components of regions #316 and #314, located above element #340, elements #356, #354a, #354b, #342, #360 and #362), wherein the seal ring comprises: a first side surface inclined from a top surface of the seal ring toward a bottom surface of the seal ring (Fig.3F, left side surface of element #362 is inclined from its top surface toward the bottom surface of the seal ring, where the bottom surface of the seal ring is the plane formed by the bottom surface of elements #356, #354a and #354b and the bottom surface of element #342 in the regions #316 and #314), wherein a lateral width of the bottom surface of the seal ring (Fig.3F, distance between the right side of element #314 and left side of element #316 along horizontal direction and the bottom surface) is larger than a lateral width of the top surface of the seal ring (Fig.3F, the distance between a point of the top surface of element #362 located in the same vertical plane as the right side of element #314 and the furthest left point of the top surface of element #362, along horizontal direction, is shorter); and a first dummy metal line disposed in the seal ring (Fig.3F, element #356 is equivalent to element #156 of Fig.1, which is a dummy metal line, paragraph [0015], rows 22-23) and comprising a second side surface adjacent to the first side surface of the seal ring (Fig.3F, left side surface of element #356, is adjacent to the left side surface of element #362) wherein a bottom surface of the first dummy metal line is substantially aligned with the bottom surface of the seal ring (Fig.3F, bottom surface of element #356 is aligned with the bottom surface of the seal ring as defined above).
Singh teaches a redistribution layer (RDL) structure disposed below the seal ring and the semiconductor die (Fig.1, elements #124, #126 and #128 located in the regions #114, #116 and #110, which are equivalent to regions #354, #356 and #310 respectively of Fig.3F), a passivation layer disposed between the seal ring and the RDL structure (Fig.3F, element #340); and a protection layer disposed on and in contact with the passivation layer and the first dummy metal line and including an inclined side surface (Fig.3F, element #342, is in contact with elements #340 and #356 and has an inclined surface on left side surface of element #356), and the first side surface of the seal ring is inclined from the top surface of the seal ring toward an upper end of the inclined side surface of the protection layer (Fig.3F, left side surface of element #362 is inclined towards the upper end of the inclined side surface of the protection layer, element #340 located on left side surface of element #356).
Singh does not teach wherein he first side surface of the seal ring is substantially continuous with the inclined side surface of the protection layer, and the inclined side surface of the protection layer is substantially continuous with an outermost side surface of the passivation layer. Eto teaches the first side surface of the seal ring is substantially continuous with the inclined side surface of the protection layer, and the inclined side surface of the protection layer is substantially continuous with an outermost side surface of the passivation layer (Fig.1, right side of element #213 is continuous with the right side surface of element #212, which is continuous with the right side surface of the passivation layer formed by elements #209 and #208). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Eto and disclose the first side surface of the seal ring is substantially continuous with the inclined side surface of the protection layer, and the inclined side surface of the protection layer is substantially continuous with an outermost side surface of the passivation layer. Having side surfaces of the seal ring, the passivation layer and the protection layer substantially continuous mitigates the presence of sharp surface points/corners that may chip away during wafer dicing and can result in reliability problems during the following packaging steps. Furthermore, having exposed and continuous outermost side surfaces of the passivation and protection layers eliminates the need for dicing these layers, which reduces the thickness of the die in the dicing region and thus reduces the stress during dicing the remainder of the die layers.
Regarding claim 2, the combination of Singh and Eto teaches the semiconductor assembly of claim 1 as set forth in the obviousness rejection. Singh further teaches an angle between the first side surface of the seal ring (Fig.3F, left side of element #162) and the bottom surface of the seal ring (Fig.3F, top surface of element #340), is acute (range 0 to 90 degrees). It would have been obvious to one ordinary skilled in the art before the effective filling date of the claimed invention, to optimize the angle through routine experimentation (MPEP 2144.05). The angle is a result effective variable because it needs to be optimized based on the singulation tool and technique used during die singulation, in order to prevent or reduce chipping.
Regarding claim 3, the combination of Singh and Eto teaches the semiconductor assembly of claim 1 as set forth in the obviousness rejection. Singh further teaches the semiconductor assembly of claim 1, wherein a portion of the protection layer is in contact with a top surface of the first dummy metal line (Fig.3F, a portion of element #342, is in contact with the top surface of the dummy metal line, element #356).
Regarding claim 4, the combination of Singh and Eto teaches the semiconductor assembly of claim 1 as set forth in the obviousness rejection. Singh does not teach the semiconductor assembly of claim 3, wherein the top surface and the second side surface of the first dummy metal line are respectively covered by the seal ring. Eto teaches wherein the top surface and the second side surface of the first dummy metal line are respectively covered by the seal ring (Fig.1, the top and right side surface of element #211c are covered by element #213). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Eto and disclose wherein the top surface and the second side surface of the first dummy metal line are respectively covered by the seal ring. The seal ring protects the metal lines from outside environmental factors, thus preventing their degradation.
Regarding claim 6, the combination of Singh and Eto teaches the semiconductor assembly of claim 1 as set forth in the obviousness rejection. Singh further teaches the semiconductor assembly of claim 1, wherein the protection layer includes a SiNx film or a SiO2 film (paragraph [0031], rows 4-6).
Regarding claim 7, the combination of Singh and Eto teaches the semiconductor assembly of claims 1 and 6 as set forth in the obviousness rejection. Singh further teaches the semiconductor assembly of claim 6, wherein the first dummy metal line is disposed on and in contact with the passivation layer (Fig.3F, element #356b, is disposed on and in contact with element #340).
Regarding claim 8, the combination of Singh and Eto teaches the semiconductor assembly of claim 1 as set forth in the obviousness rejection. Singh further teaches the semiconductor assembly of claim 1, wherein a first portion of the protection layer covers the first dummy metal line and a second portion of the protection layer covers the passivation layer (Fig.3F, different portions of element #342 cover elements #356 and #340)
Regarding claim 9, the combination of Singh and Eto teaches the semiconductor assembly of claim 1 as set forth in the obviousness rejection. Eto further teaches wherein the inclined side surface of the protection layer is aligned with the first side surface of the seal ring (Fig.1, the inclined side surface of the protection layer, the right side surface of element #212, is aligned with first side surface of the seal ring, right side surface of element #213). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Eto and disclose wherein the inclined side surface of the protection layer is aligned with the first side surface of the seal ring. Having side surfaces of the seal ring and the protection layer aligned mitigates the presence of sharp surface points/corners that may chip away during wafer dicing and can result in reliability problems during the following packaging steps.
Regarding claim 10, the combination of Singh and Eto teaches the semiconductor assembly of claim 1 as set forth in the obviousness rejection. Singh further teaches the semiconductor assembly of claim 1, wherein a bottom of the protection layer is in contact with a portion of the passivation layer (Fig.3F, a bottom of element #342 is in contact with a portion of element #40)
Regarding claim 11, the combination of Singh and Eto teaches the semiconductor assembly of claim 1 as set forth in the obviousness rejection. Singh further teaches the semiconductor assembly of claim 1, wherein the protection layer surrounds the first dummy metal line and is in contact with the second side surface of the first dummy metal line (Fig.3F, element #342 surrounds element #356 and is in contact with the left side of element #356).
Regarding claim 12, the combination of Singh and Eto teaches the semiconductor assembly of claims 1 and 3 as set forth in the obviousness rejection. Singh further teaches the semiconductor assembly of claim 3, wherein the RDL structure is not electrically connected to the first dummy metal line (Fig1, dummy line element #156, which is equivalent to element #356 of Fig.3F is not connected ty to the RDL).
Regarding claim 13, the combination of Singh and Eto teaches the semiconductor assembly of claim 1 as set forth in the obviousness rejection. Singh further teaches the semiconductor assembly of claim 1, wherein a material of the seal ring includes an insulating material (Fig.3F, element #360, which is equivalent with element #160, includes polyimide, paragraph [0021], rows 13-15).
Regarding claim 14, Singh teaches a semiconductor assembly comprising: a semiconductor die (Fig.3F, element #310 is part of the circuit region of a die, paragraph [0030], row 6; full circuit region is shown as element #110 of Fig.1, and is formed by all the elements in that region as shown in Fig.1, from element #162 down to element #120, including them) and a seal ring disposed adjacent to the semiconductor die (Fig.3F, formed by the components of regions #316 and #314, located above element #340, elements #356, #354a, #354b, #342, #360 and #362), wherein the seal ring comprises: a first side surface (Fig.3F, left side surface of element #362) inclined from a top surface of the seal ring toward a bottom surface of the seal ring (Fig.3F, left side surface of element #362 is inclined from its top surface toward the bottom surface of the seal ring, formed by the bottom surface of elements #356, #354b and #354a and bottom surface of element #342 in the regions #314 and #316); and a dummy metal line disposed in the seal ring (Fig.3F, element #356 is equivalent to element #156 of Fig.1, which is a dummy metal line, paragraph [0015], rows 22-23), a redistribution layer (RDL) structure disposed below the seal ring, wherein the RDL structure is not electrically connected to the dummy metal line (Fig.1, elements #124, #126 and #128 located under element #156, which is equivalent to element #356 of Fig.3F), and a passivation layer disposed between the seal ring and the RDL structure (Fig.3F, element #340), and a protection layer disposed on and in contact with the passivation layer and the dummy metal line and including an inclined side surface (Fig.3F, element #342, is in contact with passivation layer #340 and dummy metal line #356, and has an inclined surface on left side surface of element #356), wherein a top surface of the seal ring is substantially continuous with a top surface of the semiconductor die (Fig.3F, the top surface of element #362 above region #314 and top surface of element #362 above the semiconductor die, element #110, is in the same horizontal plane), and the first side surface of the seal ring is inclined from the top surface of the seal ring toward an upper end of the inclined side surface of the protection layer (Fig.3F, left side surface of element #362 is inclined towards the upper end of the inclined side surface of the protection layer, element #340, located on left side surface of element #356).
Singh does not teach wherein the first side surface of the seal ring is continuous with the inclined side surface of the protection layer, and the inclined side surface of the protection layer is continuous with an outermost side surface of the passivation layer. Eto teaches the first side surface of the seal ring is continuous with the inclined side surface of the protection layer, and the inclined side surface of the protection layer is continuous with an outermost side surface of the passivation layer (Fig.1, first side surface of the seal ring, right side surface of element #213, is continuous with the inclined side surface of the protection layer, the right side surface of element #212, which is continuous with an outermost side surface of the passivation layer, the right side surface of the passivation layer formed by elements #209 and #208). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention to incorporate the teachings of Eto and disclose the first side surface of the seal ring is substantially continuous with the inclined side surface of the protection layer, and the inclined side surface of the protection layer is substantially continuous with an outermost side surface of the passivation layer. Having side surfaces of the seal ring, the passivation layer and the protection layer substantially continuous mitigates the presence of sharp surface points/corners that may chip away during wafer dicing and can result in reliability problems during the following packaging steps. Furthermore, having exposed and continuous outermost side surfaces of the passivation and protection layers eliminates the need for dicing these layers, which reduces the thickness of the die in the dicing region and thus reduces the stress during dicing the remainder of the die layers.
Regarding claim 15, the combination of Singh and Eto teaches the semiconductor assembly of claim 14 as set forth in the obviousness rejection. Singh teaches the semiconductor assembly of claim 14 wherein a portion of the protection layer is in contact with a top surface of the dummy metal line (Fig.3F, a portion of element #342, is in contact with the top surface of the dummy metal line, element #356).
Regarding claim 16, the combination of Singh and Eto teaches the semiconductor assembly of claims 14 and 15 as set forth in the obviousness rejection. Singh teaches the semiconductor assembly of claim 15, wherein the top surface and a second side surface of the dummy metal line are respectively covered by the seal ring (Fig.3F, the top surface and the right side surface of the dummy metal line #356 are covered by element #362).
Regarding claim 17, the combination of Singh and Eto teaches the semiconductor assembly of claim 14 as set forth in the obviousness rejection. Singh further teaches he semiconductor assembly of claim 14, wherein the passivation layer is disposed on the bottom surface of the seal ring (Fig.3F, element #340 is disposed at the bottom surface of the seal ring, bottom surface as defined in the rejection of claim 14).
Regarding claim 18, the combination of Singh and Eto teaches the semiconductor assembly of claim 14 as set forth in the obviousness rejection. Eto further teaches wherein the inclined side surface of the protection layer is aligned with the first side surface of the seal ring (Fig.1, the inclined side surface of the protection layer, the right side surface of element #212, is aligned with first side surface of the seal ring, right side surface of element #213). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Eto and disclose wherein the inclined side surface of the protection layer is aligned with the first side surface of the seal ring. Having side surfaces of the seal ring and the protection layer aligned mitigates the presence of sharp surface points/corners that may chip away during wafer dicing and can result in reliability problems during the following packaging steps.
Regarding claim 19, the combination of Singh and Eto teaches the semiconductor assembly of claim 14, as set forth in the obviousness rejection. Singh further teaches the semiconductor assembly of claim 14, wherein a bottom of the protection layer is in contact with a portion of the passivation layer (Fig.3F, a bottom portion of element #342, is in contact with the passivation layer, element #340).
Regarding claim 20, Singh teaches a semiconductor assembly comprising: a semiconductor die (Fig.3F, element #310 is part of the circuit region of a die, paragraph [0030], row 6; full circuit region is shown as element #110 of Fig.1, and is formed by all the elements in that region as shown in Fig.1, from element #162 down to element #120, including them) and a seal ring disposed adjacent to the semiconductor die (Fig.3F, formed by the components of regions #316 and #314, located above element #340, elements #356, #354a, #354b, #342, #360 and #362), wherein the seal ring comprises: a first side surface (Fig.3F, left side surface of element #362) inclined from a top surface of the seal ring toward a bottom surface of the seal ring (Fig.3F, left side surface of element #362 is inclined from its top surface toward the bottom surface of the seal ring formed by the bottom surface of elements #356, #354a and #354b and the bottom surface of element #342 in the regions #316 and #314), wherein a lateral width of the bottom surface of the seal ring (Fig.3F, distance between the right side of element #314 and left side of element #316 along horizontal direction) is larger than a lateral width of the top surface of the seal ring (Fig.3F, the distance between a point of the top surface of element #362 located in the same vertical plane as the right side of element #314 and the furthest left point of the top surface of element #362, along horizontal direction); a redistribution layer (RDL) structure disposed below the seal ring (Fig.1, elements #124, #126 and #128 located under element #156, which is equivalent to element #356 of Fig.3F), wherein the seal ring includes a dummy metal line (Fig.3F, element #356 is equivalent to element #156 of Fig.1, which is a dummy metal line, paragraph [0015], rows 22-23); and a passivation layer disposed between the seal ring and the RDL structure (Fig.3F, element #340), and a protection layer disposed on the passivation layer and the dummy metal line and including an inclined side surface (Fig.3F, element #342, has an inclined surface on left side surface of element #356), wherein the RDL structure is not electrically connected to the dummy metal line (Fig.1, elements #124, #126 and #128 located under element #156 are not electrically connected to element #156, element #156 is equivalent to element #356 in Fig.3F) wherein a bottom surface of the dummy metal line is in contact with a top surface of the passivation layer(Fig.3F, bottom surface of element #356 is in contact with the top surface of element #340), and the first side surface of the seal ring is inclined from the top surface of the seal ring toward an upper end of the inclined side surface of the protection layer (Fig.3F, left side surface of element #362 is inclined towards the upper end of the inclined side surface of the protection layer, element #340 located on left side surface of element #356).
Singh does not teach wherein the first side surface of the seal ring is substantially continuous with the inclined side surface of the protection layer, and the inclined side surface of the protection layer is substantially continuous with an outermost side surface of the passivation layer. Eto teaches the first side surface of the seal ring is substantially continuous with the inclined side surface of the protection layer, and the inclined side surface of the protection layer is substantially continuous with an outermost side surface of the passivation layer (Fig.1, first side surface of the seal ring, right side surface of element #213, is continuous with the inclined side surface of the protection layer, the right side surface of element #212, which is continuous with an outermost side surface of the passivation layer, the right side surface of the passivation layer formed by elements #209 and #208). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention to incorporate the teachings of Eto and disclose the first side surface of the seal ring is substantially continuous with the inclined side surface of the protection layer, and the inclined side surface of the protection layer is substantially continuous with an outermost side surface of the passivation layer. Having side surfaces of the seal ring, the passivation layer and the protection layer substantially continuous mitigates the presence of sharp surface points/corners that may chip away during wafer dicing and can result in reliability problems during the following packaging steps. Furthermore, having exposed and continuous outermost side surfaces of the passivation and protection layers eliminates the need for dicing these layers, which reduces the thickness of the die in the dicing region and thus reduces the stress during dicing the remainder of the die layers.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Singh, in view of Eto and in view of Tomita, (United States Patent Application Publication Number US 2015/0091161 A1) hereinafter referenced as Tomita.
Regarding claim 5, the combination of Singh and Eto teaches the semiconductor assembly of claims 1 and 4 as set forth in the obviousness rejection. Eto teaches a maximum distance between the second side surface of the first dummy metal line and the first side surface of the seal ring is equal or greater than the sum of the thickness of the protection layer, element #212 and the thickness of the seal layer, element #213 (Fig.1, right sides surfaces of element #211c and #213). We note that the maximum distance between the two surfaces can be in any direction, for instance, from the lower right corner of the metal line, element #211c, to the highest point of the right side surface of element #213. The combination of Singh and Eto does not teach the semiconductor assembly of claim 4, wherein a maximum distance between the second side surface of the first dummy metal line and the first side surface of the seal ring is from 5 μm to 30 μm. Tomita teaches the thickness of the protection layer is 1um and the thickness of the seal ring layer is 5um (Fig.20, protection layer is element #PL, and the seal ring layer is element #PO1, paragraph [0055], rows 1-7), therefore the sum of the two thickness is 6um. As above the maximum thickness is from the lower right corner of the metal line, element #TCL (Fig.20, TCL is 1um thick, paragraph [0055], rows 1-2), to the top point of the right side surface of element #PO1. Thus, Tomita teaches the wherein a maximum distance between the second side surface of the first dummy metal line and the first side surface of the seal ring is greater than 7um. The claimed range, from 5um to 30um overlaps or lies inside the range disclosed by Tomita and therefore a prima facie case of obviousness exists (MPEP 2144.05). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention to incorporate the teachings of Eto and Tomita and disclose wherein a maximum distance between the second side surface of the first dummy metal line and the first side surface of the seal ring is from 5 μm to 30 μm. This distance separates the metal line from the outside environment, and the materials between the metal line and the outside environment, having the thickness in this range, offer protection to the metal line from environmental factors, thus preventing degradation.
Response to Arguments
Applicant’s arguments filed on 03/04/2026 have been fully considered but they
are not persuasive. Applicant’s arguments with respect to the claims have been considered but are moot because the new ground of rejection does not rely on any reference as applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/CRISTIAN A TIVARUS/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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