DETAILED ACTION
This Office action is in response to the Request for Continued Examination (RCE) and the Amendment filed on 03 March 2026. Claims 1-15 and 21-25 are pending. Claims 16-20 have been cancelled.
This application is a continuation of application Serial No. 16/851,079, filed on 16 April 2020, now US Patent 11,398,559; which is a continuation of application Serial No. 15/599,045, filed on 18 May 2017, now US Patent 10,658,486.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I, on which claims 1-15 and 21-25 are readable, in the reply filed on 21 May 2025 is acknowledged.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 03 March 2026 has been entered.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1, 3, 4, 8-11 13-15, 21, and 23-25 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 3, 5, 16, 19, and 20 of U.S. Patent No. 10,658,486. Although the claims at issue are not identical, they are not patentably distinct from each other because the pending claims and the patented claims are both drawn to a method comprising forming a gate metal stack having an opening or recess, firming a spacer layer, forming a metal fill layer, and planarizing the metal fill layer, the spacer layer, and the gate metal stack.
In light of the amendments made to claims 1, 9, and 21, the rejection of claims 1-7, 9-14, 21-23, and 25 on the ground of nonstatutory double patenting as being unpatentable over claims 1-6 of U.S. Patent No. 11,398,559 has been withdrawn.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 3-6 are rejected under 35 U.S.C. 103 as being unpatentable over Son, 5,750,430, in view Min et al., US 2009/0173994, further in view of Kubota, US 5,869,382, all of record.
With respect to independent claim 1, Son discloses a method, shown in Figs. 2A-2D, comprising:
forming a dielectric layer 12 having a first opening on a substrate 11, see Fig. 2A and column 2, lines 66-67, bridging column 3 to line 5;
forming a gate stack 13/14 in the first opening and on the dielectric layer, wherein the gate stack forms a second opening in the first opening, see Figs. 2A and 2B and column 3, lines 6-9;
forming a spacer layer 15 on top and sidewall surfaces of the gate stack, see Fig. 2C and column 3, lines 13-18;
etching the spacer layer 15 to form spacers on the sidewall surfaces of the gate stack 13/14, wherein the spacers form a third opening to expose the top surface of the gate metal stack 13/14 in the second opening, see Fig. 2C and column 3, lines 13-18; and
depositing a fill layer 14’ on the spacers 15 and the gate stack 13/14 to fill the third opening, wherein the fill layer 14’ is in contact with the gate stack 13/14 in the third opening, see Fig. 2D and column 3, lines 28-32.
Although Son discloses a gate stack 13/14 and a fill layer 14’, Son lacks anticipation of a gate metal stack and a metal fill layer. However, in the same field of endeavor, Min et al. discloses a metal gate electrode comprising a gate metal stack 145/152, see paragraphs [0024] and [0026]. Min et al. disclose that using a metal 140 having a higher work function than polysilicon along with polysilicon layer 150 increases the drive current of a transistor, see paragraphs [0010] and [0024]. In light of the disclosure of Min et al., it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include a metal gate layer beneath polysilicon layer 14 in the known method of Son in order to increase the drive current of Son’s transistor.
Furthermore, Min et al. disclose that fill layer 154 can be polysilicon or a metal such as Ti, TiN, W, WN, Ta, TaN, Co, C, Ru, or Rb, see paragraph [0026]. Therefore, Min et al. teach the functional equivalence of polysilicon and metals as a fill layer. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that a metal could have been used as the fill layer 14’ in the known method of Son.
Independent claim 1 has been amended to require removing a portion of the metal fill layer, a portion of the spacers, and a portion of the gate metal stack to planarize top surfaces of the metal fill layer, the spacers, and the gate metal stack. Son does not teach planarizing the structure shown in Fig. 2D. However, in a similar method, Kubota discloses a method which comprises depositing a conductive layer 18, forming spacers 21, depositing a fill layer 22 on the spacers 21, as shown in Fig. 6c, and planarizing the conductive layer 18, the spacers 21, and the fill layer 22, as shown in Fig. 7a, by removing a portion of the metal fill layer 22, a portion of the spacers 21, and a portion of the conductive layer 18, see column 3, lines 66-67, bridging column 4 to line 5. Kubota disclose performing the planarizing step is performed prior to removing the spacers 21, as shown in Figs. 7a and 7b. In light of this teaching of Kubota et al., it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that a portion of the metal fill layer 14’, a portion of the spacers 15, and a portion of the gate metal stack 13/14 could be removed to planarize top surfaces of the metal fill layer 14’, the spacers 15, and the gate metal stack 13/14 shown in Fig. 2D of Son, thereby facilitating the removal of spacers 15 in the known method of Son.
With respect to claim 3, the combination of Son and Min et al. would result in forming the metal gate stack 145/152 by depositing a capping layer 13 or 130 in the first opening (as shown in Fig. 2A of Son and in Fig. 3 of Min et al.); and depositing a work-function metal stack 145/152 on the capping layer (as shown in Fig. 8B of Min et al., see paragraph [0027]).
With respect to claim 4, in the method of Son, etching the spacer layer 15 to form the spacers 15 comprises: removing the spacer layer 15 from a top surface of the gat metal layer 14; and removing the spacer layer 15 from a bottom of the second opening, as shown in Fig. 2C of Son.
With respect to claim 5, in the method of Son, forming the spacer layer 15 comprises forming dielectric material of oxide to fill the second opening and anisotropically etching the oxide layer to form sidewall spacers, see Fig. 2C and column 3, lines 13-18. However, Son fails to teach that the dielectric material comprises silicon nitride (Si3N4), silicon oxynitride (SiON), carbon-doped silicon nitride (SiCN), or silicon oxycarbide (SiOxCy). In the same field of endeavor, Min et al. disclose forming sidewall spacers 135 of oxide or nitride (material 132), see Figs. 8C and 8D and paragraph [0032]. Admittedly, Min et al. do not expressly disclose the dielectric material 132 of the spacer layer is silicon nitride (Si3N4). However, in paragraph [0034], Min et al. disclose that capping insulating layer material 180 (shown in Fig. 9) can be an oxide, nitride, SiON, SixNy, or SiO2. In light of this teaching of equivalence, it would have been obvious to the skilled artisan that the spacer layer could have been an oxide, nitride, SiON, SixNy, or SiO2, since these materials are taught to be functionally equivalent insulating materials.
With respect to claim 6, the combination of Son and Min et al. as set forth above in the rejection of dependent claim 5 would make it obvious to use silicon nitride (Si3N4) as the material for the spacers 15 in the known method of Son. Hence, the combination of Son and Min et al. would result in forming the spacer layer comprising depositing a silicon-based layer comprising nitrogen to fill the second opening.
Claims 9-15 are rejected under 35 U.S.C. 103 as being unpatentable over Son, 5,750,430, in view Min et al., US 2009/0173994, both of record, further in view of Curello et al., EP 1 205 980, newly cited.
With respect to independent claim 9, Son discloses a method, shown in Figs. 2A-2D, comprising:
forming a pair of spacers 12 on a substrate 11, wherein the pair of spacers 12 are opposite to each other, see Fig. 2A and column 2, lines 66-67, bridging column 3 to line 5;
forming a dielectric layer 13 on the substrate 11 and the pair of spacers 12, as shown in Fig. 2A, see column 3, lines 6-9;
forming a gate stack 14 on the dielectric layer 13 and over the pair of spacers, wherein the gate stack 14 forms a first recess, see Fig. 2B and column 3, lines 9-12;
forming a spacer layer 15 on side surfaces of the gate stack 14 in the first recess, wherein the spacer layer 15 forms a second recess that exposes a bottom surface of the first recess, see Fig. 2C and column 3, lines 13-18; and
filling the second recess with polysilicon 14’, wherein the spacer layer 15 is between the polysilicon 14’ and the side surfaces of the gate stack 14, see Fig. 2D and column 3, lines 28-32.
Although Son discloses a gate stack 13/14 and polysilicon layer 14’, Son lacks anticipation of a gate metal stack and filling the second recess with a metal. However, in the same field of endeavor, Min et al. discloses a metal gate electrode comprising a gate metal stack 145/152, see paragraphs [0024] and [0026]. Min et al. disclose that using a metal 140 having a higher work function than polysilicon along with polysilicon layer 150 increases the drive current of a transistor, see paragraphs [0010] and [0024]. In light of the disclosure of Min et al., it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include a metal gate layer beneath polysilicon layer 14 in the known method of Son in order to increase the drive current of Son’s transistor.
Furthermore, Min et al. disclose that fill layer 154 can be polysilicon or a metal such as Ti, TiN, W, WN, Ta, TaN, Co, C, Ru, or Rb, see paragraph [0026]. Therefore, Min et al. teach the functional equivalence of polysilicon and metals as a fill layer. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the second recess could have been filled with a metal in the known method of Son, since Min et al. teach the functional equivalence of polysilicon (layer 14’) and metal as a fill layer in forming a gate electrode.
Independent claim 9 has been amended to require depositing a barrier layer on the spacer layer and the gate metal stack. Son lacks anticipation of depositing a barrier layer. However, in the same field of endeavor, Curello et al. disclose a method of fabricating a gate electrode in which a barrier layer 40 is deposited on a spacer layer 20 prior to filling the second recess with a metal 50, see Figs. 1d-1e of Curello et al. Barrier layers are known to prevent diffusion between conductive materials, thereby improving device performance and reliability. In light of the disclosure of Curello et al., it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to deposit a barrier layer on the spacer layer 15 and the gate metal stack 14 in the known method of Son in order to prevent diffusion between the gate metal stack 14 and the fill metal 14’.
With respect to claim 10, in the method of Son, forming the spacer layer comprises: blanket depositing a dielectric material 15 (oxide) in the first recess and on the gate metal stack 14; and etching the deposited dielectric material with an anisotropic etch, see Fig. 2C and column 3, lines 13-18.
With respect to claim 11, in the method of Son, etching the deposited dielectric material 15 comprises removing the deposited dielectric material 15 on horizontal surfaces of the gate metal stack 14, as shown in Fig. 2C.
With respect to claim 12, Son discloses the dielectric material 15 is oxide. However, Son fails to teach that forming the spacer layer comprises filling the first recess with a silicon nitride-based dielectric material. In the same field of endeavor, Min et al. disclose forming sidewall spacers 135 of oxide or nitride (material 132), see Figs. 8C and 8D and paragraph [0032]. Admittedly, Min et al. do not expressly disclose the dielectric material 132 of the spacer layer is silicon nitride (Si3N4). However, in paragraph [0034], Min et al. disclose that capping insulating layer material 180 (shown in Fig. 9) can be an oxide, nitride, SiON, SixNy, or SiO2. In light of this teaching of the equivalence of these dielectric materials, it would have been obvious to the skilled artisan that forming the spacer layer could comprise filling the first recess with a silicon nitride-based dielectric material, since Min et al. teach that silicon nitride and oxide are functionally equivalent insulating materials.
With respect to claim 13, Min et al. disclose that the dielectric layer 130 (equivalent to dielectric layer 13 in the known method of Son) can be formed on the substrate and on the top surface and sidewall surface of the pair of spacers 120, as shown in Figs. 8A and 8B or Min et al. Therefore, in light of the teaching of Min et al., it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the dielectric layer 13 in the known method of Son could have been formed on the substrate 11 as well as on the top surface and sidewall surface of the pair of spacers 12. Hence, this combination of Son and Min et al. would result in forming the gate metal stack 14 by conformally depositing the gate metal stack 14 on bottom and sidewall surfaces of the dielectric layer 13 in the known method of Son.
With respect to claim 14, the combination of Son and Min et al. results in filling the second recess with the metal or polysilicon 14’ by depositing the metal or polysilicon 14’ on the spacer layer 15 and the gate metal stack 14, as shown in Fig. 2D of Son.
With respect to claim 15, in the known method of Son, the top surfaces of the dielectric layer 13, the gate metal stack 14, the spacer layer 15, and the filled metal 14’ are subsequently planarized by the removal of spacers 15 and the forming of oxide film 16, as shown in Fig. 2F.
Claims 21-25 are rejected under 35 U.S.C. 103 as being unpatentable over Son, 5,750,430, newly cited, in view of Min et al., US 2009/0173994, further in view of Matsui, US 2002/0037615, newly cited.
With respect to independent claim 21, Son discloses a method, shown in Figs. 2A-2D, comprising:
depositing a dielectric layer 13 on a dielectric layer 12 having an opening see Fig. 2A and column 2, lines 66-67, bridging column 3 to line 5;
depositing a gate stack 14 on the dielectric layer 13 to form a first recess in the opening, see Fig. 2B and column 3, lines 9-12;
depositing a spacer layer 15 on top and sidewall surfaces of the gate stack 14 to fill the first recess, see Fig. 2C and column 3, lines 13-18,
removing a first portion of the spacer layer 15 on the top surfaces of the gate stack 14 to form a second recess in the first recess, wherein a second portion 15 of the spacer layer 15 remains on the sidewall inner side surfaces of the gate stack 14 in the first recess, see Fig. 2C and column 3, lines 13-18; and
filling the second recess with layer 14’, see Fig. 2D and column 3, lines 28-32.
Although Son discloses a gate stack 13/14 and a fill layer 14’, Son lacks anticipation of a gate metal stack and a metal fill layer. However, in the same field of endeavor, Min et al. discloses a metal gate electrode comprising a gate metal stack 145/152, see paragraphs [0024] and [0026]. Min et al. disclose that using a metal 140 having a higher work function than polysilicon along with polysilicon layer 150 increases the drive current of a transistor, see paragraphs [0010] and [0024]. In light of the disclosure of Min et al., it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include a metal gate layer beneath polysilicon layer 14 in the known method of Son in order to increase the drive current of Son’s transistor.
Furthermore, Min et al. disclose that fill layer 154 can be polysilicon or a metal such as Ti, TiN, W, WN, Ta, TaN, Co, C, Ru, or Rb, see paragraph [0026]. Therefore, Min et al. teach the functional equivalence of polysilicon and metals as a fill layer. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that a metal could have been used as the fill layer 14’ in the known method of Son.
Although Son teaches depositing a gate dielectric layer 13 comprising oxide (see column 3, lines 6-9), Son lacks anticipation of depositing a high-k dielectric layer on sidewall and top surfaces of a dielectric layer having an opening. In the same field of endeavor, Matsuo disclose a method of fabricating a transistor having a high-k gate dielectric 113, wherein the high-k dielectric 113 is deposited on sidewall and top surfaces of a dielectric layer 111, as shown in Figs. 1A and 1B of Matsuo. High-k gate dielectrics offer superior performance over oxide by enabling increased gate capacitance without requiring an ultra-thin layer that leads to high tunneling leakage. Therefore, in light of the known advantages of high-k gate dielectrics over oxide, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute a high-k dielectric layer for the oxide layer in the known method of Son and to deposit the high-k dielectric layer on sidewall and top surfaces of the dielectric layer 12 having an opening in the known method of Son, thereby fabricating a device with improved performance.
Independent claim 21 has been amended to require filling the second recess with layer 14’, wherein topmost surfaces of the fill layer 14’, the second portion of the spacer layer 15, the gate stack 14 and the high-k dielectric layer are substantially aligned. Substitution of the high-k dielectric layer of Matsuo for the oxide layer 13 of Son would result in topmost surfaces of the fill layer 14’, the second portion of the spacer layer 15, the gate stack 14 and the high-k dielectric layer being substantially aligned in Fig. 2D of Son..
With respect to claim 22, Son discloses the dielectric material 15 is oxide. However, Son fails to teach that forming the spacer layer comprises filling the first recess with a silicon nitride-based dielectric material. In the same field of endeavor, Min et al. disclose forming sidewall spacers 135 of oxide or nitride (material 132), see Figs. 8C and 8D and paragraph [0032]. Admittedly, Min et al. do not expressly disclose the dielectric material 132 of the spacer layer is silicon nitride (Si3N4). However, in paragraph [0034], Min et al. disclose that capping insulating layer material 180 (shown in Fig. 9) can be an oxide, nitride, SiON, SixNy, or SiO2. In light of this teaching of the equivalence of these dielectric materials, it would have been obvious to the skilled artisan that forming the spacer layer could comprise filling the first recess with a silicon nitride-based dielectric material, since Min et al. teach that silicon nitride and oxide are functionally equivalent insulating materials.
With respect to claim 23, Min et al. disclose that the dielectric layer 130 (equivalent to dielectric layer 13 in the known method of Son) can be formed on the substrate and on the top surface and sidewall surface of the pair of spacers 120, as shown in Figs. 8A and 8B or Min et al. Therefore, in light of the teaching of Min et al., it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the dielectric layer 13 in the known method of Son could have been formed on the substrate 11 as well as on the top surface and sidewall surface of the pair of spacers 12. In light of the teaching of Xie et al., it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the dielectric layer 13 in the known method of Son could have been a high-k dielectric. Hence, this combination of Son, Min et al., and Xie et al. would result in forming the gate metal stack 14 by conformally depositing the gate metal stack 14 on bottom and sidewall surfaces of the high-k dielectric layer 13 in the known method of Son.
With respect to claim 24, in the known method of Son, removing the first portion of the spacer layer 15 comprises etching the spacer layer 15 with an anisotropic etch, see Fig. 2C and column 3, lines 13-18
With respect to claim 25, in the method of Son, removing the first portion of the spacer layer 15 comprises removing the spacer layer 15 from horizontal surfaces faster than vertical surfaces in accordance with anisotropic etching, see Fig. 2C and column 3, lines 13-18.
Allowable Subject Matter
Claims 2 and 7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: None of the references of record teach or suggest forming an interfacial layer on a bottom surface of the first opening; and depositing a high-k dielectric in the first opening, wherein the high-k dielectric is in contact with the interfacial layer and in contact with sidewall surfaces of the first opening, as required in dependent claim 2.
None of the references of record teach or suggest forming the spacer layer comprises depositing a silicon-based layer comprising carbon to fill the second opening, as required in dependent claim 7.
Response to Arguments
Applicant's arguments filed 03 March 2026 have been fully considered but they are not persuasive. Independent claims 1, 9, and 21 have been rejected in this Office action over prior art of record and newly-cited references.
Applicant has requested that the Examiner reconsider the double patenting rejections. Since the claims of US Patent 10,658,486 include a planarizing step, the rejection of claims 1, 3, 4, 8-11 13-15, 21, and 23-25 on the ground of nonstatutory double patenting as being unpatentable over claims 1, 3, 5, 16, 19, and 20 of U.S. Patent No. 10,658,486 has been maintained. However, the rejection of claims 1-7, 9-14, 21-23, and 25 on the ground of nonstatutory double patenting as being unpatentable over claims 1-6 of U.S. Patent No. 11,398,559 has been withdrawn..
Conclusion
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MARY A. WILCZEWSKI
Primary Examiner
Art Unit 2898
/MARY A WILCZEWSKI/Primary Examiner, Art Unit 2898
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