DETAILED ACTION
This Office action is in response to the Amendment filed on 05 August 2026. Claims 1-15 and 21-25 are pending. Claims 16-20 have been cancelled.
This application is a continuation of application Serial No. 16/851,079, filed on 16 April 2020, now US Patent 11,398,559; which is a continuation of application Serial No. 15/599,045, filed on 18 May 2017, now US Patent 10,658,486.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I, on which claims 1-15 and 21-25 are readable, in the reply filed on 21 May 2025 is acknowledged.
Double Patenting
In light of the amendments made to claims 1, 9, and 21, the rejection of claims 1, 3, 4, 8-11 13-15, 21, and 23-25 on the ground of nonstatutory double patenting as being unpatentable over claims 1, 3, 5, 16, 19, and 20 of U.S. Patent No. 10,658,486 has been withdrawn.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 21, 22, 24, and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Guha et al., US 2006/0091432, in view of Wang et al., US 2009/0212332, both of record.
With respect to claim 21, Guha et al. disclose a method, comprising:
depositing a high-k dielectric layer 15 on sidewall and top surfaces of a dielectric layer 11 having an opening, wherein sidewall surfaces of the high-k dielectric layer 15 and the dielectric layer 11 are separated by a spacer 7, as shown in Fig. 8, see paragraph [0038];
depositing a spacer layer 16 to fill the first recess, as shown in Fig. 8, see paragraph [0040]; “depositing a spacer material, e.g. an oxide or other suitable material, in the cavity 13 and etching the deposited material anisotropically, e.g. by RIE, such that the portion of the dielectric layer 15 above channel 9 is exposed, leaving the gate spacer structure 16 on the sidewalls of the cavity 13”;
removing a first portion of the spacer layer 16 to form a second recess in the first recess, wherein a second portion of the spacer layer 16 remains on the sidewall surfaces in the first recess, as shown in Fig. 8, see paragraph [0040]: “depositing a spacer material, e.g. an oxide or other suitable material, in the cavity 13 and etching the deposited material anisotropically, e.g. by RIE, such that the portion of the dielectric layer 15 above channel 9 is exposed, leaving the gate spacer structure 16 on the sidewalls of the cavity 13”; and
filling the second recess with a metal fill layer 17, as shown in Fig. 9, see paragraph [0041], wherein topmost surfaces of the metal fill layer 17, the second portion of the spacer layer 16, and the high-k dielectric layer 15 are substantially aligned, as shown in Figs. 9 and 13.
However, Guha et al. fail to disclose depositing a gate metal stack on the high-k dielectric layer to form a first recess in the opening. However, in the same field of endeavor, Wang et al. disclose a method of fabricating a transistor having reduced overlap capacitance between a gate electrode and source and drain extension regions, the method comprising: depositing a gate metal stack 22 on a dielectric layer 20 to form a first recess in an opening, see Fig. 12 and paragraph [0094]; depositing a spacer layer 70 on top and sidewall surfaces of the gate metal stack 22 to fill the first recess, as shown in Fig. 13 (paragraph [0118}: “Referring to FIG. 13, an inner gate spacer 70 is formed by a substantially conformal deposition of a dielectric material, followed by a reactive ion etch.“); and removing a first portion of the spacer layer 70 on the top surfaces of the gate metal stack 22 to form a second recess in the first recess, wherein a second portion of the spacer layer 70 remains on the sidewall surfaces of the gate metal stack 22 (as shown in annotated Fig. 14 below) in the first recess, as shown in Fig. 13 (paragraph [0118]: Referring to FIG. 13, an inner gate spacer 70 is formed by a substantially conformal deposition of a dielectric material, followed by a reactive ion etch.”). Wang et al. also show in Fig. 14 that topmost surfaces of the metal fill layer 86, the second portion of the spacer layer 70, and the the gate metal stack 22 are substantially aligned. Since gate metal stack 22 deposited in the method of Wang et al. determines the threshold voltage of the transistor (see paragraph [0119]), it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to deposit a gate metal stack 22 on the high-k dielectric layer to form a first recess in the opening in the known method of Guha et al. Deposition of the gate metal stack 22 in the known method of Guha et al. would result in topmost surfaces of the metal fill layer 17, the second portion of the spacer layer 16, the gate metal stack 22, and the high-k dielectric layer 15 being substantially aligned
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With respect to claim 22, in the methods of Guha et al. and Wang et al., depositing the spacer layer 16 or 70, respectively, comprises filling the first recess with a dielectric material, see paragraph [0040] of Guha et al. and paragraph [0118] of Wang et al. However, neither Guha et al. nor Wang et al. disclose the spacer layer comprises a silicon nitride-based dielectric material. Rather, both Guha et al. and Wang et al. disclose silicon oxide as the spacer material. However, silicon nitride is a well known dielectric material used in the fabrication of transistors. Since both Guha et al. and Wang et al. disclose using a dielectric material as the spacer layer, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use a silicon nitride-based dielectric material as the spacer layer in the known method of Guha et al. in view of Wang et al.
With respect to claim 24, in the method of Guha et al., removing the first portion of the spacer layer 16 comprises etching the spacer layer 16 with an anisotropic etch, see paragraph [0040].
With respect to claim 25, in the method of Guha et al., removing the first portion of the spacer layer comprises removing the spacer layer 16 from horizontal surfaces faster than vertical surfaces, see paragraph [0040].
Allowable Subject Matter
Claims 1-15 are allowable over the prior art of record.
The following is a statement of reasons for the indication of allowable subject matter: None of the references of record teach or suggest forming a spacer layer comprising silicon and carbon on top and sidewall surfaces of the gate metal stack to fill the second opening, in the method of independent claim 1.
None of the references of record teach or suggest a method comprising: forming a pair of spacers on a substrate, wherein the pair of spacers are opposite to each other and surrounded by an inter-layer dielectric (ILD) layer; and forming a dielectric layer on the substrate, on top surfaces of the ILD layer, and on sidewall and top surfaces of the pair of spacers, in the method of independent claim 9.
Claim 23 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Guha et al. and Wang et al. are applied as above. However, neither Guha et al. nor Wang et al. disclose that depositing the gate metal stack comprises conformally depositing the gate metal stack on top and sidewall surfaces of the high-k dielectric layer.
Response to Arguments
Applicant’s arguments with respect to claims 21-25 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The additionally cited references disclose various of methods of fabricating gates using dielectric spacers.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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MARY A. WILCZEWSKI
Primary Examiner
Art Unit 2898
/MARY A WILCZEWSKI/Primary Examiner, Art Unit 2898
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