DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hsu et al (US Pub No. 20190058050), in view of Balsenu et al (US Pub No. 20080020591).
With respect to claim 1, Hsu et al discloses a semiconductor region; a gate stack (46,48,50,52,Fig.8) over the semiconductor region (12); a first gate spacer on a sidewall of the gate stack (30); a second gate spacer overlapping at least a portion of the first gate spacer (32); and a contact etch stop layer (36) contacting sidewalls of both of the first gate spacer and the second gate spacer (Fig.8). Hsu et al discloses that the first and the second spacer can be made from silicon oxide and silicon nitride (Para 13), wherein the first gate spacer comprises a first inner sidewall facing the gate stack (the vertical portion of the 40); however, Hsu et al does not explicitly disclose wherein the first gate spacer and the second gate spacer are formed of different materials. On the other hand, it would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify Hsu et al such that the first spacer is made from silicon nitride and the second spacer is made from silicon oxide in order to protect the gate by using a higher gate dielectric constant material around it and saving cost by using silicon oxide as the secondary spacer to save cost while protecting gate stack. However, Hsu et al does not explicitly disclose and wherein the second gate spacer comprises a second inner sidewall facing the gate stack, and wherein the second inner sidewall overlaps, and is vertically aligned to, the first inner sidewall. On the other hand, Balseanu et al discloses wherein the second gate spacer (20,Fig.1) comprises a second inner sidewall (vertical portion of 20 and horizontal portion of 20 0verlap 56) facing the gate stack (Fig.1), and wherein the second inner sidewall overlaps (horizontal portion) , and is vertically aligned to (the vertical portion), the first inner sidewall (60). It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify Hsu et al according to the teachings of the Balseanu et al such that a second gate spacer is formed in order to stress or strain the source and drain regions and protect the gate electrode from outside interference.
With respect to claim 2, Hsu et al discloses a dielectric layer (40), wherein both of a first top surface of the contact etch stop layer (Fig.8) and a second top surface of the second gate spacer (Fig.8) are in contact with a bottom surface of the dielectric layer (Fig.8).
With respect to claim 3, Hsu et al discloses wherein a first edge of the first gate spacer (outer edge) sis substantially flush with a second edge of the second gate spacer (inner edge).
With respect to claim 4, Hsu et al does not explicitly disclose wherein the first gate spacer extends laterally beyond the second gate spacer. On the other hand, it would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify Hsu et al such that the first gate spacer extends laterally beyond the second gate spacer, in order to protect the source or drain region from extra dielectric material later deposited on the first gate spacer.
Claim(s) 5-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hsu et al (US Pub No. 20190058050), in view of Zang et al (US Pub No. 20190164898), in view of Balsenu et al (US Pub No. 20080020591).
With respect to claim 5, Hsu et al does not explicitly disclose wherein the second gate spacer extends laterally beyond the first gate spacer. On the other hand, Zang et al discloses wherein the second gate spacer (320, Fig.17) extends laterally beyond the first gate spacer (310). It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify Hsu et al according to the teachings of the Zang et al such that the second gate spacer extends laterally beyond the first gate spacer, in order to make a more compact device.
With respect to claim 6, Zang discloses wherein the semiconductor region comprises a semiconductor fin (120), and wherein an interface between the first gate spacer and the second gate spacer is at a level higher than a top surface of the semiconductor fin (Fig.17).
With respect to claim 7, Zang discloses wherein the semiconductor region comprises a semiconductor fin (120), and wherein an interface between the first gate spacer and the second gate spacer (bottom portion of the interface) is level with a top surface of the semiconductor fin (is in direct contact with the top surface of the fin).
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hsu et al (US Pub No. 20190058050), in view of Wang (US Pub No. 20170338341), in view of Balsenu et al (US Pub No. 20080020591).
With respect to claim 8, Hsu et al does not explicitly disclose wherein the second gate spacer comprises a plurality of sub layers, with upper ones of the plurality of sub layers overlapping respective lower ones of the plurality of sub layers. On the other hand, Wang discloses the second gate spacer (132,134,Fig.2K) comprises a plurality of sub layers (Fig.2K), with upper ones of the plurality of sub layers (the lower portion of 134) overlapping respective lower ones of the plurality of sub layers (132). It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify Hsu et al according to the teachings of the Wang such that the second spacer has plurality of the layers, in order to better protect the gate structure from the outside interference.
Response to Arguments
Applicant's arguments filed on 02/09/2026 have been fully considered but they are not persuasive. As far as applicant’s arguments that the restriction is not proper because examiner merely is saying that independent claims 9 and 16 have different elements from the claim 1. However, theses different elements make those claims mutually exclusive from each other. In each of those claims the sidewall spacers and etch stop layers are described completely different from each other. Furthermore, reference Balseanu et al discloses the new limitations added to the claim 1.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALI N NARAGHI whose telephone number is (571)270-5720. The examiner can normally be reached 10am-6pm.
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/ALI NARAGHI/Primary Examiner, Art Unit 2817
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