DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
2. Applicants’ arguments presented in the Response dated 07/02/2025, are persuasive, therefore, the rejections of the previous Office action are withdrawn, and prosecution on the merits reopened in view of the newly applied prior art and other issues detailed below.
Claim Rejections - 35 USC § 102
3. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
4. Claim(s) 1-10, 12-13, 22, 24-30, is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al., US 2020/0098811 A1.
Claim 1. Chen et al., disclose a package (such as the one in fig. 1, item 10) comprising:
-a semiconductor wafer including an optical sensor die (item 114), the optical sensor-die having an optically active area on a front side of the semiconductor wafer generating a raw image signal (this limitation would read through [0039] wherein is disclosed the optical element 114 may include a microlens array, a color filter, or a combination thereof or another suitable optical element);
-a transparent cover (item 200) attached to the front side of the semiconductor wafer;
-the transparent cover disposed above the optically active area of the optical sensor die in the semiconductor wafer (as seen in the structure of fig. 1);
-and an image signal processor (ISP) die (item 102) embedded in a layer of molding material (item 132), the layer of the molding material attached to the semiconductor wafer on a back side opposite the front side of the semiconductor wafer, the ISP image signal processor die processing the raw image signal (this limitation would read through [0038] wherein is disclosed the aforementioned structure is fabricated by sequentially performing a front-end process (for example, the sensing region 102 is formed in the substrate 100) and a back-end process (for example, the insulating layer 110).
Claim 22. Chen et al., disclose a package (such as the one in fig. 1, item 10) comprising:
-an optical sensor-die (item 114) having an optically active area on a front side of the optical sensor die (this limitation would read through [0039] wherein is disclosed the optical element 114 may include a microlens array, a color filter, or a combination thereof or another suitable optical element);
-an image signal processor-die (item 102) attached to a bottom surface of the optical sensor die, the image signal processor die being embedded in a layer of molding material (item 132) disposed on a back side of the optical sensor die (this limitation would read through [0038] wherein is disclosed the aforementioned structure is fabricated by sequentially performing a front-end process (for example, the sensing region 102 is formed in the substrate 100) and a back-end process (for example, the insulating layer 110);
-and a transparent cover (item 200) attached to the front side of the optical sensor die, the transparent cover being disposed above the optically active area of the optical sensor die (as seen in the structure of fig. 1).
Claim 2. Chen et al., disclose the package of claim 1, further comprising: a first signal redistribution layer (item 136, fig. 1) disposed on a first surface (top surface) of the layer of the molding material corresponding to an outer surface of the package.
Claim 3. Chen et al., disclose the package of claim 2, further comprising, a conductive bump (item 106) disposed on the first signal redistribution layer disposed on the first surface of the layer of the molding material corresponding to the outer surface of the package.
Claim 4. Chen et al., disclose the package of claim 3, wherein the conductive bump disposed on the first signal redistribution layer disposed on the first surface of the layer of the molding material corresponding to the outer surface of the package includes at least one of a solder-bump (as [0052] disclose in some embodiments, the first conductive structure 136 includes aluminum, titanium, tungsten, copper, nickel, gold, or a combination thereof or another suitable conductive material).
Claim 5. Chen et al., disclose the package of claim 2, further comprising: a second signal redistribution layer (item 134) disposed the back side of the semiconductor wafer, the back side of the semiconductor wafer being adjacent to a second surface of the layer of the molding material opposite the first surface of the layer of the molding material.
Claims 6, 29. Chen et al., disclose the package of claim 5, wherein the image signal processor (ISP) die embedded in the layer of the molding material is positioned across from the optical sensor die in the semiconductor wafer and is bonded to the second signal redistribution layer disposed the back side of the semiconductor wafer (this limitation would read through [0038] wherein is disclosed the aforementioned structure is fabricated by sequentially performing a front-end process (for example, the sensing region 102 is formed in the substrate 100) and a back-end process (for example, the insulating layer 110).
Claim 7. Chen et al., disclose the package of claim 5, further comprising: a through-mold via (TMV) extending through a thickness of the layer of the molding material between the first surface of the layer of the molding material and the second surface of the layer of the molding material (this limitation would read through [0029] wherein is disclosed the first isolation portion 130a fills each of the second openings 103 of the substrate 100, and the second isolation portion 130b extends onto the second surface 100b of the substrate 100 from the first isolation portion 130a).
Claim 8. Chen et al., disclose the package of claim 5, further comprising: a through-semiconductor via (TSV) extending through a thickness of the semiconductor wafer, the TSV providing electrical connections between a front side of the optical sensor die and a back side of the optical sensor die (this limitation would read through [0031] wherein is disclosed the first conductive structure 136 is electrically isolated from the substrate 100 via the electrical isolation structure 132, and is in direct electrical contact with or indirectly electrically connected to the exposed conductive pads 106 through the first openings 101. Therefore, the first conductive portion 134a in the opening 101 is also referred to as a through substrate via (TSV)).
Claims 9, 30. Chen et al., disclose the package of claims 1, 22, wherein the transparent cover attached to the front side of the semiconductor wafer is a glass cover (this limitation would read through [0040] wherein is disclosed a cover plate 200 is provided. In the embodiment, the cover plate 200 includes glass, quartz, transparent polymer or another suitable transparent material).
Claim 10. Chen et al., disclose the package of claim 9, wherein the transparent cover is attached to the front side of the semiconductor wafer by a dam material layer (item 120) disposed around a periphery of the optically active area of the optical sensor die (this limitation would read through [0027] indicate that item 120 may referred to as dam).
Claims 12, 13. Chen et al., disclose the package of claim 1, further comprising: a black coating disposed on a side of a stack formed by the semiconductor wafer including the optical sensor die, the transparent cover bonded to the front side of the semiconductor wafer, and the layer of the molding material attached to the semiconductor wafer (this limitation would read through [0042] wherein is disclosed the spacer layer 120 is formed by a deposition process (such as a coating process, a physical vapor deposition process, a chemical vapor deposition process or another suitable process). Moreover, the spacer layer 120 includes epoxy resin, inorganic materials (such as silicon oxide, silicon nitride, silicon oxynitride, metal oxide or a combination thereof), organic polymer materials (such as polyimide, butylcyclobutene, parylene, polynaphthalenes, fluorocarbons or acrylates), or another suitable insulating material. Alternatively, the spacer layer 120 includes a photoresist material, and is patterned by a lithography process to form the cavity 116).
Claim 24. Chen et al., disclose the package of claim 22, where in the optical sensor die is an optical sensor die formed on a thinned semiconductor substrate (this limitation would read through [0039] wherein is disclosed an optical element 114 is formed on the insulating layer 110 on the first surface 100a of the substrate 100, and corresponds to the sensing region 102).
Claim 25. Chen et al., disclose the package of claim 24, wherein the optical sensor die includes a through-semiconductor via in the thinned semiconductor substrate at least one edge of the optical sensor-die (this limitation would read through [0039] wherein is disclosed an optical element 114 is formed on the insulating layer 110 on the first surface 100a of the substrate 100, and corresponds to the sensing region 102).
Claim 26. Chen et al., disclose the package of claim 24, further comprising: a through-mold via in the layer of molding material disposed on the back side of the optical sensor die (this limitation would read through [0031] wherein is disclosed the first conductive structure 136 is electrically isolated from the substrate 100 via the electrical isolation structure 132, and is in direct electrical contact with or indirectly electrically connected to the exposed conductive pads 106 through the first openings 101. Therefore, the first conductive portion 134a in the opening 101 is also referred to as a through substrate via (TSV)).
Claim 27. Chen et al., disclose the package of claim 24, wherein a first signal redistribution layer is disposed on a back side of the thinned semiconductor substrate (this limitation would read through [0031] wherein is disclosed the first conductive structure 136 is electrically isolated from the substrate 100 via the electrical isolation structure 132, and is in direct electrical contact with or indirectly electrically connected to the exposed conductive pads 106 through the first openings 101. Therefore, the first conductive portion 134a in the opening 101 is also referred to as a through substrate via (TSV)).
Claim 28. Chen et al., disclose the package of claim 24, wherein a second signal redistribution layer (item 134b, fig. 1) is disposed on a back surface of the layer of molding material on a back side of the thinned semiconductor substrate.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILNER JEAN BAPTISTE whose telephone number is (571)270-7394. The examiner can normally be reached M-T 8:00-6:00.
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/W.J/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899