DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed December 22, 2025 has been entered. Claims 1-16, 21-23, and 25 remain pending in the application. Claims 4-5, 10, and 16 remain withdrawn as being drawn to nonelected species in the reply filed on April 17, 2025.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 11-14 are rejected under 35 U.S.C. 103 as being unpatentable over Tsai et. al. (US 20200035605 A1), hereinafter Tsai, in view of Kawamura (US 20130082393 A1), in further view of Hsieh et. al. (US 20190088542 A1), hereinafter Hsieh.
Regarding claim 11, Tsai teaches a semiconductor device structure (Fig 1M integrated circuit device 200, [0015]), comprising: a gate structure (Fig 1C replacement gate structure 120, [0019]) formed over a substrate (Fig 1M substrate 102, [0016]); a source/drain (S/D) structure (Fig 1M source region 106S and drain region 106D, [0016]) formed adjacent to the gate structure (Fig 1C replacement gate structure 120, [0019]); a first dielectric layer (Fig 1M ILD layer 124, [0036]) formed over the gate structure (Fig 1C replacement gate structure 120, [0019]) and the S/D structure (Fig 1M source region 106S and drain region 106D, [0016]); an S/D contact structure (Fig 1M source contact 134S and drain contact 134D, [0041]) formed in the first dielectric layer (Fig 1M ILD layer 124, [0036]) over the S/D structure (Fig 1M source region 106S and drain region 106D, [0016]); a second dielectric layer (Fig 1M ILD layer 140, [0042]) formed over the S/D contact structure (Fig 1M source contact 134S and drain contact 134D, [0041]); a first conductive via (Fig 1M via contact 142S, [0044]) formed in the second dielectric layer (Fig 1M ILD layer 140, [0042]) and over the S/D contact structure (Fig 1M source contact 134S and drain contact 134D, [0041]); and a second conductive via (Fig 1M via contact 142D, [0044]) adjacent to the first conductive via (Fig 1M via contact 142S, [0044]); and an etching stop layer (Fig 1M etch stop layer 138, [0042]) between the first dielectric layer (Fig 1M ILD layer 124, [0036]) and the second dielectric layer (Fig 1M ILD layer 140, [0042]), wherein an interface between the first conductive via (Fig 1M via contact 142S, [0044]) and the S/D contact structure (Fig 1M source contact 134S and drain contact 134D, [0041]) is lower than a top surface of the etching stop layer (Fig 1M etch stop layer 138, [0042]).
Tsai fails to teach the first conductive via has a protruding portion embedded in the first dielectric layer and the second conductive via has a protruding portion embedded in the first dielectric layer.
However, Kawamura teaches first conductive via (Figs 24-26 wiring W1, [0213] corresponds to Tsai: Fig 1M via contact 142S, [0044]) has a protruding portion (Figs 25 and 26 portion of W1 on either side of plug PL1) embedded in the first dielectric layer (Fig 25 and 25 insulating film SO, [0215]) and the second conductive via (Figs 24-26 wiring W1, [0213] corresponds to Tsai: Fig 1M via contact 142D, [0044]) has a protruding portion (Figs 25 and 26 portion of W1 on either side of plug PL1) embedded in the first dielectric layer (Fig 25 and 25 insulating film SO, [0215]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified Tsai to incorporate the teachings of Kawamura by having the first conductive via with a protruding portion embedded in the first dielectric layer and the second conductive via with a protruding portion embedded in the first dielectric layer. This would improve the electrical performance of the semiconductor device ([0012]).
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Regarding claim 12, Tsai as modified in claim 11 teaches a bottommost surface of the first conductive via (Fig 1M via contact 142S and 142D, [0044]) is lower (Tsai as modified in claim 11 would have a portion of 142S or 142D below the top of 134S or 134D) than a top surface of the S/D contact structure (Fig 1M source contact 134S and drain contact 134D, [0041]).
Regarding claim 13, Tsai as modified in claim 11 teaches a portion of a sidewall (Tsai as modified in claim 11 would have a portion of 142S or 142D covering a portion of the sidewall the top of 134S or 134D) of the S/D contact structure (Fig 1M source contact 134S and drain contact 134D, [0041]) is covered by the first conductive via (Fig 1M via contact 142S and 142D, [0044]).
Regarding claim 14, Tsai as modified in claim 11 teaches the first conductive via (Tsai: Fig 1M via contact 142S and 142D, [0044]) comprises a first conductive material (Tsai: Cu, [0045]), and the first conductive material (Tsai: Cu, [0045]) is in direct contact (Tsai: Fig 1M) with the first dielectric layer (Tsai: Fig 1M ILD layer 124, [0036]; Tsai as modified in claim 11 would have a protrusion that would be in contact with ILD layer 124) and the second dielectric layer (Tsai: Fig 1M ILD layer 140, [0042]).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Tsai et. al. (US 20200035605 A1), hereinafter Tsai, in view of Kawamura (US 20130082393 A1), in further view of Hsieh et. al. (US 20190088542 A1), hereinafter Hsieh, in further view of Chen (US 20210134665 A1).
Tsai as modified in claim 11 fails to teach the S/D contact structure has a rounded top surface.
However, Chen teaches the S/D contact structure (Fig 2C S/D contact structure 146 with protection layer 150, [0051] corresponds to Tsai: Fig 1M source contact 134S and drain contact 134D, [0041]) has a rounded top surface (Fig 2C).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified Tsai and Kawamura to incorporate the teachings of Chen by having the S/D contact structure with a rounded top surface. This would act to protect the S/D contact from being polluted ([0051]).
Allowable Subject Matter
Claims 1-3, 6-9, 21-23, and 25 are allowed.
Regarding claim 1, the closest art is Tsai et. al. (US 20200035605 A1), hereinafter Tsai, in view of Kawamura (US 20130082393 A1).
Tsai teaches a semiconductor device structure (Fig 1M integrated circuit device 200, [0015]), comprising: a fin structure (Fig 1M not shown semiconductor device of 1A may be a FinFET, [0015]) formed over a substrate (Fig 1M substrate 102, [0016]); a gate structure (Fig 1C replacement gate structure 120, [0019]) formed over ([0016]) the fin structure (Fig 1M not shown semiconductor device of 1A may be a FinFET, [0015]); a gate spacer layer (Fig 1D gate spacers 110, [0022]) adjacent to the gate structure (Fig 1D replacement gate structure 120, [0019]); a source/drain (S/D) structure (Fig 1M source region 106S and drain region 106D, [0016]) formed over ([0016]) the fin structure (Fig 1M not shown semiconductor device of 1A may be a FinFET, [0015]) and adjacent (Fig 1M) to the gate structure (Fig 1C replacement gate structure 120, [0019]); a first dielectric layer (Fig 1M ILD layer 124, [0036]) formed over (Fig 1M) the gate structure (Fig 1A gate structure 109, [0016]) and the S/D structure (Fig 1M source region 106S and drain region 106D, [0016]); an S/D contact structure (Fig 1M source contact 134S and drain contact 134D, [0041]) formed in the first dielectric layer (Fig 1M ILD layer 124, [0036]) over the S/D structure (Fig 1M source region 106S and drain region 106D, [0016]); a second dielectric layer (Fig 1M ILD layer 140, [0042]) formed over (Fig 1M) the S/D contact structure (Fig 1M source contact 134S and drain contact 134D, [0041]); and a first conductive via (Fig 1M via contact 142S and 142D, [0044]) formed in (Fig 1M) the second dielectric layer (Fig 1M ILD layer 140, [0042]), wherein the first conductive via (Fig 1M via contact 142S and 142D, [0044]) is directly over (Fig 1M) the S/D contact structure (Fig 1M source contact 134S and drain contact 134D, [0041]) or directly over (optional so not considered) the gate structure (optional so not considered).
Tsai fails to teach the first conductive via has a protruding portion that is lower than a top surface of the S/D contact structure or lower (optional so not considered) than a top surface (optional so not considered) of the gate structure (optional so not considered), and a side portion of the first conductive via is directly over the gate spacer layer.
However, Kawamura teaches the first conductive via (Figs 24-27 wiring W1, [0213] corresponds to Tsai: Fig 1M via contact 142S and 142D, [0044]) has a protruding portion (Figs 26 and 27 portion of W1 on either side of plug PL1) that is lower than a top surface (Figs 26 and 27) of the S/D contact structure (Figs 26 and 27 plug PL1, [0214] corresponds to Tsai: Fig 1M source contact 134S and drain contact 134D, [0041]).
Tsai and Kawamura fail to teach a side portion of the first conductive via is directly over the gate spacer layer.
Examiner notes Kawamura shows a single side portion (Fig 27 left wiring W1 over unlabeled sidewall SW1) of the first conductive layer (Figs 27 wiring W1, [0213] corresponds to Tsai: Fig 1M via contact 142S and 142D, [0044]) directly over a gate spacer layer (Fig 4 sidewall SW1, [0114] corresponds to Tsai: Fig 1D gate spacers 110, [0022]) but provides no teaching, suggestion, or motivation for doing so.
Claims 2-3 and 6-9 would be allowable because they are dependent on claim 1.
Regarding claim 21, the closest art is Tsai et. al. (US 20200035605 A1), hereinafter Tsai.
Tsai teaches a semiconductor device structure (Fig 1M integrated circuit device 200, [0015]), comprising: a fin structure (Fig 1M not shown semiconductor device of 1A may be a FinFET, [0015]) formed along a first direction (Fig 1M left to right) over a substrate (Fig 1M substrate 102, [0016]); a gate structure (Fig 1C replacement gate structure 120, [0019]) formed along a second direction (Fig 1M up and down), wherein the second direction (Fig 1M up and down) is orthogonal to the first direction (Fig 1M left to right); a source/drain (S/D) structure (Fig 1M source region 106S and drain region 106D, [0016]) formed adjacent to the gate structure (Fig 1C replacement gate structure 120, [0019]); an S/D contact structure (Fig 1M source contact 134S and drain contact 134D, [0041]) formed over the S/D structure (Fig 1M source region 106S and drain region 106D, [0016]), wherein the S/D contact structure (Fig 1M source contact 134S and drain contact 134D, [0041]) has a first width (Fig 1M top of S/D contact structure) along the first direction (Fig 1M left to right); a first conductive via (Fig 1M via contact 142S and 142D, [0044]) formed over the S/D contact structure (Fig 1M source contact 134S and drain contact 134D, [0041]), wherein the first conductive via (Fig 1M via contact 142S and 142D, [0044]) has a second width (Fig 1M top of via contact) along the first direction (Fig 1M left to right), and the second width (Fig 1M top of via contact) is greater than (Fig 1M) the first width (Fig 1M top of S/D contact structure), wherein a longitudinal direction (Fig 1M up/down direction) of the S/D contact structure (Fig 1M source contact 134S and drain contact 134D, [0041]) is along the second direction (Fig 1M up and down), and a longitudinal direction (Fig 1M left to right) of the first conductive via (Fig 1M via contact 142S and 142D, [0044]) is along the first direction (Fig 1M left to right) when seen in a top view (Examiner notes that a semiconductor device necessarily has a top view and a longitudinal direction of the first conductive via along the first direction would be seen in a top view); and a gate spacer layer (Tsai: Fig 1C gate spacer 110, [0022]) adjacent to the gate structure (Tsai: Fig 1C replacement gate structure 120, [0019]).
Tsai fails to teach a sidewall portion of the first conductive via is directly over the gate spacer layer.
Examiner notes, similar to claim 1, Kawamura shows a single side portion (Fig 27 left wiring W1 over unlabeled sidewall SW1) of the first conductive layer (Figs 27 wiring W1, [0213] corresponds to Tsai: Fig 1M via contact 142S and 142D, [0044]) directly over a gate spacer layer (Fig 4 sidewall SW1, [0114] corresponds to Tsai: Fig 1D gate spacers 110, [0022]) but provides no teaching, suggestion, or motivation for doing so.
Claims 22-23 and 25 would be allowable because they are dependent on claim 21.
Response to Arguments
Applicant’s arguments, see 35 USC §112 section on page 8, filed December 22, 2025, with respect to amendments to claim 11 have been fully considered and are persuasive. The 35 USC §112 rejection of claim 11 has been withdrawn.
Applicant's arguments, see 35 USC §102/103 section on page 10, filed December 22, 2025, with respect to the 35 USC §103 rejection of claim 11 have been fully considered but they are not persuasive.
As disclosed in the rejection above, Tsai shows the limitation of the amendment.
Applicant’s arguments, see 35 USC §102/103 section on page 10, filed December 22, 2025, with respect to amendments to claim 21 have been fully considered and are persuasive. The 35 USC §102/103 rejection of claim 21 and dependent claims has been withdrawn.
Regarding the rejoinder of claims, see page 11, filed December 22, 2025, with respect to rejoinder of claims 4-5, 10, and 16. Examiner will address rejoinder at the time of allowance for the entire application.
Conclusion
The Examiner has pointed out particular references contained in the prior art of record within the body of this action for the convenience of the Applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALVIN L LEE whose telephone number is (703)756-1921. The examiner can normally be reached Monday - Friday 8:30 am - 5 pm (ET).
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/ALVIN L LEE/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813