Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 6, 8 and 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Morris (20200251049).
Regarding claim 1, Morris teaches a device (please see device in fig. 42), comprising:
PLEASE NOTE that fig. 42 does not have the elements labeled; thus, figs. 16 and 17, which are the same device structure as fig. 42, and are labeled, will be relied upon for the labels.
a top portion comprising a metal layer structure (fig. 16, 17, 42: 1624; please see in fig. 42, 1624 is on top of TFT 1622; further, fig. 42 shows that attached to 1624 is another interconnect extending in the X direction);
a bottom portion below the top portion comprising a backside power rail structure (see fig. 16: 1830; please note fig. 42 this configuration showing this limitation); and
an interconnect structure electrically connecting the metal layer structure to the backside power rail structure (fig. 16, 17, 42: please see interconnect structure below and above TFT in fig. 17, in the X and Y direction) and
comprising:
a first portion located along a central, vertical axis within the top portion and comprising an approximately hemispherical structure (see fig. 16, portion 1628 of the interconnect structure) at an interface between the top portion and the bottom portion (please see fig. 16 and 42 which teaches an interconnect structure below and above TFT in fig. 17, in the X and Y direction); and
a second portion approximately co-located along the central, vertical axis within the bottom portion and comprising an end that joins with the approximately hemispherical structure of the first portion (please see fig. 16 and 42 which teaches an interconnect structure below and above TFT in fig. 17, in the X and Y direction).
Regarding claim 6, Morris teaches a device (please see device in fig. 42), comprising:
PLEASE NOTE that fig. 42 does not have the elements labeled; thus, figs. 16 and 17, which are the same device structure as fig. 42, and are labeled, will be relied upon for the labels.
a transistor structure (fig. 16: 1622) comprising a plurality of channel structures (please see fig. 42 which shows multiple TFTs with multiple channels);
a metal layer structure above the plurality of channel structures (fig. 16, 17, 42: 1624; please see in fig. 42, 1624 is on top of TFT 1622; further, fig. 42 shows that attached to 1624 is another interconnect extending in the X direction);
a first interconnect structure above the transistor structure and electrically connecting the transistor structure to the metal layer structure (please see fig. 16 and 42 which teaches an interconnect structure below and above TFT in fig. 17, in the X and Y direction; further, this interconnect is electrically connected to the TFT); and
a second interconnect structure adjacent to the transistor structure (please see fig. 16 and 42 which teaches an interconnect structure below and above TFT in fig. 17, in the X and Y direction; further, this interconnect is electrically connected to the TFT)
comprising:
a first end electrically connected to the metal layer structure ((please see fig. 16 and 42 which teaches an interconnect structure below and above TFT in fig. 17, in the X and Y direction);
a second end electrically connected to a backside power rail structure (please see fig. 16 and 42 which teaches an interconnect structure below and above TFT in fig. 17, in the X and Y direction); and
a bowed-profile portion (fig. 16: portion 1628) between the first end and the second end.
Regarding claim 8, Morris teaches a device of claim 6, wherein the second interconnect structure comprises: a tapered portion between the first end and the bowed-profile portion (please see fig.16 and 42 wherein the interconnect below the TFT that has this structure).
Regarding claim 10, Morris teaches a device of claim 6, further comprising: a dielectric liner surrounding a portion of the second interconnect structure (par. 167 and fig. 16 shows the interconnects being surrounded by oxide layer i.e. ILD).
Allowable Subject Matter
Claims 2-5 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 7 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 9 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 11-20 allowed.
The following is an examiner’s statement of reasons for allowance: prior art fails to anticipate and/or obviate all limitations mentioned in independent claim 11, as well as the temporal ordering of steps outlined in claim 11. Case in point, prior art fails to teach ; removing the layer of silicon germanium material to expose a bottom surface of the bottom layer of semiconductor material; forming a second plurality of layers of materials on the bottom surface of the bottom layer of semiconductor material, wherein the second plurality of layers of materials are arranged in a second direction that is perpendicular to the bottom layer of semiconductor material and opposite the first direction; forming a second portion of the interconnect structure through the second plurality of layers of materials; and forming a backside power rail structure that makes electrical contact with the second portion of the interconnect structure..
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CALEB E HENRY whose telephone number is (571)270-5370. The examiner can normally be reached Mon-Fri.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/CALEB E HENRY/Primary Examiner, Art Unit 2818
Prosecution Insights