DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/04/25 has been entered.
Claim 21 is objected to because of the following informalities: “the top seal” should read as “the top seal ring”. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 16-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In claim 16, it is indefinite as to how the first and second through-substrate via (TSV)’s, respectively are connected to the continuous seal rings in order to comprise the plurality of seal ring pillars. In the applicant’s disclosure of, figure 9A [0081-0083], the delamination monitoring structure (DMS) (960) is described to be two different structures. Specifically, the through-substrate via (TSV) (961) is in a completely separate location from the continuous seal ring (980) where the plurality of seal ring pillars (982) are located at the interface (950) (see figure 9C, [0097]).
It is indefinite, which plurality of seal ring pillar interconnections that electrically connect the seal ring pillars. Specifically, it is unclear whether it is the “at least one seal ring pillar” or the continuous seal ring comprising “a plurality of seal ring pillars”.
For the purpose of examination on the merits the examiner will view the delamination monitoring structure (DMS) and the seal ring as to separate structures.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-6, 21-24 and 26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ho et al. (US PGPub 2015/0194455, hereinafter referred to as “Ho”) in view of Uchida et al. (US PGPub 2018/0047680, hereinafter referred to as “Uchida”).
Ho discloses the semiconductor device substantially as claimed. See figures 1A-7 and corresponding text, where Ho shows, in claim 1, a package structure comprising:
a bottom die (200) comprising: (examiner views that the devices are die-to-die level [0029])
a first active region (portions in-between the seal rings (208) that are not connected) surrounded by a first seal ring region (208); (figure 6; [0048])
the first seal ring region (208) comprising a bottom seal ring (208A, 208B); (figure 6; [0048]) and
a first bonding layer (210) disposed on a front side of the bottom die (200); (figure 6; [0048])
a top die (100) comprising:
a second active region (portions in-between the seal rings (616) that are not connected) surrounded by a second seal ring region (616);
the second seal ring region (616) comprising a top seal ring (616A, 616B); (figure 6; [0048]) and
a second bonding layer (112) disposed on a front side of the top die (100); and
wherein the bottom die (200) and the top die (100) are bonded through hybrid bonding ([0048]) between the first bonding layer (210) and the second bonding layer (112) at an interface therebetween such that the bottom seal ring (208A, 208B) and the top seal ring (616A, 616B) are vertically aligned and are operable to form a continuous seal ring such that the bottom seal ring and the top seal are electrically connected across the interfaces (figure 6; [0048]).
Ho fails to show, in claim 1, an additional active region embedded in the bottom die and connected to the bottom seal ring in the first seal ring region;
wherein the additional active region is configured to provide an electrical path to discharge charges formed in the interface during wafer stacking.
Uchida teaches, in claim 1, implanting ions of a p-type impurity and n-type impurity into the semiconductor substrate in the seal ring region SR (figure 1; [0081-0085], [0093-0095], [0107-0109]). In addition, Uchida provides the advantages of improving moisture resistance, preventing chipping of the semiconductor device, suppressing propagation of noise through the seal ring to the semiconductor substrate, and allowing for the electric charges stored in the box layer to flow through the semiconductor substrate prevents destruction of the box layer. ([0004-0007], [00[0171]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to incorporate an additional active region embedded in the bottom die and connected to the bottom seal ring in the first seal ring region;
wherein the additional active region is configured to provide an electrical path to discharge charges formed in the interface during wafer stacking, in the device of Ho, according to the teachings of Uchida, with the motivation of allowing for the electric charges stored in a buried insulating layer to flow through the semiconductor substrate preventing destruction of the buried layer and suppressing propagation of noise.
Ho in view of Uchida shows, in claim 2, further comprising:
a first plurality of bottom hybrid bonding metal pads (HBMPs) (614A2, 612B, 614B2) disposed in the first bonding layer (210) in the first seal ring region (208); and
a first plurality of top HBMPs (614A1, 612A, 614B1) disposed in the second bonding layer (112) in the second seal ring region (616), wherein the first plurality of top HBMPs (614A1, 612A, 614B1) are bonded to the first plurality of the bottom HBMPs (614A2, 612B, 614B2), respectively (figure 6; [0047-0048], Ho).
Ho in view of Uchida shows, in claim 3, further comprising: a first plurality of bottom hybrid bonding vias (HBVs) (614A2, 612B, 614B2) disposed in the first bonding layer (210) and respectively connecting the bottom HBMPs (614A2, 612B, 614B2) and the bottom seal ring (208) (figure 6; [0047]); and
a first plurality of top HBVs (614A1, 612A, 614B1) disposed in the second bonding layer (112) and respectively connecting the top HBMPs (614A1, 612A, 614B1) and the top seal ring (616) (figure 6; [0047])
Ho in view of Uchida shows, in claim 4, wherein the first active region and the second active region are vertically aligned, and wherein the first seal ring region (208) and the second seal ring region (616) are vertically aligned (figure 6; [0048]).
Ho in view of Uchida shows, in claim 5, further comprising:
a first multilayer interconnect (MLI) structure (206) disposed in the first active region; (figure 6; [0019], [0047])
a second plurality of bottom hybrid bonding metal pads (HBMPs) (614A2, 612B, 614B2) disposed in the first bonding layer (210) in the first active region and connected to the first MLI structure (206) (figure 6;[0019], [0047]);
a second MLI structure (110) disposed in the second active region (figure 6; [0019], [0047]); and
a second plurality of top HBMPs (614A1, 612A, 614B1) disposed in the second bonding layer (112) in the second active region and connected to the second MLI structure (110), wherein the second plurality of top HBMPs (614A1, 612A, 614B1) are bonded to the second plurality of the bottom HBMPs 614A2, 612B, 614B2), respectively (figure 6; [0019], [0047]).
Ho in view of Uchida shows, in claim 6, further comprising an interconnect structure (110A) disposed on a bottom surface of the top die, wherein the interconnect structure comprises a conductive trace and a passivation layer that covers the conductive trace (figure 6; [0019], [0047]).
Ho shows, in claim 21, a package structure comprising:
a bottom die (200) comprising:
a first active region; (figure 6; [0048])
a first seal ring region (208) surrounding the first active region and comprising a bottom seal ring; and(figure 6; [0048])
a first bonding layer (210) disposed on a front side of the bottom die;
a top die (100) comprising:
a second active region; (figure 6; [0048])
a second seal ring region (616) surrounding the second active region and comprising a top seal ring; (figure 6; [0048])and
a second bonding layer (112) disposed on a front side of the top die (100); and
wherein the bottom die (200) and the top die (100) are bonded through hybrid bonding at an interface therebetween, the first bonding layer (210) is bonded to the second bonding layer (112), the bottom seal ring (208A, 208B) and the top seal ring (616A, 616B) are vertically aligned, forming a continuous seal ring comprising the bottom seal ring (208A, 208B) and the top seal ring (616A, 616B) such that the bottom seal ring and the top seal ring (616A, 616B) are electrically connected across the interface; (figure 6; [0048])
However, Ho fails to show, in claim 21, an additional active region embedded in the bottom die and connected to the bottom seal ring in the first seal ring region;
wherein the additional active region is configured to provide an electrical path to discharge charges formed in the interface during wafer stacking.
Uchida teaches, in claim 21, implanting ions of a p-type impurity and n-type impurity into the semiconductor substrate in the seal ring region SR (figure 1; [0081-0085], [0093-0095], [0107-0109]). In addition, Uchida provides the advantages of improving moisture resistance, preventing chipping of the semiconductor device, suppressing propagation of noise through the seal ring to the semiconductor substrate, and allowing for the electric charges stored in the box layer to flow through the semiconductor substrate prevents destruction of the box layer. ([0004-0007], [00[0171]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to incorporate an additional active region embedded in the bottom die and connected to the bottom seal ring in the first seal ring region;
wherein the additional active region is configured to provide an electrical path to discharge charges formed in the interface during wafer stacking, in the device of Ho, according to the teachings of Uchida, with the motivation of allowing for the electric charges stored in a buried insulating layer to flow through the semiconductor substrate preventing destruction of the buried layer and suppressing propagation of noise.
Ho in view of Uchida shows, in claim 22, further comprising:
a first plurality of bottom hybrid bonding metal pads (HBMPs) disposed in the first bonding layer in the first seal ring region; (figure 6; [0047-0048], Ho) and
a first plurality of top HBMPs disposed in the second bonding layer in the second seal ring region, wherein the first plurality of top HBMPs are bonded to the first plurality of the bottom HBMPs, respectively (figure 6; [0047-0048], Ho).
Ho in view of Uchida shows, in claim 23, further comprising: a first plurality of bottom hybrid bonding vias (HBVs) disposed in the first bonding layer and respectively connecting the bottom HBMPs and the bottom seal ring (figure 6; [0047-0048], Ho); and
a first plurality of top HBVs disposed in the second bonding layer and respectively connecting the top HBMPs and the top seal ring (figure 6; [0047-0048], Ho).
Ho in view of Uchida shows, in claim 24, wherein the first active region and the second active region are vertically aligned, and wherein the first seal ring region and the second seal ring region are vertically aligned (figure 6; [0047-0048], Ho).
Ho in view of Uchida shows, in claim 26, wherein the bottom die comprises a substrate, and wherein the additional active region is embedded in the substrate and is connected to the bottom seal ring at a front surface of the substrate (figure 1; [0081-0085], [0093-0095], [0107-0109], Uchida).
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ho et al. (US PGPub 2015/0194455, hereinafter referred to as “Ho”) in view of Uchida et al. (US PGPub 2018/0047680, hereinafter referred to as “Uchida”) as applied to claim 1 above, and further in view of Chang et al. (US PGPub 2022/0165664, hereinafter referred to as “Chang”).
Ho in view of Uchida discloses the semiconductor device substantially as claimed. See the rejection above.
However, Ho in view of Uchida fails to show, in claim 7, further comprising a (deep trench capacitor) DTC region embedded in the top die, the DTC region comprising an array of DTCs.
Chang teaches, in claim 7, a similar device that includes an integrated circuit component that is a deep trench capacitor (DTC) die (figure 8; [0040]). In addition, Chang provides the advantages of including passive devices to improve electrical performance of the electrical circuit and less power consumption ([0015]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to incorporate further comprising a (deep trench capacitor) DTC region embedded in the top die, the DTC region comprising an array of DTCs, in the device of Ho in view of Uchida, according to the teachings of Chang, with the motivation of improve electrical performance of the electrical circuit and enabling less power consumption in the top die.
Claim(s) 9 and 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ho et al. (US PGPub 2015/0194455, hereinafter referred to as “Ho”) in view of Uchida et al. (US PGPub 2018/0047680, hereinafter referred to as “Uchida”) as applied to claims 1 and 21 above, and further in view of Chen et al. (US PGPub 2020/0075435, hereinafter referred to as “Chen”).
Ho in view of Uchida discloses the semiconductor substantially as claimed. See the rejection above.
However, Ho in view of Uchida fails to show, in claim 9, further comprising a delamination monitoring structure (DMS) configured to monitor delamination in the first seal ring region and the second seal ring region.
Chen teaches, in claim 9, a similar package device that includes the use of a detecting device that determines cracks within the semiconductor device that indicate that the seal ring is damaged (figures 1-3; [0029]). In addition, Chen provides the advantages of improving detection of cracks, delamination, and other defects within the semiconductor device ([0017-0018]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to incorporate further comprising a delamination monitoring structure (DMS) configured to monitor delamination in the first seal ring region and the second seal ring region, in the device of Ho in view of Uchida, according to the teachings of Chen, with the motivation of improving detection of cracks, delamination, and other defects within the semiconductor device.
Ho in view of Uchida fails to show, in claim 25, further comprising a delamination monitoring structure (DMS) configured to monitor delamination in the first seal ring region and the second seal ring region.
Chen teaches, in claim 25, a similar package device that includes the use of a detecting device that determines cracks within the semiconductor device that indicate that the seal ring is damaged (figures 1-3; [0029]). In addition, Chen provides the advantages of improving detection of cracks, delamination, and other defects within the semiconductor device ([0017-0018]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to incorporate further comprising a delamination monitoring structure (DMS) configured to monitor delamination in the first seal ring region and the second seal ring region, in the device of Ho in view of Uchida, according to the teachings of Chen, with the motivation of improving detection of cracks, delamination, and other defects within the semiconductor device.
Claim(s) 15-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ho et al. (US PGPub 2015/0194455, hereinafter referred to as “Ho”) in view of Uchida et al. (US PGPub 2018/0047680, hereinafter referred to as “Uchida”) in further view of Chen et al. (US PGPub 2020/0075435, hereinafter referred to as “Chen”).
Ho shows, in claim 15, a package structure comprising:
a bottom die (200) comprising:
a first active region surrounded by a first seal ring region (208);
a first seal ring region comprising a bottom seal ring (208A, 208B);
a first bonding layer (210) disposed on a front side of the bottom die;
a first plurality of bottom hybrid bonding metal pads (HBMPs) (614A2, 612B, 614B2) disposed in the first bonding layer (210) in the first seal ring region; and
a first plurality of bottom hybrid bonding via (HBVs) (614A2, 612B, 614B2) disposed in the first bonding layer and respectively connecting the bottom HBMPs (614A2, 612B, 614B2) and the bottom seal ring;
a top die (100) comprising:
a second active region surrounded by a second seal ring region (616);
a second seal ring region comprising a top seal ring (616A, 616B);
a second bonding layer (112) disposed on a front side of the top die (100);
a first plurality of top HBMPs (614A1, 612A, 614B1) disposed in the second bonding layer in the second seal ring region, wherein the first plurality of top HBMPs (614A1, 612A, 614B1) are bonded to the first plurality of the bottom HBMPs (614A2, 612B, 614B2), respectively; and
a first plurality top HBV (614A1, 612A, 614B1) disposed in the second bonding layer (112) and respectively connecting the top HBMPs (614A1, 612A, 614B1) and the top seal ring (616A, 616B);
wherein the bottom die (200) and the top die (100) are bonded through hybrid bonding ([0048]) between the first bonding layer (210) and the second bonding layer (112) at an interface therebetween such that the bottom seal ring (208A, 208B) and the top seal ring (616A, 616B) are vertically aligned, and wherein the bottom seal ring (208A, 208B), the bottom HBV (614A2, 612B, 614B2), the bottom HBMP (614A2, 612B, 614B2), the top HBMP (614A1, 612A, 614B1), the top HBV (614A1, 612A, 614B1), and the top seal ring (616A, 616B) [form a continuous seal ring] such that the bottom seal ring (208A, 208B) and the top seal ring (616A, 616B) are electrically connected across the interface (figure 6; [0047-0048]).
However, Ho fails to show, in claim 15, an additional active region embedded in the bottom die and connected to the bottom seal ring in the first seal ring region.
Uchida teaches, in claim 15, implanting ions of a p-type impurity and n-type impurity into the semiconductor substrate in the seal ring region SR (figure 1; [0081-0085], [0093-0095], [0107-0109]). In addition, Uchida provides the advantages of improving moisture resistance, preventing chipping of the semiconductor device, suppressing propagation of noise through the seal ring to the semiconductor substrate, and allowing for the electric charges stored in the box layer to flow through the semiconductor substrate prevents destruction of the box layer ([0004-0007], [00[0171]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to incorporate an additional active region embedded in the bottom die and connected to the bottom seal ring in the first seal ring region, in the device of Ho, according to the teachings of Uchida, with the motivation of allowing for the electric charges stored in a buried insulating layer to flow through the semiconductor substrate preventing destruction of the buried layer and suppressing propagation of noise.
Ho in view of Uchida fails to show, in claim 15, a delamination monitoring structure (DMS).
However, Chen teaches, in claim 15, a similar package device that includes the use of a detecting device that determines cracks within the semiconductor device that indicate that the seal ring is damaged (figures 1-3; [0029]). In addition, Chen provides the advantages of improving detection of cracks, delamination, and other defects within the semiconductor device ([0017-0018]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to incorporate a delamination monitoring structure (DMS), in the device of Ho in view of Uchida, according to the teachings of Chen, with the motivation of improving detection of cracks, delamination, and other defects within the semiconductor device.
Ho in view of Uchida in further view of Chen shows, in claim 16, wherein the DMS further comprises:
a first through-substrate via (TSV) (211); (figures 4-6; [0034-0036], Chen)
a second TSV (213);
a first routing connection;
a second routing connection; and
a portion of the continuous seal ring comprising a plurality of seal ring pillars, wherein the plurality of seal ring pillars comprise:
a starting continuous seal ring pillar;
an ending continuous seal ring pillar;
at least one seal ring pillar between the starting continuous seal ring pillar and the ending continuous seal ring pillar; and
a plurality of seal ring pillar interconnections that electrically connect the seal ring pillars to form an electrical path through the portion of the continuous seal ring], and wherein the first TSV is electrically connected to the starting continuous seal ring pillar through the first routing connection, and wherein the second TSV is electrically connected to the ending continuous seal ring pillar through the second routing connection.
Ho in view of Uchida in further view of Chen shows, in claim 17, wherein the DMS further comprises: (figures 4-6; [0034-0036], Chen)
a first monitoring structure metal pad (32) disposed on a back side of the top die and connected to the first TSV; and
a second monitoring structure disposed on the back side of the top die and connected to the second TSV.
Ho in view of Uchida in further view of Chen shows, in claim 18, wherein the electrical path crosses the interface multiple times. (figures 4-6; [0034-0036], Chen)
Ho in view of Uchida in further view of Chen shows, in claim 19, wherein the seal ring pillar interconnections are metal tracks extending horizontally. (figures 4-6; [0034-0036], Chen)
Ho in view of Uchida in further view of Chen shows, in claim 20, wherein the first routing connection comprises a first metal track disposed in a first metal layer in the top die, and wherein the second routing connection comprises a second metal track disposed in the first metal layer. (figures 4-6; [0034-0036], Chen)
Conclusion
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/STANETTA D ISAAC/ Examiner, Art Unit 2898 March 20, 2026