DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to the amendment filed on 6/29/26. Currently, claims 1-7, 9, and 15-26 are pending.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
The rejection of claim(s) 1-6, 21-24 and 26 is/are under 35 U.S.C. 103 as being unpatentable over Ho et al. (US PGPub 2015/0194455, hereinafter referred to as “Ho”) in view of Uchida et al. (US PGPub 2018/0047680, hereinafter referred to as “Uchida”) has been maintained for reasons of record.
Ho discloses the semiconductor device substantially as claimed. See figures 1A-7 and corresponding text, where Ho shows, in claim 1, a package structure comprising:
a bottom die (200) comprising: (examiner views that the devices are die-to-die level [0029])
a first active region (portions in-between the seal rings (208) that are not connected) surrounded by a first seal ring region (208); (figure 6; [0048])
the first seal ring region (208) comprising a bottom seal ring (208A, 208B); (figure 6; [0048]) and
a first bonding layer (210) disposed on a front side of the bottom die (200); (figure 6; [0048])
a top die (100) comprising:
a second active region (portions in-between the seal rings (616) that are not connected) surrounded by a second seal ring region (616);
the second seal ring region (616) comprising a top seal ring (616A, 616B); (figure 6; [0048]) and
a second bonding layer (112) disposed on a front side of the top die (100); and
wherein the bottom die (200) and the top die (100) are bonded through hybrid bonding ([0048]) between the first bonding layer (210) and the second bonding layer (112) at an interface therebetween such that the bottom seal ring (208A, 208B) and the top seal ring (616A, 616B) are vertically aligned and are operable to form a continuous seal ring such that the bottom seal ring and the top seal ring are electrically connected across the interfaces (figure 6; [0048]).
Ho fails to show, in claim 1, an additional active region embedded in the bottom die and connected to the bottom seal ring in the first seal ring region;
wherein the additional active region is configured to provide an electrical path to discharge charges formed in the interface during wafer stacking.
Uchida teaches, in claim 1, implanting ions of a p-type impurity and n-type impurity into the semiconductor substrate in the seal ring region SR (figure 1; [0081-0085], [0093-0095], [0107-0109]). In addition, Uchida provides the advantages of improving moisture resistance, preventing chipping of the semiconductor device, suppressing propagation of noise through the seal ring to the semiconductor substrate, and allowing for the electric charges stored in the box layer to flow through the semiconductor substrate prevents destruction of the box layer. ([0004-0007], [00[0171]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to incorporate an additional active region embedded in the bottom die and connected to the bottom seal ring in the first seal ring region;
wherein the additional active region is configured to provide an electrical path to discharge charges formed in the interface during wafer stacking, in the device of Ho, according to the teachings of Uchida, with the motivation of allowing for the electric charges stored in a buried insulating layer to flow through the semiconductor substrate preventing destruction of the buried layer and suppressing propagation of noise.
Ho in view of Uchida shows, in claim 2, further comprising:
a first plurality of bottom hybrid bonding metal pads (HBMPs) (614A2, 612B, 614B2) disposed in the first bonding layer (210) in the first seal ring region (208); and
a first plurality of top HBMPs (614A1, 612A, 614B1) disposed in the second bonding layer (112) in the second seal ring region (616), wherein the first plurality of top HBMPs (614A1, 612A, 614B1) are bonded to the first plurality of the bottom HBMPs (614A2, 612B, 614B2), respectively (figure 6; [0047-0048], Ho).
Ho in view of Uchida shows, in claim 3, further comprising: a first plurality of bottom hybrid bonding vias (HBVs) (614A2, 612B, 614B2) disposed in the first bonding layer (210) and respectively connecting the bottom HBMPs (614A2, 612B, 614B2) and the bottom seal ring (208) (figure 6; [0047]); and
a first plurality of top HBVs (614A1, 612A, 614B1) disposed in the second bonding layer (112) and respectively connecting the top HBMPs (614A1, 612A, 614B1) and the top seal ring (616) (figure 6; [0047])
Ho in view of Uchida shows, in claim 4, wherein the first active region and the second active region are vertically aligned, and wherein the first seal ring region (208) and the second seal ring region (616) are vertically aligned (figure 6; [0048]).
Ho in view of Uchida shows, in claim 5, further comprising:
a first multilayer interconnect (MLI) structure (206) disposed in the first active region; (figure 6; [0019], [0047])
a second plurality of bottom hybrid bonding metal pads (HBMPs) (614A2, 612B, 614B2) disposed in the first bonding layer (210) in the first active region and connected to the first MLI structure (206) (figure 6;[0019], [0047]);
a second MLI structure (110) disposed in the second active region (figure 6; [0019], [0047]); and
a second plurality of top HBMPs (614A1, 612A, 614B1) disposed in the second bonding layer (112) in the second active region and connected to the second MLI structure (110), wherein the second plurality of top HBMPs (614A1, 612A, 614B1) are bonded to the second plurality of the bottom HBMPs 614A2, 612B, 614B2), respectively (figure 6; [0019], [0047]).
Ho in view of Uchida shows, in claim 6, further comprising an interconnect structure (110A) disposed on a bottom surface of the top die, wherein the interconnect structure comprises a conductive trace and a passivation layer that covers the conductive trace (figure 6; [0019], [0047]).
Ho shows, in claim 21, a package structure comprising:
a bottom die (200) comprising:
a first active region; (figure 6; [0048])
a first seal ring region (208) surrounding the first active region and comprising a bottom seal ring; and(figure 6; [0048])
a first bonding layer (210) disposed on a front side of the bottom die;
a top die (100) comprising:
a second active region; (figure 6; [0048])
a second seal ring region (616) surrounding the second active region and comprising a top seal ring; (figure 6; [0048])and
a second bonding layer (112) disposed on a front side of the top die (100); and
wherein the bottom die (200) and the top die (100) are bonded through hybrid bonding at an interface therebetween, the first bonding layer (210) is bonded to the second bonding layer (112), the bottom seal ring (208A, 208B) and the top seal ring (616A, 616B) are vertically aligned, forming a continuous seal ring comprising the bottom seal ring (208A, 208B) and the top seal ring (616A, 616B) such that the bottom seal ring and the top seal ring (616A, 616B) are electrically connected across the interface; (figure 6; [0048])
However, Ho fails to show, in claim 21, an additional active region embedded in the bottom die and connected to the bottom seal ring in the first seal ring region;
wherein the additional active region is configured to provide an electrical path to discharge charges formed in the interface during wafer stacking.
Uchida teaches, in claim 21, implanting ions of a p-type impurity and n-type impurity into the semiconductor substrate in the seal ring region SR (figure 1; [0081-0085], [0093-0095], [0107-0109]). In addition, Uchida provides the advantages of improving moisture resistance, preventing chipping of the semiconductor device, suppressing propagation of noise through the seal ring to the semiconductor substrate, and allowing for the electric charges stored in the box layer to flow through the semiconductor substrate prevents destruction of the box layer. ([0004-0007], [00[0171]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to incorporate an additional active region embedded in the bottom die and connected to the bottom seal ring in the first seal ring region;
wherein the additional active region is configured to provide an electrical path to discharge charges formed in the interface during wafer stacking, in the device of Ho, according to the teachings of Uchida, with the motivation of allowing for the electric charges stored in a buried insulating layer to flow through the semiconductor substrate preventing destruction of the buried layer and suppressing propagation of noise.
Ho in view of Uchida shows, in claim 22, further comprising:
a first plurality of bottom hybrid bonding metal pads (HBMPs) disposed in the first bonding layer in the first seal ring region; (figure 6; [0047-0048], Ho) and
a first plurality of top HBMPs disposed in the second bonding layer in the second seal ring region, wherein the first plurality of top HBMPs are bonded to the first plurality of the bottom HBMPs, respectively (figure 6; [0047-0048], Ho).
Ho in view of Uchida shows, in claim 23, further comprising: a first plurality of bottom hybrid bonding vias (HBVs) disposed in the first bonding layer and respectively connecting the bottom HBMPs and the bottom seal ring (figure 6; [0047-0048], Ho); and
a first plurality of top HBVs disposed in the second bonding layer and respectively connecting the top HBMPs and the top seal ring (figure 6; [0047-0048], Ho).
Ho in view of Uchida shows, in claim 24, wherein the first active region and the second active region are vertically aligned, and wherein the first seal ring region and the second seal ring region are vertically aligned (figure 6; [0047-0048], Ho).
Ho in view of Uchida shows, in claim 26, wherein the bottom die comprises a substrate, and wherein the additional active region is embedded in the substrate and is connected to the bottom seal ring at a front surface of the substrate (figure 1; [0081-0085], [0093-0095], [0107-0109], Uchida).
The rejection of claim(s) 7 under 35 U.S.C. 103 as being unpatentable over Ho et al. (US PGPub 2015/0194455, hereinafter referred to as “Ho”) in view of Uchida et al. (US PGPub 2018/0047680, hereinafter referred to as “Uchida”) as applied to claim 1 above, and further in view of Chang et al. (US PGPub 2022/0165664, hereinafter referred to as “Chang”) has been maintained for reasons of record.
Ho in view of Uchida discloses the semiconductor device substantially as claimed. See the rejection above.
However, Ho in view of Uchida fails to show, in claim 7, further comprising a (deep trench capacitor) DTC region embedded in the top die, the DTC region comprising an array of DTCs.
Chang teaches, in claim 7, a similar device that includes an integrated circuit component that is a deep trench capacitor (DTC) die (figure 8; [0040]). In addition, Chang provides the advantages of including passive devices to improve electrical performance of the electrical circuit and less power consumption ([0015]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to incorporate further comprising a (deep trench capacitor) DTC region embedded in the top die, the DTC region comprising an array of DTCs, in the device of Ho in view of Uchida, according to the teachings of Chang, with the motivation of improve electrical performance of the electrical circuit and enabling less power consumption in the top die.
Claim(s) 9 and 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ho et al. (US PGPub 2015/0194455, hereinafter referred to as “Ho”) in view of Uchida et al. (US PGPub 2018/0047680, hereinafter referred to as “Uchida”) as applied to claims 1 and 21 above, and further in view of Chen et al. (US PGPub 2020/0075435, hereinafter referred to as “Chen”).
Ho in view of Uchida discloses the semiconductor substantially as claimed. See the rejection above.
However, Ho in view of Uchida fails to show, in claim 9, further comprising a delamination monitoring structure (DMS) configured to monitor delamination in the first seal ring region and the second seal ring region.
Chen teaches, in claim 9, a similar package device that includes the use of a detecting device that determines cracks within the semiconductor device that indicate that the seal ring is damaged (figures 1-3; [0029]). In addition, Chen provides the advantages of improving detection of cracks, delamination, and other defects within the semiconductor device ([0017-0018]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to incorporate further comprising a delamination monitoring structure (DMS) configured to monitor delamination in the first seal ring region and the second seal ring region, in the device of Ho in view of Uchida, according to the teachings of Chen, with the motivation of improving detection of cracks, delamination, and other defects within the semiconductor device.
Ho in view of Uchida fails to show, in claim 25, further comprising a delamination monitoring structure (DMS) configured to monitor delamination in the first seal ring region and the second seal ring region.
Chen teaches, in claim 25, a similar package device that includes the use of a detecting device that determines cracks within the semiconductor device that indicate that the seal ring is damaged (figures 1-3; [0029]). In addition, Chen provides the advantages of improving detection of cracks, delamination, and other defects within the semiconductor device ([0017-0018]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to incorporate further comprising a delamination monitoring structure (DMS) configured to monitor delamination in the first seal ring region and the second seal ring region, in the device of Ho in view of Uchida, according to the teachings of Chen, with the motivation of improving detection of cracks, delamination, and other defects within the semiconductor device.
Allowable Subject Matter
Claims 15-20 are allowed over the prior art of record.
The following is an examiner’s statement of reasons for allowance: the closest prior art of record and to the examiner’s knowledge does not suggest or render obvious a package structure, particularly characterized by a delamination monitoring structure (DMS) comprising: a first through-substrate via; a second TSV; a first routing connection; and a second routing connection; wherein an electrical path passes through a portion of the continuous seal ring, and the portion of the continuous seal ring comprises a starting continuous seal ring pillar an dan ending continuous seal ring pillar and an ending continuous seal ring pillar electrically connected to the starting continuous seal ring pillar, and wherein the first TSV is electrically connected to the starting continuous seal ring pillar through the first routing connection, the second TSV is electrically connected to the ending continuous seal ring pillar through the second routing connection, and wherein, the DMS is configured to monitor delamination of the continuous seal ring by applying a voltage bias to the first TSV and the second TSV and measuring an electric current generated by the voltage bias, as detailed in claim 15. Claims 16-20 depend from claim 15.
The closest prior art of record, under 35 U.S.C. 103 as being unpatentable over Ho et al. (US PGPub 2015/0194455, hereinafter referred to as “Ho”) in view of Uchida et al. (US PGPub 2018/0047680, hereinafter referred to as “Uchida”) in further view of Chen et al. (US PGPub 2020/0075435, hereinafter referred to as “Chen”) teaches, a package structure comprising:
a bottom die (200) comprising:
a first active region surrounded by a first seal ring region (208);
a first seal ring region comprising a bottom seal ring (208A, 208B);
a first bonding layer (210) disposed on a front side of the bottom die;
a first plurality of bottom hybrid bonding metal pads (HBMPs) (614A2, 612B, 614B2) disposed in the first bonding layer (210) in the first seal ring region; and
a first plurality of bottom hybrid bonding via (HBVs) (614A2, 612B, 614B2) disposed in the first bonding layer and respectively connecting the bottom HBMPs (614A2, 612B, 614B2) and the bottom seal ring;
a top die (100) comprising:
a second active region surrounded by a second seal ring region (616);
a second seal ring region comprising a top seal ring (616A, 616B);
a second bonding layer (112) disposed on a front side of the top die (100);
a first plurality of top HBMPs (614A1, 612A, 614B1) disposed in the second bonding layer in the second seal ring region, wherein the first plurality of top HBMPs (614A1, 612A, 614B1) are bonded to the first plurality of the bottom HBMPs (614A2, 612B, 614B2), respectively; and
a first plurality top HBV (614A1, 612A, 614B1) disposed in the second bonding layer (112) and respectively connecting the top HBMPs (614A1, 612A, 614B1) and the top seal ring (616A, 616B);
wherein the bottom die (200) and the top die (100) are bonded through hybrid bonding ([0048]) between the first bonding layer (210) and the second bonding layer (112) at an interface therebetween such that the bottom seal ring (208A, 208B) and the top seal ring (616A, 616B) are vertically aligned, and wherein the bottom seal ring (208A, 208B), the bottom HBV (614A2, 612B, 614B2), the bottom HBMP (614A2, 612B, 614B2), the top HBMP (614A1, 612A, 614B1), the top HBV (614A1, 612A, 614B1), and the top seal ring (616A, 616B) [form a continuous seal ring] such that the bottom seal ring (208A, 208B) and the top seal ring (616A, 616B) are electrically connected across the interface (figure 6; [0047-0048]).
However, Ho fails to teach, an additional active region embedded in the bottom die and connected to the bottom seal ring in the first seal ring region.
Uchida teaches, implanting ions of a p-type impurity and n-type impurity into the semiconductor substrate in the seal ring region SR (figure 1; [0081-0085], [0093-0095], [0107-0109]). In addition, Uchida provides the advantages of improving moisture resistance, preventing chipping of the semiconductor device, suppressing propagation of noise through the seal ring to the semiconductor substrate, and allowing for the electric charges stored in the box layer to flow through the semiconductor substrate prevents destruction of the box layer ([0004-0007], [00[0171]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to incorporate an additional active region embedded in the bottom die and connected to the bottom seal ring in the first seal ring region, in the device of Ho, according to the teachings of Uchida, with the motivation of allowing for the electric charges stored in a buried insulating layer to flow through the semiconductor substrate preventing destruction of the buried layer and suppressing propagation of noise.
Ho in view of Uchida fails to teach, a delamination monitoring structure (DMS).
However, Chen teaches, a similar package device that includes the use of a detecting device that determines cracks within the semiconductor device that indicate that the seal ring is damaged (figures 1-3; [0029]). In addition, Chen provides the advantages of improving detection of cracks, delamination, and other defects within the semiconductor device ([0017-0018]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to incorporate a delamination monitoring structure (DMS), in the device of Ho in view of Uchida, according to the teachings of Chen, with the motivation of improving detection of cracks, delamination, and other defects within the semiconductor device.
However, the prior art of record fails to teach the above claimed invention.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Response to Arguments
Applicant's arguments filed 6/29/26, regarding claims 1-7, 9 and 21-26 have been fully considered but they are not persuasive. Applicant raises the clear issue as to whether Ho alone or in combination with Uchida, Chang, and Chen, suggests an additional active region embedded in the bottom die and connected to the bottom seal ring in the first seal ring region; and wherein the additional active region is configured to provide an electrical path to discharge charges from in the interface during wafer stacking.
The examiner views that based on the combined teachings of Ho in view of Uchida the above limitations and or statements are taught. Specifically, Ho teaches die to die level bonding (See [0029]) and that the seal ring in the first region is continuous and connected to the bottom die (figure 6; [0048]). Ho only fails to explicitly teach an additional active region embedded in the bottom die and connected to the bottom seal ring in the first seal ring region; wherein the additional active region is configured to provide an electrical path to discharge charges formed in the interface during wafer stacking. Therefore, Uchida provides advantages to implanting ions of a p-type impurity and n-type impurity into the semiconductor substrate in the seal ring region SR (figure 1; [0081-0085], [0093-0095], [0107-0109]), for the purpose of improving moisture resistance, preventing chipping of the semiconductor device, suppressing propagation of noise through the seal ring to the semiconductor substrate, and allowing for the electric charges stored in the box layer to flow through the semiconductor substrate prevents destruction of the box layer. ([0004-0007], [0171]).
In response to applicant's argument that the examiner's conclusion of obviousness is based upon improper hindsight reasoning, it must be recognized that any judgment on obviousness is in a sense necessarily a reconstruction based upon hindsight reasoning. But so long as it takes into account only knowledge which was within the level of ordinary skill at the time the claimed invention was made, and does not include knowledge gleaned only from the applicant's disclosure, such a reconstruction is proper. See In re McLaughlin, 443 F.2d 1392, 170 USPQ 209 (CCPA 1971).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STANETTA D ISAAC whose telephone number is (571)272-1671. The examiner can normally be reached M-F 10-6.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at 571-270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/STANETTA D ISAAC/Examiner, Art Unit 2898 September 5, 2026
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
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