DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on January 27 2026 has been entered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 9-10, 14-15, and 17-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al. (“Lin” US Patent No. 9,679,878).
Regarding claim 9, Lin discloses a package comprising:
a first semiconductor die (22);
a second semiconductor die (42) disposed to a side of the first semiconductor die (22, see Figure 34);
a first dielectric fill material layer (56) embedding the first semiconductor die (22) and the second semiconductor die (42);
a first connector clip (64, left portion connected to leftmost pad 28/30) having a segment overlaying a first portion of a top surface of the first dielectric fill material layer (56, see Figure 34);
a second connector clip (64, right portion connected to rightmost pad 28/30) having a segment overlaying a second portion of the top surface of the first dielectric fill material layer (56, see Figure 34), wherein the second connector clip (64, right portion) connects a gate contact pad (28/30, right portion of first die 22, see Figure 2) of the first semiconductor die (22) exposed through the first dielectric fill material layer (56) to a first signal contact pad (160) on a top surface of the second semiconductor die (42, Figure 34 shows the signal contacts 160 on the semiconductor die 42 on the lower surface, however Lin discloses in col. 7, lines 16-18 that the “third die” 42 can be flipped and coupled with the electrically conductive elements 12 using wire bonds, see electrically conductive elements 12 labeled in Figure 1, which are connected to the second connector clip, 64, right portion, thus the connector clip connects a gate contact pad of the first die to the first signal contact pad 160 on a top surface of the second die 42);
a third semiconductor die (32) disposed on the segment of the first connector clip (64, left portion) overlaying the first portion of the first dielectric fill material layer (56, see Figure 34); and
a second dielectric fill material layer (66) overlaying and in direct physical contact with the first dielectric fill material layer (56, see Figure 34) and embedding the third semiconductor die (32, see Figure 34).
Regarding claim 10, Lin discloses wherein the first connector clip (64, left portion) and the second connector clip (64, right portion) are plated connector clips (see co. 8, lines 4-9, the “first RDL” 64 may be formed using a plating method).
Regarding claim 14, Lin further discloses a third connector clip (80, left portion) connecting a source pad (col. 7, lines 25-31 discloses that the “second die” 32 has two contacts on one side, and one contact on the other, which is a common configuration of a FET that has source and gate on one side and the drain contact on the other) of the third semiconductor die (32) to a second connector pad (152 of 144, see Figure 33 and 34) external to the first dielectric fill material layer (50) and the second dielectric fill material layer (66, see Figure 34).
Regarding claim 15, Lin further discloses a fourth connector clip (80, right portion) connecting a gate contact pad (36, right side) of the third semiconductor die (32) to a second signal contact pad (160, rightmost) on a top surface (see col. 7, lines 16-18, where contacts are on the top surface of die 42) of the second semiconductor die (42, see Figure 34).
Regarding claim 17, Lin discloses wherein at least one of a gate contact pad (28/30, right side) of the first semiconductor die (22), or a first signal contact pad (48, leftmost) and a second signal contact pad (48, rightmost) of the second semiconductor die (42) are exposed through the first dielectric fill material (50) layer by vias (see metal layers 18) through the first dielectric fill material layer (50), and wherein at least one of a gate contact pad (36, right side) of the third semiconductor die (32) or the second signal contact pad (48, rightmost) of second semiconductor die (42) are exposed through the second dielectric fill material layer (66) by vias through the second dielectric fill material layer (66, see vias in 66 exposing the contacts through the second dielectric layer).
Regarding claim 18, Lin further discloses a molding material (82) encapsulating components of the package (see Figure 34).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-5, 7 and 25-32 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (“Lin” US Patent No. 9,679,878) and Ohguro (US 2023/0290757).
Regarding claim 1, Lin discloses a package (Figure 34) comprising:
a dielectric fill material layer (mold compound 56) embedding a first semiconductor die (22, See Figure 34);
a connector clip (64) having a segment disposed above and in physical contact with a top surface of the dielectric fill material layer (56, see Figure 34), the segment being aligned along a same direction as a top surface of the first semiconductor die (22, the segment of the clip 64 extends horizontally, which is parallel with the top surface of the first semiconductor die 22); and
a second semiconductor die (32) bonded directly to the segment of the connector clip (64) disposed above and in physical contact with the dielectric fill material layer (56, see Figure 34).
Lin does not explicitly disclose a connector pad external and lateral to the dielectric fill material layer, the connector pad having a bottom surface coplanar with a bottom surface of the dielectric fill material layer, and the connector clip electrically coupling the first semiconductor die to the connector pad.
Ohguro discloses, however, a connector pad (120, see Figure 4) external and lateral to the dielectric fill material layer (here the dielectric fill material layer is considered to be the portion of the resin member 190 that is immediately surrounding the first semiconductor die 140, see labeled below in annotated Figure 4 of Ohguro), the connector pad (120) having a bottom surface coplanar with a bottom surface of the dielectric fill material layer (portion of 190, see Figure 4), and the connector clip (160) electrically coupling the first semiconductor die (140) to the connector pad (120, see Figure 4).
All of the claimed elements were known in the prior art before the effective filing date of the present invention, and the combination would have resulted in the predictable result to one having ordinary skill in the art of providing electrical connection to the first semiconductor die from a source external to the semiconductor package. Thus, it would have been obvious to one having ordinary skill in the art to incorporate the teachings of Ohguro above into the teachings of Lin. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Regarding claim 3, Lin discloses wherein a source pad (30, left side) and a gate contact pad (30, right side) of the first semiconductor die (22, these are considered the source and gate contact pad because the semiconductor die 22 has a source, gate, and drain, one of which is coupled to the horizontal member 14/12, see col. 6, lines 56-67) are exposed through the dielectric fill material layer (56).
Lin does not disclose that and the connector clip connects the source pad of the first semiconductor die to the connector pad.
Ohguro discloses, however, that the connector clip (160) connects the source pad (source electrode 142, para. [0044]) of the first semiconductor die (140) to the connector pad (120, see Figure 4).
Regarding claim 4, the combination of Lin and Ohguro discloses wherein the connector clip (64) is a first connector clip (64) and the connector pad (120 of Ohguro, incorporated into the teachings of Lin) is a first connector pad (120), the package further comprising a second connector clip (80) connecting a source pad (38, left portion, shown in Figure 7) of the second semiconductor die (32) to a second connector pad external [and lateral to] the dielectric fill material layer (col. 8, lines 58-67 discloses that the connector clip “second RDL” may couple the source pad “leftmost upper contact of the second die” with an element external to the package).
Lin does not explicitly disclose that the second connector pad is lateral to the dielectric fill material layer.
Ohguro discloses, however, a second connector clip (170) connected to a second connector pad (110) lateral to the dielectric fill material layer (see Figure 5, which shows a portion of the dielectric fill material layer on the lower left corner of Figure 5, to which the second connector pad 110 is lateral).
All of the claimed elements were known in the prior art before the effective filing date of the present invention, and the combination would have resulted in the predictable result to one having ordinary skill in the art of providing electrical connection to the first semiconductor die from a source external and lateral to the semiconductor package, which is a known disposition of means for external connection as evidenced by Ohguro. Thus, it would have been obvious to one having ordinary skill in the art to incorporate the teachings of Ohguro above into the teachings of Lin. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Regarding claim 5, Lin further discloses an integrated circuit (IC) controller chip (42, a driver chip controls gates of other FETs in the package) disposed on the dielectric fill material layer (56, see Figure 34).
Regarding claim 7, Lin does not disclose a molding material at least partially encapsulating the dielectric fill material layer, the connector clip, the second semiconductor die, and the connector pad, wherein the bottom surface of the connector pad is exposed through the molding material.
Ohguro discloses, however, a molding material (outer edge portions of resin member 190, see labeled below) at least partially encapsulating the dielectric fill material layer (inner portions of 190 immediately surrounding die 140), the connector clip (160), the second semiconductor die (150), and the connector pad (120), wherein the bottom surface of the connector pad (120) is exposed through the molding material (outer portions of 190, see Figure 4).
It would have been obvious to one having ordinary skill in the art to incorporate the teachings of Ohguro above into the teachings of Lin for the purpose of sealing the semiconductor chips, which provides protection to the devices, while also allowing the “substrate” 110 and “leads” 120/130 to be exposed from the package to facilitate external connection (Ohguro, para. [0055]).
Regarding claim 25, Lin discloses a package comprising:
a first semiconductor die (22) disposed on a top surface of a substrate (6, see Figure 34);
a first dielectric fill material layer (50) embedding the first semiconductor die (22), the first dielectric fill material layer (50) disposed on a portion of the top surface of the substrate (6, see Figure 34);
a first connector clip (64, left portion) having a bottom surface disposed on the first dielectric fill material layer (50, see Figure 34);
a second semiconductor die (32) bonded directly to a top surface of the first connector clip (64, vertical portion) above the first semiconductor die (22, see Figure 34); and
a second connector clip (76) connecting a source pad (36, left) of the second semiconductor die (32) to a second connector pad (80) on the top surface of the substrate (6, see Figure 34).
Lin does not disclose the first connector clip connecting a source pad of the first semiconductor die and a first connector pad disposed on and in direct contact with the top surface of the substrate, wherein the first connector pad is external to the first dielectric fill material layer.
Ohguro discloses, however, a first connector clip (160) connecting a source pad (source electrode 142, see para. [0044]) of the first semiconductor die (140) and a first connector pad (120c) disposed on and in direct contact with the top surface of the substrate (120, see Figure 4), wherein the first connector pad (120c) is external to the first dielectric fill material layer (portion of resin member 190 immediately surrounding the first semiconductor die 140, see Figure 4 and annotated Figure 4 of Ohguro below.
All of the claimed elements were known in the prior art before the effective filing date of the present invention, and the combination would have resulted in the predictable result to one having ordinary skill in the art of providing electrical connection to the first semiconductor die from a source external to the semiconductor package. Thus, it would have been obvious to one having ordinary skill in the art to incorporate the teachings of Ohguro above into the teachings of Lin. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Regarding claim 26, Lin further discloses a first dam structure (portions of 50 that extend vertically and surround the first die 22, labeled below) surrounding the first semiconductor die (22);
a second dam structure (portions of 50 that extend vertically and surround the first die’s source pad 28/30, left, labeled below) surrounding a source pad (28/30, left) of the first semiconductor die (22); and
a third dam structure (portions of 50 that extend vertically and surround the first die’s gate pad, labeled below) surrounding a gate contact pad (28/30, right) of the first semiconductor die (22),
the first dielectric fill material layer (50) being disposed in the first dam structure, the second dam structure, and the third dam structure to embed the first semiconductor die (22, see Figure 34).
Regarding claim 27, Lin further discloses a fourth dam structure (portions of 66 that extend vertically and surround the second die 32, labeled below) surrounding the second semiconductor die (32), the fourth dam structure including a second dielectric fill material layer (66) embedding the second semiconductor die (32, see Figure 34).
Regarding claim 28, Lin discloses a third connector clip (76) connecting a source pad (36, left) of the second semiconductor die (32) to a second connector pad (80) on the top surface of the substrate (6, see Figure 34).
Regarding claim 29, Lin discloses wherein the third connector clip (76) is a plating (76 may be formed using the same method as the first pillars, which is a plating method, see col. 8, lines 46-50 and col. 7, lines 59-65).
Regarding claim 30, Lin further discloses a mold body (82) encapsulating at least the substrate (6), the first semiconductor die (22), the second semiconductor die (32), and the first dielectric fill material layer (50, see Figure 34, the mold body 82 is a top layer of the package, encapsulating the entire package).
Regarding claim 31, the combination of Lin and Ohguro discloses wherein the segment (of clip 64 of Lin, modified by clip 160 in Ohguro) is a first segment (161 segment/portion of the connector clip 160, see Figure 4), the connector clip (160) including a second segment (162) external to the dielectric fill material layer (see Figure 4 and annotated Figure 4, which shows the segment 162 external to the dielectric fill material layer portion of resin member 190), the second segment (162) extending between the first segment (161) and the connector pad (120, see Figure 4), wherein a portion of the molding material (remaining outer portions of resin member 190) is disposed between the second segment (162) and the dielectric fill material layer (portion of resin member 190 immediately surrounding the first die 140, see annotated Figure 4 below which shows a portion of the molding material being between the segment 162 and the dielectric fill material portion of 190).
Regarding claim 32, Ohguro discloses wherein the first semiconductor die (140) is disposed on a top surface of a landing pad (141c, see Figure 4), and wherein a bottom surface of the landing pad (141c) is exposed through the molding material (outer portions of 190, see Figure 4).
it would have been obvious to one having ordinary skill in the art to incorporate the teachings of Ohguro above into the teachings of Lin for the purpose of allowing the “substrate” 110 to be exposed from the package to facilitate external connection to the first semiconductor die (Ohguro, para. [0055]).
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Claim 8 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Lin and Ohguro as applied to claim 1 and over Lin applied to claim 9 above, respectively, and further in view of Tang et al. (“Tang” US 2022/0037280) and Hosseini et al. (“Hosseini” US Patent No. 9,070,568).
Regarding claim 8, Tang discloses a thin-film redistribution layer (RDL) component (passive component 141) disposed in the dielectric fill material layer (158, see Figure 1B).
It would have been obvious to one having ordinary skill in the art to incorporate the teachings of Tang into the teachings of Lin and Ohguro in the manner above for the purpose of implementing a higher density of integrated devices in a device as evidenced by Hosseini (Hosseini, col. 6, lines 36-63).
Regarding claim 16, Tang discloses a thin-film redistribution layer (RDL) component (passive component 140) disposed on the segment of the second connector clip (120) and embedded in the second dielectric fill material layer (128/158, see Figure 1B).
It would have been obvious to one having ordinary skill in the art to incorporate the teachings of Tang into the teachings of Lin in the manner above for the purpose of implementing a higher density of integrated devices in a device as evidenced by Hosseini (Hosseini, col. 6, lines 36-63).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Lin as applied to claim 9 above, and further in view of Ohguro (US 2023/0290757).
Regarding claim 11, Ohguro discloses wherein the first connector clip (160, Figure 4) connects a source pad (source electrode 142, para. [0044]) of the first semiconductor die (140) exposed through the first dielectric fill material layer (portion of 190 immediately surrounding the first die 140, see labeled below in annotated Figure 4 of Ohguro) to a first connector pad (120) external to the first dielectric fill material layer (portion of 190, see Figure 4 and annotated Figure 4 of Ohguro).
All of the claimed elements were known in the prior art before the effective filing date of the present invention, and the combination would have resulted in the predictable result to one having ordinary skill in the art of providing electrical connection to the first semiconductor die from a source external to the semiconductor package. Thus, it would have been obvious to one having ordinary skill in the art to incorporate the teachings of Ohguro above into the teachings of Lin. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
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Claim 33 is rejected under 35 U.S.C. 103 as being unpatentable over Lin as applied to claim 15 above, and further in view of Mahler et al. (“Mahler” US 2013/0256856).
Mahler discloses in Figure 2B a fifth connector clip (133) connecting a third signal contact pad (control contact pad 12, para. [0036]) on the top surface of the second semiconductor die (121) to a second connector pad (142) external and lateral to the first dielectric fill material layer (here the first dielectric fill material layer is the portion of the insulating material 152 immediately surrounding the IC chips 111/121, outside of and lateral to the second connector pad 142 is disposed), the fifth connector clip (133) having a segment overlaying and in direct contact with the first dielectric fill material layer (SEE Figure 2B, and annotated Figure 2B below which shows the boundaries of the dielectric fill material layer, the top surface of which the segment overlays and directly contacts).
All of the claimed elements were known in the prior art before the effective filing date of the present invention, and the combination would have resulted in the predictable result to one having ordinary skill in the art of providing electrical connection to the claimed second semiconductor die from a source external to the semiconductor package. Thus, it would have been obvious to one having ordinary skill in the art to incorporate the teachings of Maher above into the teachings of Lin. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Additionally, the connector pad provides heat dissipation to the package (Maher, para. [0061]).
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Response to Arguments
Applicant’s arguments filed January 27 2206 with respect to the prior art rejections have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant's amendments regarding the objections to claims 1, 2, and 9 overcome the objections. Claim 2 has been cancelled. Thus the objections to claims 1 and 9 are withdrawn.
Applicant’s amendments regarding the 112 rejections of claims 2, 13, and 17 overcome the 112 rejection. Claim 2 has been cancelled. Thus the 112 rejections of claims 13 and 17 are withdrawn.
Conclusion
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/Genevieve G Bullard-Connor/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899