DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 25 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 25 requires the limitations “a second connector clip connecting a source pad of the second semiconductor die to a second connector pad on the top surface of the substrate; and a third connector clip connecting a source pad of the second semiconductor die to a second connector pad disposed on and in direct contact with the top surface of the substrate.”
This limitation requires two connector clips, the second and third connector clips, both connecting a source pad of the second semiconductor die to second connector pads, presumably one second connector pad on the top surface of the substrate, and the other second connector pad on and in direct contact with the top surface of the substrate (or the twice recited second connector pads are intended to be the same connector pad, it is unclear). The second semiconductor die is believed to be the semiconductor die 120 in present application’s Figure 3C and the clip connected to the source pad of the semiconductor die 120 to be element 170. However, the disclosure does not contemplate or show in the figures another clip connecting the same source pad of the semiconductor die 120 to another or the same connector pad 102c on the substrate. The disclosure only supports the presence of one connector clip connecting the pad 102c and the source pad of the semiconductor die 120. Thus, Applicant has introduced new matter to the claims.
Claims depending from the rejected claims noted above are rejected at least on the same basis as the claim(s) from which the dependent claims depend.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 25 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 25 requires the limitations “a second connector clip connecting a source pad of the second semiconductor die to a second connector pad on the top surface of the substrate; and a third connector clip connecting a source pad of the second semiconductor die to a second connector pad disposed on and in direct contact with the top surface of the substrate.”
It is unclear if the recited second connector pads are intended to be the same or different connector pads, given they are both preceded by an “a”, indicating a new element is being recited, have different requirements for the disposition with respect to the substrate, and are connected to different connector clips. For examination purposes, the Examiner will interpret the recited second connector pads to be different elements.
Claims depending from the rejected claims noted above are rejected at least on the same basis as the claim(s) from which the dependent claims depend.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 9-10, 14-15, and 17-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al. (“Lin” US Patent No. 9,679,878).
Regarding claim 9, Lin discloses a package comprising:
a first semiconductor die (22);
a second semiconductor die (42) disposed to a side of the first semiconductor die (22, see Figure 34);
a first dielectric fill material layer (56) embedding the first semiconductor die (22) and the second semiconductor die (42);
a first connector clip (64, left portion connected to leftmost pad 28/30) having a segment overlaying a first portion of a top surface of the first dielectric fill material layer (56, see Figure 34);
a second connector clip (64, right portion connected to rightmost pad 28/30) having a segment overlaying a second portion of the top surface of the first dielectric fill material layer (56, see Figure 34), wherein the second connector clip (64, right portion) directly contacts a gate contact pad (28/30, right portion of first die 22, see Figure 2 and Figure 34 showing direct physical and electrical contact) of the first semiconductor die (22) exposed through the first dielectric fill material layer (56) and directly contacts a first signal contact pad (160, directly electrical connection is made through electrically conductive elements 12, labeled in Figure 1) on a top surface of the second semiconductor die (42, Figure 34 shows the signal contacts 160 on the semiconductor die 42 on the lower surface, however Lin discloses in col. 7, lines 16-18 that the “third die” 42 can be flipped and coupled with the electrically conductive elements 12 using wire bonds, see electrically conductive elements 12 labeled in Figure 1, which are connected to the second connector clip, 64, right portion, thus the connector clip directly electrically and directly physically contacts a gate contact pad of the first die and directly electrically contacts the first signal contact pad 160 on a top surface of the second die 42 through the conductive elements 12);
a third semiconductor die (32) disposed on the segment of the first connector clip (64, left portion) overlaying the first portion of the first dielectric fill material layer (56, see Figure 34); and
a second dielectric fill material layer (66) overlaying and in direct physical contact with the first dielectric fill material layer (56, see Figure 34) and embedding the third semiconductor die (32, see Figure 34).
Regarding claim 10, Lin discloses wherein the first connector clip (64, left portion) and the second connector clip (64, right portion) are plated connector clips (see col. 8, lines 4-9, the “first RDL” 64 may be formed using a plating method).
Regarding claim 14, Lin further discloses a third connector clip (80, left portion) connecting a source pad (col. 7, lines 25-31 discloses that the “second die” 32 has two contacts on one side, and one contact on the other, which is a common configuration of a FET that has source and gate on one side and the drain contact on the other) of the third semiconductor die (32) to a second connector pad (152 of 144, see Figure 33 and 34) external to the first dielectric fill material layer (50) and the second dielectric fill material layer (66, see Figure 34).
Regarding claim 15, Lin further discloses a fourth connector clip (80, right portion) connecting a gate contact pad (36, right side) of the third semiconductor die (32) to a second signal contact pad (160, rightmost) on a top surface (see col. 7, lines 16-18, where contacts are on the top surface of die 42) of the second semiconductor die (42, see Figure 34).
Regarding claim 17, Lin discloses wherein at least one of a gate contact pad (28/30, right side) of the first semiconductor die (22), or a first signal contact pad (48, leftmost) and a second signal contact pad (48, rightmost) of the second semiconductor die (42) are exposed through the first dielectric fill material (50) layer by vias (see metal layers 18) through the first dielectric fill material layer (50), and wherein at least one of a gate contact pad (36, right side) of the third semiconductor die (32) or the second signal contact pad (48, rightmost) of second semiconductor die (42) are exposed through the second dielectric fill material layer (66) by vias through the second dielectric fill material layer (66, see vias in 66 exposing the contacts through the second dielectric layer).
Regarding claim 18, Lin further discloses a molding material (82) encapsulating components of the package (see Figure 34).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Lin applied to claim 9 above and further in view of Tang et al. (“Tang” US 2022/0037280) and Hosseini et al. (“Hosseini” US Patent No. 9,070,568).
Regarding claim 16, Tang discloses a thin-film redistribution layer (RDL) component (passive component 140) disposed on the segment of the second connector clip (120) and embedded in the second dielectric fill material layer (128/158, see Figure 1B).
It would have been obvious to one having ordinary skill in the art to incorporate the teachings of Tang into the teachings of Lin in the manner above for the purpose of implementing a higher density of integrated devices in a device as evidenced by Hosseini (Hosseini, col. 6, lines 36-63).
Claims 11 and 34-35 are rejected under 35 U.S.C. 103 as being unpatentable over Lin as applied to claim 9 above, and further in view of Tonedachi et al. (“Tonedachi” US 2017/0154834).
Regarding claim 11, Tonedachi discloses wherein the first connector clip (8 in Figure 2A, bottom left clip 8 in Figure 1) connects a pad (5 on top surface of IGBT 63, bottom left 63 in Figure 1) of the first semiconductor die (63, bottom left in Figure 1) exposed through the first dielectric fill material layer (sealing material 68 plus portion of resin, not illustrated, immediately surrounding the material 68, see labeled below in annotated Figure 2A of Tonedachi) to a first connector pad (5 on top surface of element 43) external to the first dielectric fill material layer (sealing material 68 plus portion of resin, not illustrated, immediately surrounding the material 68, see annotated Figure 2A).
All of the claimed elements were known in the prior art before the effective filing date of the present invention, and the combination would have resulted in the predictable result to one having ordinary skill in the art of providing electrical connection to the first semiconductor die from a source external to the semiconductor package, as well as incorporating a large, thermally conductive clip with greater surface area for heat dissipation (Tonedachi, para. [0057]). Thus, it would have been obvious to one having ordinary skill in the art to incorporate the clip structure of Tonedachi above into the teachings of Lin. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Regarding claim 34, Lin does not disclose a fifth connector clip connecting a third signal contact pad on the top surface of the second semiconductor die to a second connector pad external to the first dielectric fill material layer, wherein respective bottom surfaces of the first connector pad and the second connector pad are coplanar with a bottom surface of the first dielectric fill material layer.
Tonedachi discloses a fifth connector clip (8 in Figure 2A, top left clip 8 in Figure 1) connecting a contact pad (5 on IGBT 63, top left in Figure 1) on the top surface of the second semiconductor die (IGBT 63, top left in Figure 1) to a second connector pad (5 on top surface of element 43 in Figure 2A, of the top left module in Figure 1) external to the first dielectric fill material layer (sealing material 68 plus portion of resin, not illustrated, immediately surrounding the material 68, see labeled below in annotated Figure 2A of Tonedachi), wherein respective bottom surfaces of the first connector pad and the second connector pad (43 of each module on the far left of Figure 1 are on the same plane) are coplanar with a bottom surface of the first dielectric fill material layer (see annotated Figure 2A).
All of the claimed elements were known in the prior art before the effective filing date of the present invention, and the combination would have resulted in the predictable result to one having ordinary skill in the art of providing electrical connection to the second semiconductor die from a source external to the semiconductor package, as well as incorporating a large, thermally conductive clip with greater surface area for heat dissipation (Tonedachi, para. [0057]). Thus, it would have been obvious to one having ordinary skill in the art to incorporate the clip structure of Tonedachi above into the teachings of Lin. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
PNG
media_image1.png
466
895
media_image1.png
Greyscale
Regarding claim 35, the combination of Lin and Tonedachi discloses wherein the first connector pad and the second connector pad (43 of each far left module shown in Tonedachi’s Figure 1) are surrounded laterally by a molding material (resin material, not illustrated, surrounding the labeled dielectric fill material layer below) that encapsulates the first dielectric fill material layer and the second dielectric fill material layer (as taught by Lin), the respective bottom surfaces being exposed through the molding material (exposed through the molding material through element 43, onto the substrate 7).
It would have been obvious to incorporate the teachings of Tonedachi into Lin to include the molding material and the relative dispositions of the connector pads for the purpose of sealing the elements on the substrate (Tonedachi, para. [0024]) for protection from the external environment while also allowing for electrical connection to sources external the sealing/molding material (i.e. having surfaces of the connector pads exposed, in order to electrically connect to other sources).
PNG
media_image2.png
378
408
media_image2.png
Greyscale
Claim 33 is rejected under 35 U.S.C. 103 as being unpatentable over Lin as applied to claim 15 above, and further in view of Mahler et al. (“Mahler” US 2013/0256856).
Mahler discloses in Figure 2B a fifth connector clip (133) connecting a third signal contact pad (control contact pad 12, para. [0036]) on the top surface of the second semiconductor die (121) to a second connector pad (142) external and lateral to the first dielectric fill material layer (here the first dielectric fill material layer is the portion of the insulating material 152 immediately surrounding the IC chips 111/121, outside of and lateral to the second connector pad 142 is disposed), the fifth connector clip (133) having a segment overlaying and in direct contact with the first dielectric fill material layer (see Figure 2B, and annotated Figure 2B below which shows the boundaries of the dielectric fill material layer, the top surface of which the segment overlays and directly contacts).
All of the claimed elements were known in the prior art before the effective filing date of the present invention, and the combination would have resulted in the predictable result to one having ordinary skill in the art of providing electrical connection to the claimed second semiconductor die from a source external to the semiconductor package. Thus, it would have been obvious to one having ordinary skill in the art to incorporate the teachings of Mahler above into the teachings of Lin. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Additionally, the connector pad provides heat dissipation to the package (Mahler, para. [0061]).
PNG
media_image3.png
295
680
media_image3.png
Greyscale
Claims 1, 3-5, and 31-32 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (“Lin” US Patent No. 9,679,878) and Tonedachi et al. (“Tonedachi” US 2017/0154834).
Regarding claim 1, Lin discloses a package (Figure 34) comprising:
a dielectric fill material layer (mold compound 56) embedding a first semiconductor die (22, See Figure 34);
a connector clip (64) having a segment disposed above and in physical contact with a top surface of the dielectric fill material layer (56, see Figure 34), the segment being aligned along a same direction as a top surface of the first semiconductor die (22, the segment of the clip 64 extends horizontally, which is parallel with the top surface of the first semiconductor die 22); and
a second semiconductor die (32) bonded directly to the segment of the connector clip (64) disposed above and in physical contact with the dielectric fill material layer (56, see Figure 34).
Lin does not explicitly disclose a connector pad external and lateral to the dielectric fill material layer, the connector pad having a bottom surface coplanar with a bottom surface of the dielectric fill material layer, and the connector clip electrically coupling the first semiconductor die to the connector pad, and molding material at least partially encapsulating the dielectric fill material layer, the connector clip, the second semiconductor die, and the connector pad, wherein the connector pad is surrounded laterally by the molding material and has a bottom surface exposed through the molding material.
Tonedachi discloses a clip structure with a connector clip (8) and connector pad (5) external and lateral to the dielectric fill material layer (68 plus resin, not illustrated, immediately surrounding the sealing resin 68, see Figure 2A and para. [0024]), the connector pad (5) having a bottom surface coplanar with a bottom surface of the dielectric fill material layer (68 plus resin, the bottom surface of the dielectric fill material layer being the lower surface in direct physical contact with the top surface of element 41), and the connector clip (8) electrically coupling the first semiconductor die (63) to the connector pad (5), and molding material (remaining portions of the resin, not illustrated, outside of the dielectric fill material layer) at least partially encapsulating the dielectric fill material layer (68 plus resin, not illustrated, immediately surrounding the sealing resin 68) the connector clip (8), the second semiconductor die (69), and the connector pad (5), wherein the connector pad (5) is surrounded laterally by the molding material (resin, not illustrated) and has a bottom surface exposed through the molding material (Figure 2A shows the bottom surface of the pad 5 connected to the clip 8 would be exposed from the molding material, which is not illustrated, since it is in direct physical contact with the upper surface of element 43).
All of the claimed elements were known in the prior art before the effective filing date of the present invention, and the combination would have resulted in the predictable result to one having ordinary skill in the art of providing electrical connection to the first semiconductor die from a source external to the semiconductor package, as well as incorporating a large, thermally conductive clip with greater surface area for heat dissipation (Tonedachi, para. [0057]). Thus, it would have been obvious to one having ordinary skill in the art to incorporate the clip structure of Tonedachi above into the teachings of Lin. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Regarding claim 3, Lin discloses wherein a source pad (30, left side) and a gate contact pad (30, right side) of the first semiconductor die (22, these are considered the source and gate contact pad because the semiconductor die 22 has a source, gate, and drain, one of which is coupled to the horizontal member 14/12, see col. 6, lines 56-67) are exposed through the dielectric fill material layer (56).
Lin does not disclose that and the connector clip connects the source pad of the first semiconductor die to the connector pad.
Tonedachi discloses, however, that the connector clip (8) connects the pad (top terminal of IGBT 63) of the first semiconductor die (63) to the connector pad (5, see Figure 2A).
Regarding claim 4, the combination of Lin and Tonedachi discloses wherein the connector clip (64 of Lin, 8 of Tonedachi) is a first connector clip (64 Lin, 8 Tonedachi) and the connector pad (5, connected to clip 8 of Tonedachi, incorporated into the teachings of Lin) is a first connector pad (5), the package further comprising a second connector clip (80 of Lin) connecting a source pad (38, left portion, shown in Figure 7) of the second semiconductor die (32) to a second connector pad external [and lateral to] the dielectric fill material layer (col. 8, lines 58-67 discloses that the connector clip “second RDL” may couple the source pad “leftmost upper contact of the second die” with an element external to the package).
Lin does not explicitly disclose that the second connector pad is lateral to the dielectric fill material layer.
Tonedachi discloses, however, a second connector clip (8, on another semiconductor element in Figure 1) connected to a second connector pad (5, connected to clip 8 on another semiconductor element in Figure 1) lateral to the dielectric fill material layer (sealing resin 68 plus portion of resin, not illustrated, surrounding the sealing resin 68, see annotated Figure 2A below).
All of the claimed elements were known in the prior art before the effective filing date of the present invention, and the combination would have resulted in the predictable result to one having ordinary skill in the art of providing electrical connection to the first semiconductor die from a source external and lateral to the semiconductor package, which is a known disposition of means for external connection. Also, the clips (8) as disclosed by Tonedachi aid in heat dissipation (see claim 1 above) Thus, it would have been obvious to one having ordinary skill in the art to incorporate the teachings of Tonedachi above into the teachings of Lin. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Regarding claim 5, Lin further discloses an integrated circuit (IC) controller chip (42, a driver chip controls gates of other FETs in the package) disposed on the dielectric fill material layer (56, see Figure 34).
Regarding claim 31, the combination of Lin and Tonedachi discloses wherein the segment (of clip 64 of Lin, modified by clip structure 8/5 in Tonedachi) is a first segment (81), the connector clip (8) including a second segment (82) external to the dielectric fill material layer (see Figure 2A and annotated Figure 2A, which shows the segment 82 external to the dielectric fill material layer portion of resin), the second segment (82) extending between the first segment (81) and the connector pad (5, see Figure 2A), wherein a portion of the molding material (remaining outer portions of resin) is disposed between the second segment (82) and the dielectric fill material layer (68 plus portion of resin immediately surrounding element 68, see annotated Figure 2A below which shows a portion of the molding material being between the segment 82 and the dielectric fill material portion labeled).
Regarding claim 32, Tonedachi discloses wherein the first semiconductor die (63) is disposed on a top surface of a landing pad (61), and wherein a bottom surface of the landing pad (61) is exposed through the molding material (outer portions of resin, not illustrated, see annotated Figure 2A).
it would have been obvious to one having ordinary skill in the art to incorporate the teachings of Tonedachi above into the teachings of Lin for the purpose of radiating heat to the external environment (Tonedachi, para. [0073]).
PNG
media_image2.png
378
408
media_image2.png
Greyscale
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Lin and Tonedachi as applied to claim 1 above and further in view of Tang et al. (“Tang” US 2022/0037280) and Hosseini et al. (“Hosseini” US Patent No. 9,070,568).
Regarding claim 8, Tang discloses a thin-film redistribution layer (RDL) component (passive component 141) disposed in the dielectric fill material layer (158, see Figure 1B).
It would have been obvious to one having ordinary skill in the art to incorporate the teachings of Tang into the teachings of Lin and Tonedachi in the manner above for the purpose of implementing a higher density of integrated devices in a device as evidenced by Hosseini (Hosseini, col. 6, lines 36-63).
Claims 25, 27, and 29-30 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (“Lin” US Patent No. 9,679,878) and Ohguro (US 2023/0290757).
Regarding claim 25, Lin discloses a package comprising:
a first semiconductor die (22) disposed on a top surface of a substrate (6, see Figure 34);
a first dielectric fill material layer (50) embedding the first semiconductor die (22), the first dielectric fill material layer (50) disposed on a portion of the top surface of the substrate (6, see Figure 34);
a first connector clip (64, left portion) having a bottom surface disposed on the first dielectric fill material layer (50, see Figure 34);
a second semiconductor die (32) bonded directly to a top surface of the first connector clip (64, vertical portion) above the first semiconductor die (22, see Figure 34); and
a second connector clip (76) connecting a source pad (36, left) of the second semiconductor die (32) to a second connector pad (80) on the top surface of the substrate (6, see Figure 34); and
a third connector clip (76) connecting a source pad (36, left) of the second semiconductor die (32) to a second connector pad (80) on [and in direct contact with] the top surface of the substrate (6, see Figure 34).
Lin does not disclose the first connector clip connecting a source pad of the first semiconductor die and a first connector pad disposed on and in direct contact with the top surface of the substrate, wherein the first connector pad is external to the first dielectric fill material layer, that the second connector pad is in direct contact with the top surface of the substrate.
Ohguro discloses, however, a first connector clip (160) connecting a source pad (source electrode 142, see para. [0044]) of the first semiconductor die (140) and a first connector pad (120c) disposed on and in direct contact with the top surface of the substrate (110/120/130, see Figure 4), wherein the first connector pad (120c) is external to the first dielectric fill material layer (portion of resin member 190 immediately surrounding the first semiconductor die 140, see Figure 4 and annotated Figure 4 of Ohguro below), and
a third connector clip (170) connecting a pad of the second semiconductor die (150) to a second connector pad (110c) on and in direct contact with the top surface of the substrate (110/120/130, see Figure 4).
All of the claimed elements were known in the prior art before the effective filing date of the present invention, and the combination would have resulted in the predictable result to one having ordinary skill in the art of providing electrical connection to the first and second semiconductor dies from a source external to the semiconductor package. Thus, it would have been obvious to one having ordinary skill in the art to incorporate the teachings of Ohguro above into the teachings of Lin. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Regarding claim 27, Lin further discloses a fourth dam structure (portions of 66 that extend vertically and surround the second die 32, labeled below) surrounding the second semiconductor die (32), the fourth dam structure including a second dielectric fill material layer (66) embedding the second semiconductor die (32, see Figure 34).
Regarding claim 29, Lin discloses wherein the third connector clip (76) is a plating (76 may be formed using the same method as the first pillars, which is a plating method, see col. 8, lines 46-50 and col. 7, lines 59-65).
Regarding claim 30, Lin further discloses a mold body (82) encapsulating at least the substrate (6), the first semiconductor die (22), the second semiconductor die (32), and the first dielectric fill material layer (50, see Figure 34, the mold body 82 is a top layer of the package, encapsulating the entire package).
PNG
media_image4.png
510
975
media_image4.png
Greyscale
PNG
media_image5.png
528
728
media_image5.png
Greyscale
Claim 26 is rejected under 35 U.S.C. 103 as being unpatentable over Lin and Ohguro as applied to claim 25 above and further in view of Weinschenk (US 2014/0131899).
Regarding claim 26, Lin further discloses a first dam structure (portions of 50 that extend vertically and surround the first die 22, labeled below) surrounding the first semiconductor die (22);
a second dam structure (portions of 50 that extend vertically and surround the first die’s source pad 28/30, left, labeled below) surrounding a source pad (28/30, left) of the first semiconductor die (22); and
a third dam structure (portions of 50 that extend vertically and surround the first die’s gate pad, labeled below) surrounding a gate contact pad (28/30, right) of the first semiconductor die (22),
the first dielectric fill material layer (50) being disposed in the first dam structure, the second dam structure, and the third dam structure to embed the first semiconductor die (22, see Figure 34).
Lin does not explicitly disclose that the first, second, and third dam structures have a higher viscosity than a viscosity of the first dielectric fill material layer.
Weinschenk discloses, however, a conventional “dam and fill” technique (para. [0005]-[0006]), where the dam structures (see Figure 2) have a higher viscosity than the encapsulant material which is filled in the space enclosed by the dam structures (see para. [0005]).
It would have been obvious to a person having ordinary skill in the art to incorporate the teachings of Weinschenk into the teachings of Lin and Ohguro to employ this conventional dam and fill technique, where the dam structures have a higher viscosity than the encapsulant/dielectric fill material filled therein, since this is a known technique in the art and can be used in place of any other conventional encapsulation method.
Response to Arguments
Applicant’s arguments filed 17 June 2026 with respect to the prior art rejection of claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant’s arguments regarding claim 9 have been fully considered but are not persuasive. The interpretation of “directly contacts” can include direct physical contact and/or direct electrical contact since the claim does not specify which kind of direct contact is required.
Applicant’s arguments regarding claim 25 have been fully considered but are not persuasive. Ohguro discloses another, “third connector clip” as discussed with respect to claim 25 above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Genevieve G Bullard-Connor whose telephone number is (571)270-0609. The examiner can normally be reached Mon-Fri, 9am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 571-270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Genevieve G Bullard-Connor/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
Prosecution Insights