DETAILED ACTION
This Office action is in response to the Request for Continued Examination submitted on 09 June 2026. Claims 7-22 and 24-27 are pending in the application. Claim 27 is newly submitted. Claims 1-6 and 23 have been cancelled.
This application is a divisional of application Serial No. 16/887,219; filed on 29 May 2020; now US Patent 11,715,777.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 26 May 2026 has been entered.
Claim Rejections - 35 USC § 112
In light of the cancellation of claim 23, the rejection of claim 23 is rejected under 35 U.S.C. 112(b) has been withdrawn.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 14, 15, 21, 24, and 26 are rejected under 35 U.S.C. 102(a)(2) as being clearly anticipated by Hwang et al., US 2021/0104524, newly cited.
Hwang et al. disclose a method, shown in Figs. 11A, 15A, 16A, and 17A, comprising:
forming a multi-layer stack 111/112 on a semiconductor substrate 100/AP1, the multi-layer stack comprising a first semiconductor layer 111 on the semiconductor substrate and a second semiconductor layer 112 on the first semiconductor layer 111, see Fig. 11 A and paragraphs [0086]-[0087];
replacing the first semiconductor layer 111 with a gate structure GI/GE, see Fig. 15A and paragraphs [0100]-[0104];
forming a source/drain region SD1 in the semiconductor substrate 100/AP1 adjacent the gate structure GI/GE, see Fig. 15A and paragraph [0098];
etching the source/drain region SD1 to form a first recess RS1 extending to level with a bottom surface of the second semiconductor layer 112, wherein the second semiconductor layer 112 is a lowermost semiconductor layer of a channel region, see Fig. annotated 16A below and paragraph [0105]; and
forming a source/drain contact P1/P2 in the first recess, see Fig. 2A and paragraph [0106].
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With respect to claim 15, the method of Hwang et al. further comprises:
forming a dielectric layer 130 on the gate structure GI/GE and the source/drain region SD1, see Fig. 21 and paragraph [0111]; and etching the dielectric layer 130 to form a second recess TR4 exposing a top surface of the source/drain region SD1, wherein the source/drain contact P2 is formed in the second recess TR3, see Figs 16A and 3A.
With respect to claim 21, Hwang et al. disclose a method comprising:
forming a first channel region SP1 over a semiconductor substrate, wherein no other channel regions are between the first channel region SP1 and the semiconductor substrate 100/AP1, as shown in Fig. 15A;
forming a first gate stack GI/GE over the semiconductor substrate 100/AP1 and surrounding four sides of the first channel region SP1, as shown in Fig. 16A;
forming a first epitaxial source/drain region SD1 (see paragraph [0034] and [0098]) adjacent the first gate stack GI/GE and the first channel region SP1, as shown in Fig. 15A; and
forming a first source/drain contact P1/P2 coupled to the first epitaxial source/drain region SD1, see Fig. 3A,
a bottommost surface of the first source/drain contact P1/P2 extending below a topmost surface of the first channel region SP1, as shown in Fig. 3A.
With respect to claim 24, the method of Hwang et al. further comprises:
forming a first interlayer dielectric 110 over the first epitaxial source/drain region SD1, see Fig. 15A;
forming an opening TR3 in the first interlayer dielectric 110 to expose the first epitaxial source/drain region SD1; see 16A;
forming a spacer 130 along sidewalls of the opening, wherein forming the first source/drain contact P1/P2 comprises forming the first source/drain contact P1/P2 in the opening TR3 (see paragraph [0106]), wherein the spacer 130 separates the first source/drain contact P1/P2 from the first interlayer dielectric 110, as shown in Figs. 21 and 3A.
With respect to claim 26, in the method of Hwang et al., a bottommost surface of the first gate stack GI/GE extends below the bottommost surface of the first source/drain contact P1/P2, as shown in Fig. 16A and 3A.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 14-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al., US 2019/0074362, in view of Hwang et al., US 2021/0104524, newly cited
With respect to claim 14, Lee et al. disclose a method comprising:
forming a multi-layer stack 111/112 on a semiconductor substrate 100/100P, the multi-layer stack comprising a first layer 111 on the semiconductor substrate 100/100P and a second semiconductor layer 112 on the first layer 111, see Fig.15 and paragraphs [0131]-[0135];
replacing the first layer 111 with a gate structure 120, see Fig. 16 and paragraphs [0136]-[0140];
forming a source/drain region 150 in the semiconductor substrate 100/100P adjacent the gate structure 120, see Fig. 16 and paragraph [0141];
etching the source/drain region 150 to form a first recess extending to level with a bottom surface of the second semiconductor layer 112 (see Fig. 2), see Figs. 17-22 and paragraphs [0142]-[0155]; and
forming a source/drain contact 172 in the first recess, see Fig. 2.
Although Lee et al. disclose that the active pattern 112 may include a material having an etching selectivity to the sacrificial pattern 111, Lee et al. do not disclose that the multi-layer stack comprising a first semiconductor layer on the semiconductor substrate and a second semiconductor layer on the first semiconductor layer. However, in a similar method of fabricating a nano-sheet gate all-around transistor, shown in Figs. 11A, 15A, 16A18, and 18, Hwang et al .disclose forming a multi-layer stack 111/112 on a semiconductor substrate 100/AP1, the multi-layer stack comprising a first semiconductor layer 111 on the semiconductor substrate and a second semiconductor layer 112 on the first semiconductor layer 111, see Fig. 11 A and paragraphs [0086]-[0087] Hwang et al disclose that layers 111 may be formed of or include a material that is chosen to have an etch selectivity with respect to the semiconductor layers 112, and Hwang et al. disclose that layers 111 can comprise a semiconductor, such as SiGe or Ge, see paragraph [0086]. In light of the teaching of Hwang et al., it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the multi-layered stack of Lee et al. could comprise two different semiconductor materials, so that the active pattern 112 includes a semiconductor material which has an etching selectivity to the first semiconductor layer 111.
Independent claim 14 has been amended to require etching the source/drain region to form a first recess extending to level with a bottom surface of the second semiconductor layer, wherein the second semiconductor layer is a lowermost semiconductor layer of a channel region. In the same field of endeavor, in paragraph [0105], Hwang et al. clearly teach that the depth of the first recess RS1 can be varied, see also Figs. 7A-7C, 8. 9, 16A, and 16B. Hwang et al. clearly disclose etching the source/drain region SD1 to form a first recess RS1 extending to level with a bottom surface of the second semiconductor layer 112, wherein the second semiconductor layer 112 is a lowermost semiconductor layer of a channel region, see annotated Fig. 16A below and paragraph [0105]. In light of the teaching of Hwang et al., it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the first recess formed in the known method of Lee et al. could extend to level with a bottom surface of the second semiconductor layer 112, wherein the second semiconductor layer 112 is a lowermost semiconductor layer of a channel region, as taught by Hwang et al..
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With respect to claim 15, the method of Lee et al. further comprises a dielectric layer 190 on the gate structure 120 and the source/drain region 150; and etching the dielectric layer 190 to form a second recess exposing a top surface of the source/drain region 150, wherein the source/drain contact 172 is formed in the second recess, see Figs. 2 and 17-22.
With respect to claim 16, the method of Lee et al. further comprises forming a first spacer 171 in the second recess lining the dielectric layer 190, wherein the source/drain contact 172 is formed in contact with the first spacer 171 and the source/drain region 150, as shown in Fig. 2.
With respect to claim 17, as shown in Fig. 2 of Lee et al., a side surface of the first spacer 171 is continuous with a side surface of the source/drain region 150 adjacent the first recess.
With respect to claim 18, in the method of Lee et al., the source/drain region 150 is etched by an iterative etch process , as shown in Figs. 19-21, including a first etch process and a second etch process, wherein the first etch process deposits a polymer byproduct adjacent the source/drain region, and wherein the second etch process removes the polymer byproduct adjacent the source/drain region, see paragraphs [0142]-[0155].
With respect to claim 19, in the method of Lee et al., it would have been obvious that the first recess could extend to a depth greater than 15 nm from a top surface of the multi-layer stack, since Lee et al. discloses that the nanosheets in the channel region can have a thickness from 1 nm to 100nm, see paragraph [0029]. Since the first recess extends to about half the thickness of channel layer 310, it would have been obvious that this depth could be greater than 15 nm from a top surface of multi-layer stack.
With respect to claim 20, in the method of Lee et al., as shown in Fig. 15, the first semiconductor layer 111 is formed in physical contact with the semiconductor substrate 100/100P, wherein the second semiconductor layer 112 is formed in physical contact with the first semiconductor layer 111. However, Lee et al. fail to disclose that that a distance from the source/drain contact 172 to the second semiconductor layer 112 is less than 6 nm. However, the distance from the source/drain contact 172 to the second semiconductor layer 112 would be an obvious processing parameter to optimize and clearly ascertainable through routine experimentation, since the skilled artisan would not want to short the source/drain contact to physically touch the second semiconductor layer 112, thereby creating a short circuit and yielding an inoperable transistor.
Claims 22, 25, and 27 are rejected under 35 U.S.C. 103 as being unpatentable over Hwang et al., US 2021/0104524, as applied to claims 21 and 24 above, and further in view of Lee et al., US 2019/0074362.
Hwang et al. is applied as above. As shown in Fig. 3A of Hwang et al., the bottommost surface of the first source/drain contact P1/P2 extends below the topmost surface of the first channel region SP1 However, with respect to claim 22, Hwang et al. lack anticipation only of the bottommost surface of the first source/drain contact P1/P2 extends below the topmost surface of the first channel region SP1 by greater than 15 nm. In the same field of endeavor, Lee et al. discloses that the nanosheets in the channel region can have a thickness from 1 nm to 100nm, see paragraph [0029]. Therefore, for a first channel layer SP1 having a thickness of 100 nm, since Hwang et al. teach that the bottommost surface of the first source/drain contact P1/P2 extends below the topmost surface of the first channel region SP1, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the bottommost surface of the first source/drain contact P1/P2 could extend below the topmost surface of the first channel region SP1 by greater than 15 nm.
With respect to claim 25, Hwang et al. fails to teach that a topmost surface of the first epitaxial source/drain region SD1 is from 10 nm to 20 nm above the bottommost surface of the first source/drain contact P1/P2. However, in the same field of endeavor, Lee et al. discloses that the nanosheets in the channel region can have a thickness from 1 nm to 100nm, see paragraph [0029]. Therefore, in light of the teaching of Lee et al., it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that a topmost surface of the first epitaxial source/drain region SD1 could be from 10 nm to 20 nm above the bottommost surface of the first source/drain contact P1/P2 in the known method of Hwang et al.
With respect to claim 27, Hwang et al. disclose forming the first source/drain contact P1/P2 comprises performing a first etching process (shown in Fig. 16A) and performing a second etching process (shown in Fig. 21). However, Hwang et al. fail to teach the first etching process etches the first epitaxial source/drain region SD1 and forms a polymer byproduct along surfaces of the first epitaxial source/drain region SD1, wherein the second etching process etches the polymer byproduct. In the same field of endeavor, Lee et al. disclose etching the source/drain region 150 by an iterative etch process, as shown in Figs. 19-21, including a first etch process and a second etch process, wherein the first etch process deposits a polymer byproduct adjacent the source/drain region, and wherein the second etch process removes the polymer byproduct adjacent the source/drain region, see paragraphs [0142]-[0155]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the iterative etching process of Lee et al. to form the first source/drain contact in the known method of Hwang et al., since both etching processes are functionally equivalent for forming a source/drain contact.
Allowable Subject Matter
Claims 7-13 are allowable over the prior art of record.
The following is a statement of reasons for the indication of allowable subject matter: None of the references of record teach or suggest a method comprising: epitaxially growing a first semiconductor material; epitaxially growing a second semiconductor material over the first semiconductor material; and epitaxially growing a third semiconductor material over the second semiconductor material, wherein an atomic concentration of a dopant in the first semiconductor material is between an atomic concentration of a dopant in the third semiconductor material and an atomic concentration of a dopant in the second semiconductor material; and etching the first source/drain region to form a first recess in the first source/drain region, wherein the first recess extends through the third semiconductor material and partially through the second semiconductor material, a bottommost surface of the first recess being disposed above a bottommost surface of the second semiconductor material, as required in independent claim 7.
Response to Arguments
Applicant's arguments filed 26 May 2026 have been fully considered but they are not persuasive. Independent claim 14 has been amended to require etching the source/drain region to form a first recess extending to level with a bottom surface of the second semiconductor layer, wherein the second semiconductor layer is a lowermost semiconductor layer of a channel region. The newly cited reference to Hwang et al., US 2021/0104524, clearly teaches “etching the source/drain region to form a first recess extending to level with a bottom surface of the second semiconductor layer, wherein the second semiconductor layer is a lowermost semiconductor layer of a channel region“, as shown in Figs. 3A and 16A. As set forth above, the newly cited Hwang et al. reference anticipates Applicant’s claimed method in independent claims 14 and 21.
Furthermore, Hwang has been applied as a secondary reference with Lee et al. as the primary reference in a rejection of claims 14-20 under 35 U.S.C. 103. Hwang et al. clearly teach that the depth of the first recess RS1 can be varied, see paragraph [0105] and also Figs. 7A-7C, 8. 9, 16A, and 16B. Hwang et al. clearly disclose etching the source/drain region SD1 to form a first recess RS1 extending to level with a bottom surface of the second semiconductor layer 112, wherein the second semiconductor layer 112 is a lowermost semiconductor layer of a channel region, annotated Fig. 16A below and paragraph [0105]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the first recess formed in the known method of Lee et al. could extend to level with a bottom surface of the second semiconductor layer 112, wherein the second semiconductor layer 112 is a lowermost semiconductor layer of a channel region, as taught by Hwang et al..
Conclusion
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MARY A. WILCZEWSKI
Primary Examiner
Art Unit 2898
/MARY A WILCZEWSKI/Primary Examiner, Art Unit 2898
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