DETAILED ACTION
This Office action is in response to the Amendment filed on 22 December 2025. Claims 7-26 are pending in the application. Claims 1-6 have been cancelled.
This application is a divisional of application Serial No. 16/887,219; filed on 29 May 2020; now US Patent 11,715,777.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of the invention of Group II, on which claims 7-26 are readable, in the reply filed on 06 June 2025 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 23 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Independent claim 21, from which claim 23 depends, has been amended to require no other channel regions are between the first channel region and the semiconductor substrate. However, claim 23 requires forming a second channel region below the first channel region (emphasis added). It is unclear how a second channel layer can be below the first channel layer, if there are no other channel regions between the first channel region and the semiconductor substrate. In rejecting dependent claim 23 over prior art, claim 23 has been construed as requiring forming a second channel region above the first channel region, wherein the bottommost surface of the first source/drain contact extends below a topmost surface of the second channel region.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 21-26 are rejected under 35 U.S.C. 102(a)(2) as being clearly anticipated by Tsai et al., US 2021/0098583, newly cited.
With respect to claim 21, Tsai et al. disclose a method comprising:
forming a first channel region 28 (see paragraphs [0041] and [0066]) over a semiconductor substrate 20 (see paragraph [0035]), wherein no other channel regions are between the first channel region 28 and the semiconductor substrate 20, as shown in Fig. 15B (first channel layer 28 is the bottommost channel layer of the 4 channel layers shown in Fig. 15B);
forming a first gate stack 42/44 over the semiconductor substrate 20 and surrounding four sides of the first channel region 28, see Figs. 15B and 15C and paragraphs [0068]-[0071];
forming a first epitaxial source/drain region 38 adjacent the first gate stack 42/44 and the first channel region 28, as shown in Fig. 15B; and
forming a first source/drain contact 50 coupled to the first epitaxial source/drain region 38, a bottommost surface of the first source/drain contact 50 extending below a topmost surface of the first channel region 28, as shown in Fig. 18.
With respect to claim 22, in the method of Tsai et al., the bottommost surface of the first source/drain contact 50 extends below the topmost surface of the first channel region 28 by greater than 15 nm, see Figs. 17B and 18 and paragraphs [0042] and [0077]. First channel layer 28 has a thickness of 3 nm to 20 nm (see paragraph [0042]), and the source/drain contact 50 extends below the bottom surface of the first channel layer 28 by between about 3 nm and about 5 nm (see paragraph [0077]). Therefore, in the method of Tsai et al., the first source/drain contact 50 can extend below the topmost surface of the first channel region 28 by greater than 15 nm,
With respect to claim 23, the method of Tsai et al. further comprises forming a second channel region 28 [[below]] above the first channel region 28, wherein the bottommost surface of the first source/drain contact 50 extends below a topmost surface of the second channel region 28, as shown in Fig. 18.
With respect to claim 24, the method of Tsai et al. further comprises:
forming a first interlayer dielectric 40 over the first epitaxial source/drain region 38;
forming an opening in the first interlayer dielectric 40 to expose the first epitaxial source/drain region 38, as shown in Figs. 17A and 17B; and
forming a spacer 52/54 along sidewalls of the opening, wherein forming the first source/drain contact 50 comprises forming the first source/drain contact in the opening, wherein the spacer 52/54 separates the first source/drain contact 50 from the first interlayer dielectric 40, as shown in Fig. 18.
With respect to claim 25, in the method of Tsai et al., a topmost surface of the first epitaxial source/drain region 38 is from 10 nm to 20 nm above the bottommost surface of the first source/drain contact 50, since each of channel superlattice layers 26 and 28 can have a thickness of 3 nm for a total of 24 nm, see paragraph 42, and .the first source/drain contact 50 does not extend all the way through the channel superlattice.
With respect to claim 26, as shown in Fig. 18 of Tsai et al., a bottommost surface of the first gate stack 42/44 extends below the bottommost surface of the first source/drain contact 50.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 14-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al., US 2019/0074362, in view of Chao et al., 2019/0267463.
With respect to claim 14, Lee et al. disclose a method comprising:
forming a multi-layer stack 111/112 on a semiconductor substrate 100, the multi-layer stack comprising a first layer 111 on the semiconductor substrate 100 and a second semiconductor layer 112 on the first semiconductor layer 100, see Fig.15 and paragraphs [0131]-[0135];
replacing the first layer 111 with a gate structure 120, see Fig. 16 and paragraphs [0136]-[0140];
forming a source/drain region 150 in the semiconductor substrate 100 adjacent the gate structure 120, see Fig. 16 and paragraph [0141];
etching the source/drain region 150 to form a first recess extending to level with a bottom surface of the second semiconductor layer 112 (see Fig. 2), see Figs. 17-22 and paragraphs [0142]-[0155]; and
forming a source/drain contact 172 in the first recess, see Fig. 2.
Although Lee et al. disclose that the active pattern 112 may include a material having an etching selectivity to the sacrificial pattern 111, Lee et al. do not disclose that the multi-layer stack comprising a first semiconductor layer on the semiconductor substrate and a second semiconductor layer on the first semiconductor layer. However, in a similar method of fabricating a nano-sheet gate all-around transistor, shown in Figs. 1-9, Chao et al. disclose a multi-layer stack comprising a first semiconductor layer 106 on the semiconductor substrate and a second semiconductor layer 104 on the first semiconductor layer, as shown in Fig. 1. Chao et al. disclose that layers 104 and 106 can be semiconductor layers, see paragraphs [0020]-[0023]: “In one particular embodiment, the layers of channel material 104 may be formed from, e.g., a silicon-containing semiconductor, with silicon itself being specifically contemplated, and the layers of sacrificial material may be formed from a silicon germanium composite, with a germanium concentration of about 40%.”) In light of the teaching of Chao et al., it would have been obvious to the skilled artisan that the multi-layered stack of Lee et al. could comprise two different semiconductor materials, so that the active pattern 112 include a semiconductor material which has an etching selectivity to the sacrificial pattern 111.
With respect to claim 15, the method of Lee et al. further comprises a dielectric layer 190 on the gate structure 120 and the source/drain region 150; and etching the dielectric layer 190 to form a second recess exposing a top surface of the source/drain region 150, wherein the source/drain contact 172 is formed in the second recess, see Figs. 2 and 17-22.
With respect to claim 16, the method of Lee et al. further comprises forming a first spacer 171 in the second recess lining the dielectric layer 190, wherein the source/drain contact 172 is formed in contact with the first spacer 171 and the source/drain region 150, as shown in Fig. 2.
With respect to claim 17, as shown in Fig. 2 of Lee et al., a side surface of the first spacer 171 is continuous with a side surface of the source/drain region 150 adjacent the first recess.
With respect to claim 18.in the method of Lee et al., the source/drain region 150 is etched by an iterative etch process , as shown in Figs. 19-21, including a first etch process and a second etch process, wherein the first etch process deposits a polymer byproduct adjacent the source/drain region, and wherein the second etch process removes the polymer byproduct adjacent the source/drain region, see paragraphs [0142]-[0155].
With respect to claim 19, in the method of Lee et al., it would have been obvious that the first recess could extend to a depth greater than 15 nm from a top surface of the multi-layer stack, since Lee et al. discloses that the nanosheets in the channel region can have a thickness from 1 nm to 100nm, see paragraph [0029]. Since the first recess extends to about half the thickness of channel layer 310, it would have been obvious that this depth could be greater than 15 nm from a top surface of multi-layer stack.
With respect to claim 20, in the method of Lee et al., as shown in Fig. 15, the first semiconductor layer 111 is formed in physical contact with the semiconductor substrate 100, wherein the second semiconductor layer 112 is formed in physical contact with the first semiconductor layer 111. However, Lee et al. fail to disclose that that a distance from the source/drain contact 172 to the second semiconductor layer 112 is less than 6 nm. However, the distance from the source/drain contact 172 to the second semiconductor layer 112 would be an obvious processing parameter to optimize and clearly ascertainable through routine experimentation, since the skilled artisan would not want to short the source/drain contact to physically touch the second semiconductor layer 112, thereby creating a short circuit and yielding an inoperable transistor.
Response to Arguments
Applicant's arguments filed 22 December 2025 have been fully considered but they are not persuasive. Applicant has argued that Lee et al. fail to teach etching the source/drain region to form a first recess extending to level with a bottom surface of the second semiconductor layer, as required in independent claim 14. Applicant has argued that the active pattern 112 as seen in Fig. 16 of Lee et al. becomes wire pattern 110 as illustrated in Fig. 2 of Lee et al. However, active pattern 112 corresponds to 110, 210, and 310 in Fig. 2 of Lee et al., that is, the three layer 112 shown in Fig. 15 correspond to a first semiconductor layer 110, a second semiconductor layer 210 and a third semiconductor layer 310. As shown in Fig. 2 of Lee et al, etching the source/drain region 150 to form a first recess extending to level (h12) with a bottom surface of the second semiconductor layer 112 or 210. Lee et al. clearly teach that each of the first to third wire patterns 110, 210, and 310 may include silicon or germanium which is an elemental semiconductor material, each of the first to third wire patterns 110, 210, and 310 may be used as a channel region of the transistor, see paragraphs [0045]-[0046], hence, it is clear that active patterns 112 shown in Fig. 15 correspond to wires 110, 210, and 310 illustrated in Fig. 2 of Lee. For these reasons, the method of claim 14 is not deemed patentably distinct from the known method of Lee et al.
Allowable Subject Matter
Claims 7-13 are allowable over the prior art of record.
The following is a statement of reasons for the indication of allowable subject matter: None of the references of record teach or suggest a method comprising: epitaxially growing a first semiconductor material; epitaxially growing a second semiconductor material over the first semiconductor material; and epitaxially growing a third semiconductor material over the second semiconductor material, wherein an atomic concentration of a dopant in the first semiconductor material is between an atomic concentration of a dopant in the third semiconductor material and an atomic concentration of a dopant in the second semiconductor material; and etching the first source/drain region to form a first recess in the first source/drain region, wherein the first recess extends through the third semiconductor material and partially through the second semiconductor material, a bottommost surface of the first recess being disposed above a bottommost surface of the second semiconductor material, as required in independent claim 7.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The additionally cited references disclose the formation of contacts to epitaxial source/drain regions.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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MARY A. WILCZEWSKI
Primary Examiner
Art Unit 2898
/MARY A WILCZEWSKI/Primary Examiner, Art Unit 2898