DETAILED ACTION
This Office action is in response to the Request for Continued Examination (RCE) and the Amendment submitted on 18 February 2026. Claims 1-18, 20, and 21 are pending in this application. Claim 19 has been cancelled. Claim 21 is newly submitted.
This application is a divisional of application Serial No. 16/888,264; filed on 29 May 2020; now US Patent 11,854,688 which claims priority to provisional application 62/978,617, filed on 15 February 2020.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 18 February 2026 has been entered.
Drawings
In light of Applicant’s arguments, the previous rejection of the drawings under 37 CFR 1.83(a) has been withdrawn.
Claim Rejections - 35 USC § 112
In light of Applicant’s arguments, the rejection of claims 3 and 4 under 35 U.S.C. 112(a) has been withdrawn.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3 are rejected under 35 U.S.C. 102(a)(1) as being clearly anticipated by Kim et al., US 2019/0386099, newly cited.
With respect to claim 1, Kim et al. disclose a semiconductor device, shown in Fig. 4, comprising:
a shallow trench isolation region 105 (see paragraph [0051]-[0052]) on a semiconductor substrate 100 (see paragraph [0043]);
a gate stack 130 (paragraph [0060]) on the shallow trench isolation region 105; as shown in Fig. 4; and
an interlayer dielectric 180/192 on the shallow trench isolation region 105 and the gate stack 130, as shown in Fig. 4, wherein the interlayer dielectric 180/192 comprises a first rounded profile extending into the shallow trench isolation region 105 to a first depth below a top surface of the shallow trench isolation region 105 and a second rounded profile extending into the shallow trench isolation region 105 from the first rounded profile to a second depth below the top surface of the shallow trench isolation region 105, wherein the second depth is different than the first depth,
wherein the first rounded profile and the second rounded profile of the interlayer dielectric each have a convex shape, as shown in annotated Fig. 4 below.
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With respect to claim 2, the semiconductor device of Kim et al. further comprises a first fin 310 extending from the semiconductor substrate 100; and a second fin 410 extending from the semiconductor substrate 100, wherein the interlayer dielectric 180/192 extends into the shallow trench isolation region 105 to a third depth 180t below the top surface of the shallow trench isolation region 105 between the first fin and the second fin, as shown in Figs. 1, 3, and 4, wherein the interlayer dielectric 180/192 extends into the shallow trench isolation region 105 to a fourth depth below the top surface of the shallow trench isolation region 105 outside the first fin 310 and the second fin 410, and wherein the fourth depth is greater than the third depth, see Figs. 1 and 4, see annotated Fig. 4 below.
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With respect to claim 3, in the semiconductor device of Kim et al., the interlayer dielectric 180/192 comprises a third rounded profile extending into the shallow trench isolation region to a fifth depth, and wherein the interlayer dielectric comprises a fourth rounded profile extending into the shallow trench isolation region to the fourth depth below the top surface of the shallow trench isolation region, as shown in annotated Fig. 4 below.
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Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al., US 2019/0386099, newly cited.
Kim et al. is applied as above. Kim et al. lack anticipation of the limitations of dependent claims 4 and 5, that is the third depth is 5 nm to 10 nm, wherein the fourth depth is 15 nm to 25 nm, and wherein the fifth depth is from 10 nm to 20 nm, and .
the first depth is 10 nm to 20 nm, and wherein the second depth is from 15 nm to 25 nm. However, Kim et al. teach the relative depths with respect to one another, as shown in Figs. 3 and 4 of Kim et al.. It has been well established that where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Since Kim et al. disclose the relative depths of these claims, the claimed depths would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention and clearly ascertainable through routine experimentation because it is not inventive to discover the optimum or workable ranges of these depths.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al., US 2019/0386099, as applied to claim 1 above, in view of Yaegashi et al., US 2010/0230739, of record.
Kim et al. disclose a gate spacer 185 adjacent the gate stack, as shown in Fig. 3. However, Kim et al. lack anticipation of the interlayer dielectric 180/192 extending under the gate spacer in a direction parallel to a major surface of the semiconductor substrate. However, in the same filed of endeavor, Yaegashi et al. disclose a semiconductor device in which comprises a gate spacer 22b adjacent the gate stack 21/22, wherein an interlayer dielectric 31 extends under the gate spacer 22b in a direction parallel to a major surface of the semiconductor substrate 11, as shown in Fig. 5. Hence, between the disclosures of Kim et al. and Yaegashi et al., the interlayer dielectric can either extend under a gate spacer or not extend under a gate spacer. In light of this teaching of Yaegashi et al., it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the interlayer dielectric 180/192 in the known semiconductor device of Kim et al. could have extended under the gate spacer 185 in a direction parallel to a major surface of the semiconductor substrate 100, since “obvious to try” is a proper rationale to support a conclusion that the claim would have been obvious if a person of ordinary skill has good reason to pursue the known options within his or her technical grasp. KSR, 550 U.S. at 421, 82 USPQ2d at 1397.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al., US 2019/0386099, as applied to claim 1 above, in view of Shepard, US 5,729,043, of record.
Kim et al. is applied as above. Kim et al. lack anticipation of the shallow trench isolation region 105 doped with phosphorus. Shepard discloses shallow trench isolation in a semiconductor device in which the STI is doped with phosphorus in the amount of 1-5 E15/cm2, see Fig. 4C and column 4, lines 53-55. Since the shallow trench isolation of Shepard doped with phosphorus is an improved trench isolation, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to dope the shallow trench isolation region 105 in the known device of Kim et al. with a phosphorous concentration of at least 1 x 1015 atoms/cm3, thereby providing an improved shallow trench isolation region.
Claims 14, 18, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al., US 2019/0386099, newly cited, in view of Fung et al., US 2011/0193107, newly cited.
With respect to claim 14, Kim et al. disclose a semiconductor device, shown in Fig. 4, comprising:
a shallow trench isolation region (STI) 105 (see paragraph [0051]-[0052]) over a semiconductor substrate 100 (see paragraph [0043]);
a gate electrode 130 (paragraph [0060]) over the STI region 105; as shown in Fig. 4; and
a first dielectric 180/192 over the STI region 105 and surrounding the gate electrode 130, the first dielectric 180/192 comprising an interlayer dielectric (ILD) 180/192, the first dielectric 180/192 having a first rounded profile extending below a top surface of the STI region 105 a first distance, the first dielectric having a second rounded profile extending from the first rounded profile below a top surface of the STI region 105 a second distance, as shown in annotated Fig. 4 above provided in the rejection of independent claim 1.
Kim et al. lack anticipation only of the first dielectric 180/192 comprising a contact etch stop layer (CESL) and an interlayer dielectric (ILD) 180/192 over the CESL, wherein the CESL is at the lowest point of the second rounded profile. However, in the same filed of endeavor, Fung et al. disclose a semiconductor device comprising a first dielectric 66/70 comprising a contact etch stop layer (CESL) 66 and an interlayer dielectric (ILD) 70 over the CESL 66, wherein the CESL 66 is at the lowest point of the second rounded profile, as shown in Fig. 8A. Fung et al. disclose that the CESL 66 may apply a stress to the underlying MOS devices 240 and 340 to improve the carrier mobility. Therefore, in order to improve carrier MOBILITY IN THE KNOWN DEVICE OF Kim et al., it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include a CESL in the first dielectric in the known device of Kim et al., thereby resulting in the first dielectric 180/192 comprising a contact etch stop layer (CESL) and an interlayer dielectric (ILD) 180/192 over the CESL, wherein the CESL is at the lowest point of the second rounded profile shown in Fig. 4 of Kim et al.
Kim et al. lack anticipation of the limitations of dependent claim 18, that is, wherein the first rounded profile has a maximum width from 25 nm to 30 nm, and wherein the second rounded profile has a maximum width from 5 nm to 10 nm. However, Kim et al. teach the relative widths with respect to one another, as shown in Fig.4 of Kim et al.. It has been well established that where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Since Kim et al. disclose the width of the first rounded profile is greater than the width of the second rounded profile, the claimed widths required in claim 18 would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention and clearly ascertainable through routine experimentation because it is not inventive to discover the optimum or workable ranges of these widths.
With respect to claim 21, Kim et al. lack anticipation of the first distance being from 5 nm to 25 nm and the second distance being from 10 nm to 30 nm. However, Kim et al. teach the relative distances with respect to one another, that is, the first distance is less than the second distance, as shown in Fig. 4 of Kim et al.. It has been well established that where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Since Kim et al. disclose the relative distances of claim 21, these claimed distances would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention and clearly ascertainable through routine experimentation because it is not inventive to discover the optimum or workable ranges of these distances.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al., US 2019/0386099, in view of Fung et al., US 2011/0193107, as applied to claim 14 above, further in view of Yaegashi et al., US 2010/0230739, of record.
Kim et al. disclose a gate spacer 185 adjacent the gate electrode 130, as shown in Fig. 3. However, Kim et al. lack anticipation of the first dielectric 180/192 extending under the gate spacer a lateral distance from 3 nm to 5 nm. However, in the same filed of endeavor, Yaegashi et al. disclose a semiconductor device in which comprises a gate spacer 22b adjacent the gate electrode 22, wherein a first dielectric 31 extends under the gate spacer 22b, as shown in Fig. 5. Hence, between the disclosures of Kim et al. and Yaegashi et al., the first dielectric can either extend under a gate spacer or not extend under a gate spacer. In light of the teaching of Yaegashi et al., it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the first dielectric 180/192 in the known semiconductor device of Kim et al. could have extended under the gate spacer 185, since “obvious to try” is a proper rationale to support a conclusion that the claim would have been obvious if a person of ordinary skill has good reason to pursue the known options within his or her technical grasp. KSR, 550 U.S. at 421, 82 USPQ2d at 1397.
Admittedly, Yaegashi et al. do not specifically disclose that the first dielectric extends under the gate spacer a lateral distance from 3 nm to 5 nm. However, Yaegashi et al. clearly show the first dielectric extends under spacer 22b. It has been well established that where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Since Yaegashi et al. disclose the first dielectric extends under the gate spacer, the lateral distance the first dielectric extends under the spacer would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention and clearly ascertainable through routine experimentation because it is not inventive to discover the optimum or workable ranges of this lateral distance.
Claims 16 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al., US 2019/0386099 in view of Fung et al, US 2011/0193167, as applied to claim 14 above, further in view of Shepard, US 5,729,043, of record.
Kim et al. and Fung et al. are applied as above. Neither Kim et al. nor Fung et al. teach or suggest the STI region 105 is doped with phosphorus to a dopant concentration of at least 1 x 1015 atoms/cm3. Shepard discloses shallow trench isolation in a semiconductor device in which the STI is doped with phosphorus in the amount of 1-5 E15/cm2, see Fig. 4C and column 4, lines 53-55. Since the shallow trench isolation of Shepard doped with phosphorus is an improved trench isolation, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to dope the shallow trench isolation region 105 in the known device of Kim et al. with a phosphorous concentration of at least 1 x 1015 atoms/cm3, thereby providing an improved shallow trench isolation region.
-With respect to claim 20, the semiconductor device of Kim et al. further comprises a source/drain contact 195 extending at least partially through the first dielectric 180/192, wherein a bottom surface of the source/drain contact is disposed below a top surface of the STI region 105, as shown in annotated Fig. 16 below.
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Allowable Subject Matter
Claims 8-13 are allowable over the prior art of record.
The following is a statement of reasons for the indication of allowable subject matter: The newly cited reference to Kim et al. fails to teach or suggest a semiconductor device comprising: a semiconductor fin extending from a semiconductor substrate; a first gate stack on the semiconductor fin; a source/drain region in the semiconductor fin adjacent the first gate stack; an interlayer dielectric (ILD) and a contact etch stop layer (CESL)on the semiconductor fin, the first gate stack, and the source/drain region, the ILD and the CESL comprising a first rounded portion extending below a bottom surface of the first gate stack, the first rounded portion having a first width, the ILD and the CESL further comprising a second rounded portion extending below the first rounded portion, the second rounded portion having a second width less than the first width, the CESL being at the lowest point of the second rounded portion; and a source/drain contact extending in the ILD and electrically coupled to the source/drain region.
Response to Arguments
Applicant’s arguments with respect to claim(s 1-7 have been considered but are moot in light of the new grounds of rejection based on Kim et al., US 2019/0386099, newly cited.
Conclusion
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MARY A. WILCZEWSKI
Primary Examiner
Art Unit 2898
/MARY A WILCZEWSKI/Primary Examiner, Art Unit 2898
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