Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 8/25/26 has been entered.
Information Disclosure Statement
The information disclosure statement filed 8/25/26 has been considered.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 22, 25, 29, 32-33, 35, 39, 42-45 is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by MISAKI (U.S. Patent Publication No. 2019/0385960).
Referring to figures 3A, MISAKI teaches a power semiconductor device, comprising:
a substrate (1);
an insulating layer (2/4) disposed over the substrate;
a metal layer (SL/7S/7D, see paragraph# 126) disposed over the insulating layer and including a first portion (SL) and a second portion (7s/7d), the first portion having a first thickness and the second portion having a second thickness greater than the first thickness (see figure 3a);
a coating layer (11) disposed over the metal layer and having a portion with a third thickness greater than the second thickness, the first portion of the metal layer being disposed between the portion of the coating layer and the second portion of the metal layer, the coating layer including an insulating material (see figure 3a); and
a protective layer (17) covering the substrate, the insulating layer, the metal layer, and the coating layer (see figure 3a).
Regarding to claim 25, the first thickness is a distance between an upper surface of the first portion and a lower surface of the first portion at an outer edge of the first portion, and the second thickness is a distance between an upper surface of the second portion and a lower surface of the second portion at an outer edge of the second portion (see figure 3a).
Regarding to claim 29, the metal layer includes Al, Cu, and W (see paragraph# 150).
Regarding to claim 32, the coating layer has a honeycomb structure (11, see figure 3a).
Regarding to claim 33, the third thickness of the coating layer is at least 2 times greater than the second thickness of the second portion.
Regarding to claim 34, the protective layer has a coefficient of thermal expansion (CTE) in a range from 3.4*10-6/oC to 8.0*10-6/C, and the substrate has a CTE in a range from 4.2*10-6/oC to 4.4*10-6/oC.
Regarding to claim 35, the insulating layer is a first insulating layer (4), the power semiconductor device comprising: a second insulating layer (2) disposed between the substrate (1) and the first insulating layer (4); and a passivation layer (17, the first portion that coplanar with layer 15 (protective layer), the second the portion of layer is the portion on top of first portion) disposed over the first insulating layer and the metal layer (see figure 3a).
Regarding to claim 39, a power semiconductor device, comprising:
a substrate (1);
an insulating layer (2/4) disposed over the substrate;
a metal layer (SL/7S/7D) disposed over the insulating layer and including a first portion (SL) and a second portion (7S/7D), the first portion having a first thickness and the second portion having a second thickness greater than the first thickness, the second portion being spaced apart from the first portion (see figure 3a);
a coating layer (11) disposed over the metal layer and having a portion with a third thickness greater than the second thickness, the first portion of the metal layer being disposed between the portion of the coating layer and the second portion of the metal layer the coating layer including an insulating material (see figure 3a); and
a protective layer (17) covering the substrate, the insulating layer, the metal layer, and the coating layer (see figures 3a).
Regarding to claim 42, wherein the portion of the coating layer (11) is a first portion of the coating layer (SL), the coating layer has a second portion (7S/7D) over the first portion of the metal layer or over the second portion of the metal layer of the second portion of the coating layer has a thickness less than the third thickness (see figures 3a).
Regarding to claim 43, the portion of the coating layer (11) having the third thickness is disposed over and in direct contact with a portion of the passivation layer.
Regarding claim 44, no metal layer is disposed under the portion of the coating layer (11) have the third thickness (see figure 3a).
Regarding to claim 45, an upper surface of the first portion is at a level different than that of an upper surface of the second portion (see figure 3a).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 23-24, 27-28, 33, 40-41 is/are rejected under 35 U.S.C. 103 as being unpatentable over MISAKI (U.S. Patent Publication No. 2019/0385960) as applied in claims 22, 22, 25, 29, 32-33, 35, 39, 42-45 above.
Referring to figures 3A, MISAKI teaches a power semiconductor device, comprising:
a substrate (1);
an insulating layer (2/4) disposed over the substrate;
a metal layer (SL/7S/7D, see paragraph# 126) disposed over the insulating layer and including a first portion (SL) and a second portion (7s/7d), the first portion having a first thickness and the second portion having a second thickness greater than the first thickness (see figure 3a);
a coating layer (11) disposed over the metal layer and having a portion with a third thickness greater than the second thickness, the first portion of the metal layer being disposed between the portion of the coating layer and the second portion of the metal layer, the coating layer including an insulating material (see figure 3a); and
a protective layer (17) covering the substrate, the insulating layer, the metal layer, and the coating layer (see figure 3a).
However, the reference does not clearly teach the specific dimensions of the layers in claims 23-24, 27-28, 33, 38, 40-41.
In re claims 23-24, 27-28, 33, 40-41, the selection of the thickness is obvious because it is a matter of determining optimum process condition by routine experimentation with a limited number of species. In re Jones, 162 USPQ 224 (CCPA 1955)(the selection of optimum ranges within prior art general conditions is obvious) and In re Boesch, 205 USPQ 215 (CCPA 1980)(discovery of optimum value of result effective variable in a known process is obvious). In such a situation, applicant must show that the particular range is critical, generally by showing that the claimed range achieves unexpected results relative to prior art range. See M.P.E.P 2144.05 III. In particular, Wu et al suggest that the thickness (figures 13). The specification contains no disclosure of either the critical nature of the claimed dimensions or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen limitations or upon another variable recited in a claim, the applicant must show that the chosen limitations are critical. In re Woodruff, 919 F.2d 1575, 1578 (FED. Cir. 1990).
Therefore, it would have been obvious to a person of ordinary skill in the art at the time of the invention was filed would to form layers with specific dimension in MISAKI because choosing an optimum dimension for a layer is known in the semiconductor art to form a desired device.
Claim(s) 36 is/are rejected under 35 U.S.C. 103 as being unpatentable over MISAKI (U.S. Patent Publication No. 2019/0385960) as applied in claims 22, 25, 29, 32-33, 35, 39, 42-45 above in view of Koezuka et al. (U.S. Patent Publication No. 2020/0052100).
Referring to figures 3A, MISAKI teaches a power semiconductor device, comprising:
a substrate (1);
an insulating layer (2/4) disposed over the substrate;
a metal layer (SL/7S/7D, see paragraph# 126) disposed over the insulating layer and including a first portion (SL) and a second portion (7s/7d), the first portion having a first thickness and the second portion having a second thickness greater than the first thickness (see figure 3a);
a coating layer (11) disposed over the metal layer and having a portion with a third thickness greater than the second thickness, the first portion of the metal layer being disposed between the portion of the coating layer and the second portion of the metal layer, the coating layer including an insulating material (see figure 3a); and
a protective layer (17) covering the substrate, the insulating layer, the metal layer, and the coating layer (see figure 3a).
However, the reference does not clearly teach the silicon carbide (SiC) substrate, Gallium nitride (GaN) substrate, or Gallium arsenide (GaAs) substrate (in claim 36).
Koezuka et al. teaches a semiconductor device having a silicon carbide substrate (see paragraph# 119, figure 1).Therefore, it would have been obvious to a person of ordinary skill in the art at the time of the invention was filed would to form the silicon carbide (SiC) substrate, Gallium nitride (GaN) substrate, or Gallium arsenide (GaAs) substrate in MISAKI as taught by Koezuka et al. because choosing an optimum material for a layer is known in the semiconductor art to support for the device.
Allowable Subject Matter
Claims 37-38 are allowed. None of the prior art teaches/suggest a power semiconductor device, comprising: a passivation layer disposed over the second insulating layer and the metal layer; a coating layer disposed over the passivation layer and having a portion with a third thickness greater than the second thickness, the first portion of the metal layer being disposed between the portion of the coating layer and the second portion of the metal layer; and
a protective layer covering the substrate, the first insulating layer, the second insulating layer, the metal layer, the passivation layer, and the coating layer.
Claim 34 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Thanh Nguyen whose telephone number is (571) 272-1695, or by Email via address Thanh.Nguyen@uspto.gov. The examiner can normally be reached on Monday-Thursday from 6:00AM to 3:30PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Yara Green, can be reached on (571) 270-3035. The fax phone number for this Group is (571) 273-8300.
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/THANH T NGUYEN/ Primary Examiner, Art Unit 2893
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