Prosecution Insights
Last updated: April 19, 2026
Application No. 17/814,905

Structure and Method for Single Gate Non-Volatile Memory Device

Non-Final OA §103§112
Filed
Jul 26, 2022
Examiner
BELL, LAUREN R
Art Unit
2896
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company Ltd.
OA Round
3 (Non-Final)
40%
Grant Probability
At Risk
3-4
OA Rounds
3y 7m
To Grant
70%
With Interview

Examiner Intelligence

Grants only 40% of cases
40%
Career Allow Rate
148 granted / 375 resolved
-28.5% vs TC avg
Strong +31% interview lift
Without
With
+30.7%
Interview Lift
resolved cases with interview
Typical timeline
3y 7m
Avg Prosecution
61 currently pending
Career history
436
Total Applications
across all art units

Statute-Specific Performance

§103
42.1%
+2.1% vs TC avg
§102
19.7%
-20.3% vs TC avg
§112
33.1%
-6.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 375 resolved cases

Office Action

§103 §112
DETAILED ACTION Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/18/2026 has been entered. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1-16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Regarding claim 1, the limitation “free of any silicide” is unclear as to how it is related to the previous recitation of silicide and as to what is required of “any.” Specifically, “any” is defined as “one or some, no matter which,” or “one, some, or several, as specified, no matter how much or many, what kind or quality, etc.” It is unclear if the limitation refers to the same silicide as the previous recitation, and also as to the proper interpretation of being free of “any.” Regarding claim 11, the limitation “free of physical contact with silicide,” is unclear as to how it is related to the previous recitation of silicide and as to what is required by “free of physical contact.” Specifically, it is unclear how “silicide” relates to the previous recitation of silicide. It is further unclear what types “physical contact” are precluded by the limitation, e.g. thermal, direct, electrical, contact. Note the dependent claims necessarily inherit the indefiniteness of the claims on which they depend. Claim Rejections - 35 USC § 103 The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action: (a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under pre-AIA 35 U.S.C. 103(a) are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims under pre-AIA 35 U.S.C. 103(a), the examiner presumes that the subject matter of the various claims was commonly owned at the time any inventions covered therein were made absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and invention dates of each claim that was not commonly owned at the time a later invention was made in order for the examiner to consider the applicability of pre-AIA 35 U.S.C. 103(c) and potential pre-AIA 35 U.S.C. 102(e), (f) or (g) prior art under pre-AIA 35 U.S.C. 103(a). Claim(s) 11-16 is/are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable Pikhay et al. (US 2009/0213660; herein “Pikhay ‘660”) in view of Okumura et al. (US 6163046; herein referred to as “Okumura”). Regarding claim 11, Pikhay teaches in Figs. 1, 7, 12 and related text (including similar features as discussed in accordance with Fig. 5) semiconductor device comprising: a field effect transistor (HV MOSFET 130, see [0033]) disposed in a periphery region of a substrate (101), the field effect transistor including a gate electrode (120-3), a first source (S130), a first drain (D130); and a floating gate non-volatile memory device disposed in a memory region of the substrate, the floating gate non-volatile memory device including a second source, a second drain, a third source, and a third drain, a fourth source, a first floating gate electrode associated with the second source, the second drain, and the third source and a second floating gate electrode associated with the second source, the third drain, and the fourth source, wherein the second floating gate electrode is physically spaced apart from the first floating gate electrode, wherein the first floating gate electrode (120-5C of 150C-2,1), the second source (S155C of 150C-2,1/150C-3,1), and the second drain (D150C of 150C-2,1) form a first injection transistor (158 of 150C-2,1), the first floating gate electrode, the third source (S151C of 150C-2,1), and the second drain form a first floating gate transistor (151C of 150C-2,1), the second floating gate electrode (120-5C of 150C-3,1), the second source, and the third drain (D150C of 150C-3,1) form a second injection transistor (158 of 150C-3,1), the second floating gate electrode, the third drain, and the fourth source (S151 of 150C-3,1) form a second floating gate transistor (151C of 150C-3,1), wherein the second source is disposed lengthwise between the first floating gate electrode and the second floating gate electrode , wherein the second source a constant width an entire length between the first floating gate electrode and the second floating gate electrode (e.g. a width in the vertical direction as oriented in Fig. 12), wherein each of the third source and the fourth source has a width that is larger than the constant width of the second source (e.g. a width in a diagonal direction as oriented in Fig. 12); wherein the floating gate non-volatile memory device is free of any silicide feature (see Fig. 5). Pikhay does not disclose the field effect transistor disposed in a periphery region of the semiconductor device includes silicide, wherein the gate electrode of the field effect transistor is free of physical contact with silicide. In the same field of endeavor, Okumura teaches in Fig. 5A-B and related text an integrated circuit comprising a field effect transistor disposed in a periphery region and including a gate electrode, a first source, and a first drain, the field effect transistor includes silicide (24, see col. 13 lines 46-51), wherein the gate electrode of the field effect transistor is free of physical contact with silicide (see Fig. 5B) and wherein the memory device is free of any silicide feature (see Fig. 5A). It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify the device of Pikhay by having the field effect transistor disposed in a periphery region of the semiconductor device includes silicide, wherein the gate electrode of the field effect transistor is free of physical contact with silicide, as taught by Okumura, in order to provide low resistivity for source/drain contacts while employing a metal gate structure. Regarding claims 12-13, Pikhay further discloses a first contact (box with “X” shape) disposed directly on the second source; an injection bit line coupled to the first contact (see [0056] and [0037]); a second contact (box with “X” shape) disposed directly on the third source; and a read bit line coupled to the second contact; a third contact and a fourth contact (box with “X” shape) disposed directly on the second drain; and a word line coupled to the third contact and the fourth contact. Additionally, it is the Office’s position that the limitations “an injection bit line…,” “a read bit line…” and “a word line…” are directed to a method of using the device and that because the device of Pikhay has all of the structural limitations of the claimed invention the device is capable of being operated in the manner claimed by the applicant. A claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987). Further, while features of an apparatus may be recited either structurally or functionally, claims directed to apparatus must be distinguished from the prior art in terms of structure rather than function. In re Schreiber, 128 F.3d 1473, 1477-78, 44 USPQ2d 1429, 1431- 32 (Fed. Cir. 1997); see also In re Swinehart, 439 F.2d 210, 212-13, 169 USPQ 226, 228-29 (CCPA 1971); In re Danly, 263 F.2d 844, 847, 120 USPQ 528, 531 (CCPA 1959); MPEP 2114. Regarding claim 14, Pikhay further discloses wherein the first floating gate electrode includes at least a first portion, a second portion, and a third portion, the first portion disposed between the second source and the second drain, the second portion disposed between the third source and the second drain, and the third portion disposed over (e.g. at a position higher than) the second drain and configured to physically connect the first portion to the second portion (see Fig. 26). Regarding claim 15, Pikhay further discloses wherein a width of the first portion is smaller than a width of the second portion (note that one can choose portions such that the claimed limitation is met). Regarding claim 16, the combined device shows wherein the silicide is disposed on the first source and the first drain of the field effect transistor (Fang: 1021 and 1022, see [0047]). Allowable Subject Matter Claims 21-24 are allowed. Response to Arguments Applicant's arguments filed 12/18/2025 have been fully considered but are moot in view of the new grounds of rejection presented above. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Lauren R Bell whose telephone number is (571)272-7199. The examiner can normally be reached M-F 8am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Kraig can be reached at (571) 272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /LAUREN R BELL/Primary Examiner, Art Unit 2896 3/24/2026
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Prosecution Timeline

Jul 26, 2022
Application Filed
Apr 03, 2025
Non-Final Rejection — §103, §112
Aug 22, 2025
Interview Requested
Aug 29, 2025
Examiner Interview Summary
Aug 29, 2025
Applicant Interview (Telephonic)
Sep 03, 2025
Response Filed
Sep 30, 2025
Final Rejection — §103, §112
Dec 18, 2025
Request for Continued Examination
Jan 09, 2026
Response after Non-Final Action
Mar 24, 2026
Non-Final Rejection — §103, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
40%
Grant Probability
70%
With Interview (+30.7%)
3y 7m
Median Time to Grant
High
PTA Risk
Based on 375 resolved cases by this examiner. Grant probability derived from career allow rate.

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