DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 7/26/22, 12/28/22, and 1/4/24 were filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “top surface of the conductive via is below a top surface of the encapsulant” as recited in claim 3 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim 20 is objected to because of the following informalities:
Claim 20 recites “comprising” in line 1, the examiner advises using the verb “comprises” instead of the gerund “comprising”.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 6, 8, 9, 10, 12, 13, 14, 15, 16, 17, 18, 19, and 20 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Chiang (US 10832985).
The applied reference has a common inventor with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
Regarding claim 1.
Chiang teaches a method comprising: forming a sacrificial layer (166) on a semiconductor die (130) (paragraph 52), the semiconductor die (126) comprising a sensor (paragraph 24); forming a conductive via (116) on a first redistribution structure (106) (paragraph 20); placing the semiconductor die (126) on the first redistribution structure (106) adjacent the conductive via (116); encapsulating (142) the semiconductor die (126), the sacrificial layer (166), and the conductive via (116) with an encapsulant (142) (fig 15) (paragraph 53-54); planarizing the encapsulant to expose the conductive via and the sacrificial layer (fig 15-16) (paragraph 54); removing the sacrificial layer (166) using an etching process (paragraph 54); and forming a second redistribution structure (144) over the encapsulant (142) and over the semiconductor die, wherein the second redistribution structure is electrically connected to the conductive via (116) and to the semiconductor die (126), and wherein the second redistribution structure (144) comprises an opening (152) that exposes the sensor of the semiconductor die (126) (fig 17) (paragraph 54-55).
Regarding claim 6.
Chiang teaches the sacrificial layer (166) comprises a polymer (paragraph 52).
Regarding claim 8
Chiang teaches forming the second redistribution(144) process comprises: depositing a first dielectric layer (146) over the encapsulant (142) and over the semiconductor die (126); patterning the first dielectric layer (142); forming a metallization pattern (148) on the patterned first dielectric layer; and depositing a second dielectric layer over the metallization pattern (paragraph 36-38) (fig 20).
Regarding claim 9.
Chiang teaches a method comprising: forming a conductive via (116) on a substrate (102) (paragraph 52-54); attaching a sensor device (126) to the substrate (102) (fig 15) (paragraph 24,52-54); depositing a polymer material (166) on the sensor device (126) (paragraph 52); depositing a molding material (142) on the conductive via (116) (paragraph 53-54), the sensor device (126); and the polymer material (166); after depositing the molding material (142), removing the polymer material (166) to expose the sensor device (126); depositing a dielectric material (146) on the molding material (142), the conductive via (116), and the sensor device (126) (fig 15-16); removing a first portion (152) of the dielectric material (142) to expose a sensing region of the sensor device (126); and forming a metallization pattern (148) on the dielectric material (146), wherein the metallization pattern (148) physically and electrically contacts the conductive via and the sensor device (fig 17) (paragraph 54-56).
Regarding claim 10.
Chiang teaches the substrate (102) comprises a redistribution layer (106), wherein the conductive via (116) is electrically connected to the redistribution layer (106) (fig 16) (paragraph 15).
Regarding claim 12.
Chiang teaches removing a second portion of the dielectric material (142) to expose a contact pad (134) of the sensor device (126) (fig 16-17) (paragraph 52-55).
Regarding claim 13.
Chiang teaches performing a planarization process on the molding material (142) to expose the polymer material (166) (fig 15) (paragraph 52-53).
Regarding claim 14.
Chiang teaches after forming the metallization pattern (148), the sensing region of the sensor device is exposed (fig 17).
Regarding claim 15.
Chiang teaches forming the metallization pattern (148) comprises: depositing a photoresist on the dielectric material and on the exposed sensing region of the sensor device; patterning the photoresist, wherein the patterned photoresist covers the sensing region of the sensor device; and depositing a conductive material over the patterned photoresist and over the dielectric material (146) (paragraph 36).
Regarding claim 16.
Chiang teaches an insulating material (150) over the conductive material (148); and etching the insulating material to expose (152)2 the sensing region of the sensor device (126) (fig 17) (paragraph 53-56).
Regarding claim 17.
Chiang teaches a method comprising: forming a semiconductor device (126) comprising a sensor region (paragraph 24); depositing a sacrificial material (166) over the sensor region of the semiconductor device (126) (fig 15); attaching the semiconductor device (126) to a redistribution structure (106); encapsulating (142) the semiconductor device (126) and the sacrificial material (166) with an encapsulant (142); forming a via (116) penetrating the encapsulant (142) to contact the redistribution structure (106) (fig 15) (paragraph 52-55); removing the encapsulant (142) to expose the sacrificial material (166); etching the sacrificial material (166) to expose the sensor region; and forming a metallization pattern (144) over the via (116) and the semiconductor device (126), wherein the metallization pattern (144) electrically connects the via (116) to the semiconductor device (126) (paragraph 52-56) (fig 15-17).
Regarding claim 18.
Chiang teaches before forming the metallization pattern (144), depositing a first dielectric material (146) over the via (116), the encapsulant (142), and the semiconductor device (126) (fig 17) (paragraph 34-38).
Regarding claim 19.
Chiang teaches etching the first dielectric material (142) to expose the sensor region (paragraph 53-56) (fig 17).
Regarding claim 20.
Chiang teaches removing the encapsulant (142) comprising a planarization process (paragraph 54).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2 and 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chiang (US 10832985) as applied to claim 1 and further in view of Yama (US 2007/0042521).
Regarding claim 2.
Chiang teaches elements of the claimed invention above.
Chiang does not teach wet etching.
Yama teaches etching a sacrificial material comprises a wet chemical etching process (paragraph 66).
It would have been obvious to one of ordinary skill in the art to use wet chemical etching in order to dissolve and remove the sacrificial material.
Regarding claim 4.
Chiang teaches elements of the claimed invention above.
Chiang does not teach plasma etching.
Yama teaches etching a sacrificial material comprises a plasma etching process (paragraph 66).
It would have been obvious to one of ordinary skill in the art to use plasma etching in order to dissolve and remove the sacrificial material.
Allowable Subject Matter
Claims 3, 5, 7, and 11 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 3, the prior art does not teach a method comprising: forming a sacrificial layer on a semiconductor die, the semiconductor die comprising a sensor; forming a conductive via on a first redistribution structure; placing the semiconductor die on the first redistribution structure adjacent the conductive via; encapsulating the semiconductor die, the sacrificial layer, and the conductive via with an encapsulant; planarizing the encapsulant to expose the conductive via and the sacrificial layer; removing the sacrificial layer using an etching process; and forming a second redistribution structure over the encapsulant and over the semiconductor die, wherein the second redistribution structure is electrically connected to the conductive via and to the semiconductor die, and wherein the second redistribution structure comprises an opening that exposes the sensor of the semiconductor die, wherein after removing the sacrificial layer, a top surface of the conductive via is below a top surface of the encapsulant.
Regarding claim 5, the prior art does not teach a method comprising: forming a sacrificial layer on a semiconductor die, the semiconductor die comprising a sensor; forming a conductive via on a first redistribution structure; placing the semiconductor die on the first redistribution structure adjacent the conductive via; encapsulating the semiconductor die, the sacrificial layer, and the conductive via with an encapsulant; planarizing the encapsulant to expose the conductive via and the sacrificial layer; removing the sacrificial layer using an etching process; and forming a second redistribution structure over the encapsulant and over the semiconductor die, wherein the second redistribution structure is electrically connected to the conductive via and to the semiconductor die, and wherein the second redistribution structure comprises an opening that exposes the sensor of the semiconductor die, after forming the sacrificial layer on the semiconductor die, using a laser process to remove the sacrificial layer over a scribe region and using a sawing process on the scribe region to singulate the semiconductor die.
Regarding claim 7, the prior art does not teach a method comprising: forming a sacrificial layer on a semiconductor die, the semiconductor die comprising a sensor; forming a conductive via on a first redistribution structure; placing the semiconductor die on the first redistribution structure adjacent the conductive via; encapsulating the semiconductor die, the sacrificial layer, and the conductive via with an encapsulant; planarizing the encapsulant to expose the conductive via and the sacrificial layer; removing the sacrificial layer using an etching process; and forming a second redistribution structure over the encapsulant and over the semiconductor die, wherein the second redistribution structure is electrically connected to the conductive via and to the semiconductor die, and wherein the second redistribution structure comprises an opening that exposes the sensor of the semiconductor die, after removing the sacrificial layer, a portion of the encapsulant overhangs the semiconductor die.
Regarding claim 11, the prior art does not teach a method comprising: forming a conductive via on a substrate; attaching a sensor device to the substrate; depositing a polymer material on the sensor device; depositing a molding material on the conductive via, the sensor device; and the polymer material; after depositing the molding material, removing the polymer material to expose the sensor device; depositing a dielectric material on the molding material, the conductive via, and the sensor device; removing a first portion of the dielectric material to expose a sensing region of the sensor device; and forming a metallization pattern on the dielectric material, wherein the metallization pattern physically and electrically contacts the conductive via and the sensor device, wherein the polymer material is deposited before attaching the sensor device to the substrate.
Prior Art
Relevant prior art: Chiang (US 10832985), Hsu (US 10269671), Chu (US 11289396), Tseng (US 11854927), Han (US 2013/0069252). Strothmann (US 2013/0221452), Mao (US 2017/0015548).
Conclusion
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/D.J.G/Examiner, Art Unit 2817
/KYOUNG LEE/Primary Examiner, Art Unit 2817