oiDETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Sato et al. (“Sato”), US 2023/0092244, in view of Park et al. (“Park”), US 2008/0258141, listed in the IDS dated 11/11/2025.
Regarding Claim 1, Sato discloses a method (700; Fig. 7; ¶¶ 0071-0075) comprising:
forming a first thin-film omega transistor (600; Fig. 6; ¶¶ 0046, 0066, 0071) comprising:
forming a gate fin (702; Fig. 7; ¶ 0071; see annotated Fig. 6 infra, fin 204) over a first dielectric layer (202; Fig. 6; ¶¶ 0046, 0071, “the supporting layer is typically non-conductive”), wherein the gate fin (204; Fig. 6; ¶ 0046 “one or more layers of metal”, ¶ 0067 “channel width can be further increased by increasing the height of the fin”) contacts (Fig. 6; ¶ 0037 “204 is formed over the support structure 202”) a top surface of the first dielectric layer (¶ 0037 “204 is formed over the support structure 202”; see annotated Fig. 6 infra) to form a first interface (in this instance a first interface is where gate fin 204 is on 202; see annotated Fig. 6 infra);
forming a first gate dielectric (704; Fig. 7; ¶ 0072) on sidewalls and a top surface of the gate fin (Fig. 7; ¶ 0072 “the gate dielectric may be deposited using a conformal deposition process”, see also 206 in figure 6);
depositing a first oxide semiconductor layer (706; Fig. 7; ¶¶ 0054, 0073 “the channel material” “may include a high mobility oxide semiconductor material”, see also 208 in figure 6) over the first gate dielectric (¶ 0073 “channel material conforms to the shape of the gate stack”), wherein the gate fin, the first gate dielectric, and the first oxide semiconductor layer collectively form a fin structure (¶ 0073 the “gate electrode, gate dielectric, and channel material form a transistor”);
forming a source region (708; Fig. 7; ¶¶ 0073, 0075 “forming S/D regions”) contacting first sidewalls and a first top surface of a first portion of the first oxide semiconductor layer (Figs. 6-7; ¶’s 0073, 0075, see figure 6 element 610); and
forming a drain region (708; Fig. 7; ¶¶ 0073, 0075 “forming S/D regions”) contacting second sidewalls and a second top surface of a second portion of the first oxide semiconductor layer (Figs. 6-7; ¶¶ 0073, 0075, see figure 6 the other element 610).
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Sato does not disclose wherein the first gate dielectric contacts the top surface of the first dielectric layer to form a second interface, and the first interface is joined to the second interface.
Park discloses wherein the first gate dielectric (44; Fig. 4; ¶ 0048 “gate insulating layer 44”) contacts (¶ 0048 “44…is formed on the substrate 40”) the top surface (Fig. 4; ¶ 0048 “44 covering laterals and an upper surface of the gate 42 is formed on the substrate 40”) of the first dielectric layer (40; Fig. 4; ¶ 0048 “substrate 40 can be an insulating substrate”) to form a second interface (Fig. 4; ¶ 0048 “44…is formed on the substrate 40” in this instance a second interface is where gate dielectric 44 is on 40), and the first interface (Fig. 4; ¶ “gate 42 is formed on a substrate 40” in this instance the first interface is where gate fin 42 is on 40) is joined to the second interface (Fig. 4).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Sato to have wherein the first gate dielectric contacts the top surface of the first dielectric layer to form a second interface, and the first interface is joined to the second interface, as taught by Park, in order to “ensure uniform device characteristics and increase stability” (Park ¶ 0015) to improve the reliability of the structure (Park ¶ 0015).
Regarding Claim 18, Sato discloses a structure (Fig. 6; ¶ 0066) comprising:
a first dielectric layer (202; Fig. 6; ¶ 0046 “the supporting layer is typically non-conductive”);
a thin-film omega transistor (600; Fig. 6; ¶ 0046; see annotated Fig. 6 supra) comprising:
a conductive fin (204; Fig. 6; ¶¶ 0046, 0067 “one or more layers of metal”, and “channel width can be further increased by increasing the height of the fin”) protruding higher than a top surface of the first dielectric layer (¶ 0046; see annotated Fig. 6 supra), wherein the conductive fin contacts (¶ 0037 “204 is formed over the support structure 202”; see annotated Fig. 6 supra) the first dielectric layer (¶ 0037 “204 is formed over the support structure 202”; see annotated Fig. 6 supra) to form an interface (Fig. 6 in this instance an interface is where conductive fin 204 contacts 202);
a gate dielectric (206; Fig. 6; ¶¶ 0047-0048) on the conductive fin (Fig. 6; ¶ 0048 “the gate dielectric” “coats the sides of the fin” “as well as the top of the fin”);
an oxide semiconductor layer (208; Fig. 6; ¶ 0054 “the channel material 208 may include a high mobility oxide semiconductor material”) on the gate dielectric (Fig. 6; ¶ 0050 “over the gate dielectric”), wherein the oxide semiconductor layer has a substantially omega-shaped cross-sectional-view shape (¶¶ 0050, 0067 “the channel material” “coats the sides of the fin” “as well as the top of the fin” “and the tops of” ”the base”, and “forms a continuous channel over the fin-shaped gate stack”), and
wherein the oxide semiconductor layer comprises:
a first sub-layer (¶ 0054 in this instance zinc oxide) having a first conductivity value (“a high mobility oxide semiconductor material”); and
a second sub-layer (¶ 0056 in this instance IGZO) over the first sub-layer (¶ 0054 “the channel material” “may include one or more of”), wherein the second sub-layer has a second conductivity value higher than the first conductivity value (¶ 0056 “higher carrier mobility than oxide semiconductors such as zinc oxide”);
a source region (610; Fig. 6; ¶ 0068) contacting (see annotated Fig. 6 supra) a first portion of the oxide semiconductor layer (Fig. 6; ¶ 0066 “two contacts” “wrap around different portions of the fin” “and extend across respective portions of the base”, plus “each of the contacts” “extends across all five channel surfaces”); and
a drain region (610; Fig. 6; ¶ 0068) contacting (see annotated Fig. 6 supra) a second portion of the oxide semiconductor layer (Fig. 6; ¶ 0066 “two contacts” “wrap around different portions of the fin” “and extend across respective portions of the base”, plus “each of the contacts” “extends across all five channel surfaces”); and
a dielectric layer (¶ 0069 “a dielectric spacer may be provided between” “the contacts 610a and 610b”) over and contacting a third portion of the oxide semiconductor layer (Fig. 6; ¶ 0066 “a portion of the fin” “and a portion of the base” “are between the two contacts” and “not covered by a contact”), wherein the third portion is between, and interconnects, the first portion and the second portion (Fig. 6; ¶ 0066 “a portion of the fin” “and a portion of the base” “are between the two contacts” and “not covered by a contact”).
Sato does not disclose wherein the gate dielectric comprises a first bottom at a same level as a second bottom of the conductive fin.
Park discloses wherein the gate dielectric (44; Fig. 4; ¶ 0048 “gate insulating layer 44”) comprises a first bottom (Fig. 4; ¶ 0048 “gate insulating layer 44…is formed on the substrate 40” in this instance a first bottom is where gate dielectric 44 is on 40) at a same level (Fig. 4) as a second bottom (Fig. 4; ¶ 0048 “gate 42 is formed on a substrate 40” in this instance a second bottom is where conductive fin 42 is on 40) of the conductive fin (42; Fig. 4; ¶ 0048 “gate 42”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Sato to have wherein the gate dielectric comprises a first bottom at a same level as a second bottom of the conductive fin, as taught by Park, in order to “ensure uniform device characteristics and increase stability” (Park ¶ 0015) to improve the reliability of the structure (Park ¶ 0015).
Claims 12, 15, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Sato et al. (“Sato”), US 2023/0092244, in view of Park et al. (“Park”), US 2008/0258141, listed in the IDS dated 11/11/2025, and further in view of Jung et al. (“Jung”), US 2009/0305468.
Regarding Claim 12, Sato discloses a structure (Fig. 6; ¶ 0066) comprising:
a first dielectric layer (202; Fig. 6; ¶ 0046 “the supporting layer is typically non-conductive”); and
a thin-film omega transistor (600; Fig. 6; ¶ 0046; see annotated Fig. 6 supra) comprising:
a gate fin (204; Fig. 6; ¶¶ 0046, 0067 “one or more layers of metal”, and “channel width can be further increased by increasing the height of the fin”) over the first dielectric layer (Fig. 6; ¶ 0046);
a gate dielectric (206; Fig. 6; ¶¶ 0047-0048) on sidewalls and a top surface of the gate fin (206; Fig. 6; ¶ 0048 “the gate dielectric” “coats the sides of the fin” “as well as the top of the fin”), wherein the gate dielectric comprises a bottom surface contacting (in this instance indirectly contacting) the first dielectric layer (Fig. 6);
an oxide semiconductor layer (208, Fig. 6; ¶ 0054 “the channel material” “may include a high mobility oxide semiconductor material”) over the gate dielectric (Fig. 6; ¶ 0050 “over the gate dielectric”);
a source region (610; Fig. 6; ¶ 0068) contacting (see annotated Fig. 6 supra) first sidewalls and a first top surface of a first portion of the oxide semiconductor layer (Fig. 6; ¶ 0066 “two contacts” “wrap around different portions of the fin” “and extend across respective portions of the base”, plus “each of the contacts” “extends across all five channel surfaces”); and
a drain region (610; Fig. 6; ¶ 0068) contacting (see annotated Fig. 6 supra) second sidewalls and a second top surface of a second portion of the oxide semiconductor layer (Fig. 6; ¶ 0066 “two contacts” “wrap around different portions of the fin” “and extend across respective portions of the base”, plus “each of the contacts” “extends across all five channel surfaces”); and
a second dielectric layer (¶ 0069 “a dielectric spacer may be provided between” “the contacts 610a and 610b”, the second dielectric layer is formed around the source region 610 and the drain region 610), wherein the source region and the drain region are in the second dielectric layer (¶ 0069 the second dielectric layer is “between” the source region and the drain region, therefore the source region and the drain region are in the second dielectric layer).
Sato does not disclose:
wherein the gate dielectric comprises a bottom surface contacting the first dielectric layer to form a first interface;
an etch stop layer over and contacting the oxide semiconductor layer;
the second dielectric layer is over the etch stop layer; and
wherein the source region and the drain region are in the etch stop layer.
Park discloses wherein the gate dielectric (44; Fig. 4; ¶ 0048 “gate insulating layer 44”) comprises a bottom surface (Fig. 4; ¶ 0048 “gate insulating layer 44…is formed on the substrate 40” in this instance a bottom surface is where gate dielectric 44 is on 40) contacting (Fig. 4; ¶ 0048 “gate insulating layer 44…is formed on the substrate 40” in this instance gate dielectric 44 is physically contacting 40) the first dielectric layer (40; Fig. 4; ¶ 0048 “40 can be an insulating substrate”) to form a first interface (Fig. 4 in this instance a first interface is where gate dielectric 44 is contacting first dielectric layer 40).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Sato to have wherein the gate dielectric comprises a bottom surface contacting the first dielectric layer to form a first interface, as taught by Park, in order to “ensure uniform device characteristics and increase stability” (Park ¶ 0015) to improve the reliability of the structure (Park ¶ 0015).
Sato as modified does not disclose:
an etch stop layer over and contacting the oxide semiconductor layer;
the second dielectric layer is over the etch stop layer; and
wherein the source region and the drain region are in the etch stop layer.
Jung discloses an etch stop layer (115; Fig. 9; ¶ 0049) over and contacting (Fig. 9; ¶ 0049 “on the exposed upper surface of the channel layer”) the oxide semiconductor layer (Fig. 9; ¶ 0049 “on the exposed upper surface of the channel layer”); wherein the source region and the drain region are in the etch stop layer (Fig. 9; ¶ 0048 the etch stop layer contacts the source region and the drain region, therefore the source region and the drain region are in the etch stop layer). In addition, Jung discloses that a dielectric layer (120; Fig. 9; ¶ 0038) is over the etch stop layer (Fig. 9, element 120 is located over element 115).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to incorporate the etch stop layer of Jung below the second dielectric layer of Sato as modified in order to provide additional electrical isolation between the source and drain electrodes” (¶ 0069 of Sato) lowering the power loss of the structure.
Regarding Claim 15, Sato as modified discloses wherein each of the source region and the drain region comprises:
an additional oxide semiconductor layer (Sato ¶ 0054 “if the transistor 200 is a TFT, the channel material” “may include one or more” layers) having a U-shaped cross-sectional-view shape (Sato Fig. 6; ¶ 0067 “the channel is not planar, but is folded over the gate electrode”); and
Sato as modified does not disclose a metallic layer between opposite sidewall portions of the additional oxide semiconductor layer.
Jung discloses a metallic layer (Jung ¶ 0037 the source and drain electrodes are “a multi-layer structure”, in this instance the metallic layer) between opposite sidewall portions of the additional oxide semiconductor layer (Jung Figs. 4 and 9; the inside/closest edges of the source and drain electrodes are between the opposite sidewall portions of the additional oxide semiconductor layer 116).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to incorporate metallic layer of Jung into the source and drain regions of Sato as modified in order to facilitate efficient power management.
Regarding Claim 19, Sato as modified discloses wherein the source region comprises:
an additional oxide semiconductor layer (Sato ¶ 0054 “if the transistor 200 is a TFT, the channel material” “may include one or more” layers) comprising:
a bottom portion over and contacting the oxide semiconductor layer (Sato ¶ 0054 the “one or more” layers of “the channel material”, in this instance a bottom portion of the additional oxide semiconductor material); and
sidewall portions over, and connecting to opposite ends of, the bottom portion (Sato ¶ 0054 the “one or more” layers of “the channel material”, in this instance sidewall portions of the additional oxide semiconductor material; see also Sato ¶ 0067 “the channel is not planar, but is folded over the gate electrode”); and
Sato as modified does not disclose a metallic region over the bottom portion and between the sidewall portions.
Jung discloses a metallic region (Jung ¶ 0037 the source and drain electrodes are “a multi-layer structure”, in this instance the metallic layer) over the bottom portion and between opposite sidewall portions (Jung Figs. 4 and 9; the inside/closest edges of the source and drain electrodes are between the opposite sidewall portions of the additional oxide semiconductor layer 116).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to incorporate metallic layer of Jung into the source and drain regions of Sato as modified in order to facilitate efficient power management.
Claims 2-4 are rejected under 35 U.S.C. 103 as being unpatentable over Sato et al. (“Sato”), US 2023/0092244 and Park et al. (“Park”), US 2008/0258141, as applied to Claim 1 supra, and further in view of Dewey et al. (“Dewey”), US 2020/0411692.
Regarding Claim 2, Sato as modified does not disclose forming a Fin Field-Effect Transistor (FinFET) on a semiconductor substrate, wherein the first dielectric layer is overlying the semiconductor substrate and the FinFET.
Dewey discloses forming (Fig. 1; ¶ 0038) a Fin Field-Effect Transistor (FinFET) (1581; Fig. 15; ¶ 0069) on a semiconductor substrate (1501), wherein the first dielectric layer is overlying the semiconductor substrate and the FinFET (Fig. 15; ¶ 0071).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Sato as modified to include the finFET of Dewey in order to facilitate a compact circuit to improve reliability.
Regarding Claim 3, Sato as modified does not disclose the first thin-film omega transistor overlaps the FinFET.
Dewey discloses the first thin-film omega transistor overlaps the FinFET (Fig. 15; ¶ 0071).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Sato as modified to include the first thin-film omega transistor overlapping the FinFET, as disclosed by Dewey, in order to facilitate a compact circuit to improve reliability.
Regarding Claim 4, Sato as modified does not disclose wherein the first thin-film omega transistor and the FinFET are of opposite conductivity types, and the method further comprises:
electrically interconnecting the first thin-film omega transistor and the FinFET to form a complementary device.
Dewey discloses wherein the first thin-film omega transistor and the FinFET are of opposite conductivity types (Dewey ¶¶ 0044, 0069; note also ¶ 0083 of Sato), and the method further comprises:
electrically interconnecting the first thin-film omega transistor and the FinFET to form a complementary device (Fig. 15; ¶ 0070).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Sato as modified to form the complementary device of Dewey in order to facilitate a compact circuit to improve reliability.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Sato et al. (“Sato”), US 2023/0092244 and Park et al. (“Park”), US 2008/0258141, as applied to Claim 1 supra, and further in view of Choi et al (“Choi”), CN 102024842.
Regarding Claim 6, Sato as modified does not teach wherein the forming the source region and the drain region comprises:
forming a second dielectric layer on the fin structure;
forming a source opening and a drain opening exposing the first portion and the second portion, respectively, of the first oxide semiconductor layer, wherein the source region and the drain region are formed in the source opening and the drain opening, respectively.
Choi discloses wherein the forming the source region and the drain region comprises:
forming a second dielectric layer (150; FIG. 6; ¶ 0055) on the fin structure;
forming a source opening (153) and a drain opening (154) exposing the first portion and the second portion, respectively, of the first oxide semiconductor layer (141), wherein the source region (163) and the drain region (164) are formed in the source opening and the drain opening, respectively (Fig. 6).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Sato as modified to include the forming steps of Choi in order to electrically isolate the source and drain regions and improve the reliability of the thin film transistor.
Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Sato et al. (“Sato”), US 2023/0092244 and Park et al. (“Park”), US 2008/0258141, as applied to Claim 1 supra, and further in view of Jeong et al. (“Jeong”), US 2012/0052609.
Regarding Claim 7, Sato as modified discloses wherein one of the source region and the drain region (Sato ¶ 0065 the material composition of one element 610 “may be different from the material composition of the second” element 610, therefore one of the source region and the drain region) comprises:
an additional oxide semiconductor layer (Sato ¶ 0065, 0068 element 610 “may include one or more…oxides”); and
a metallic layer (Sato ¶ 0065 “one or more layers of metal and/or metal alloys may be used to form” element 610) on the additional oxide semiconductor layer.
Sato as modified does not disclose that the additional oxide semiconductor layer has a higher conductivity value than the first oxide semiconductor layer.
Jeong discloses wherein the additional oxide semiconductor layer has a higher conductivity value than the first oxide semiconductor layer (Jeong, ¶¶ 0042, 0045 “oxide semiconductor layer 13 may include a GaInZnO (GIZO) bilayer structure including a lower layer 13a and an upper layer 13b”, and “in the GIZO bilayer structure, the In concentration of the lower layer 13a may be higher than the In concentration of the upper layer 13b”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Sato as modified to have the oxide semiconductor bilayer of Jeong in order to “ensure semiconducting characteristics” and “obtain desired electrical characteristics” (Jeong, ¶ 0051) to reduce the power loss of the structure.
Regarding Claim 8, Sato as modified does not disclose wherein both of the first oxide semiconductor layer and the additional oxide semiconductor layer comprise indium oxide, and wherein the additional oxide semiconductor layer has a higher indium atomic percentage than the first oxide semiconductor layer.
Jeong discloses wherein both of the first oxide semiconductor layer and the additional oxide semiconductor layer comprise indium oxide (Jeong, ¶ 0042 “upper layer 13b may have a different indium (In) concentration than the lower layer 13a ”), and wherein the additional oxide semiconductor layer has a higher indium atomic percentage than the first oxide semiconductor layer (Jeong, ¶ 0051 “the In concentration of the GIZO lower layer 13a may be about 40 to about 60 at. %, and the In concentration of the GIZO upper layer 13b may be about 30 to about 50 at. %”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Sato as modified to have the atomic percentage characteristics of the oxide semiconductor bilayer of Jeong in order to “ensure semiconducting characteristics” and “obtain desired electrical characteristics” (Jeong, ¶ 0051) to reduce the power loss of the structure.
Claims 9-11 are rejected under 35 U.S.C. 103 as being unpatentable over Sato et al. (“Sato”), US 2023/0092244 and Park et al. (“Park”), US 2008/0258141, as applied to Claim 1 supra, and further in view of Shi et al. (“Shi”), US 2017/0141127, cited in IDS filed November. 12, 2024.
Regarding Claim 9, Sato as modified does not disclose forming a second thin-film omega transistor immediately neighboring the first thin-film omega transistor, wherein the second thin-film omega transistor comprises a second gate dielectric and a second oxide semiconductor layer on the second gate dielectric, wherein the first thin-film omega transistor and the second thin-film omega transistor are discrete transistors electrically and signally disconnected from each other, and wherein the first oxide semiconductor layer and the second oxide semiconductor layer are portions of a continuous oxide semiconductor layer.
Shi discloses forming a second thin-film omega transistor immediately neighboring the first thin-film omega transistor (Fig. 9; ¶¶ 0079, 0086), wherein the second thin-film omega transistor comprises a second gate dielectric (right side of element 3) and a second oxide semiconductor layer (43) on the second gate dielectric, wherein the first thin-film omega transistor and the second thin-film omega transistor are discrete transistors electrically and signally disconnected from each other (gates 21, 23 are electrically and signally disconnected), and wherein the first oxide semiconductor layer and the second oxide semiconductor layer are portions of a continuous oxide semiconductor layer (41, 42, 43).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Sato as modified to include the second thin film transistor of Shi in order to facilitate a compact circuit.
Regarding Claim 10, Sato as modified does not disclose forming a second thin-film omega transistor immediately neighboring the first thin-film omega transistor, wherein the second thin-film omega transistor comprises a second gate dielectric and a second oxide semiconductor layer, wherein the first thin-film omega transistor and the second thin-film omega transistor are discrete transistors electrically and signally disconnected from each other, and wherein the first oxide semiconductor layer and the second oxide semiconductor layer are separated from each other by an etch stop layer and an additional dielectric layer.
Shi discloses forming a second thin-film omega transistor immediately neighboring the first thin-film omega transistor (Fig. 1; ¶ 0009), wherein the second thin-film omega transistor comprises a second gate dielectric (right side of 300; Fig. 2; ¶ 0007) and a second oxide semiconductor layer (440) wherein the first thin-film omega transistor and the second thin-film omega transistor are discrete transistors electrically and signally disconnected from each other (gates 210, 230 are electrically and signally disconnected), and wherein the first oxide semiconductor layer and the second oxide semiconductor layer are separated from each other by an etch stop layer (bottom portion of 500) and an additional dielectric layer (top portion of 500).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Sato as modified to include the second thin film transistor of Shi in order to facilitate a compact circuit.
Regarding Claim 11, Sato as modified does not disclose wherein the first gate dielectric and the second gate dielectric are portions of a continuous dielectric layer.
Shi discloses wherein the first gate dielectric and the second gate dielectric are portions of a continuous dielectric layer (300; Fig. 2; ¶ 0007).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Sato as modified to include the continuous dielectric layer of Shi in order to facilitate a compact circuit.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Sato et al. (“Sato”), US 2023/0092244, Park et al. (“Park”), US 2008/0258141, and Jung et al. (“Jung”), US 2009/0305468 as applied to Claim 12 supra, and further in view of Dewey et al. (“Dewey”), US 2020/0411692.
Regarding Claim 13, Sato as modified does not disclose a Fin Field-Effect Transistor (FinFET) on a semiconductor substrate, wherein the first dielectric layer is over the semiconductor substrate and FinFET, and wherein the thin-film omega transistor overlaps the FinFET.
Dewey discloses a Fin Field-Effect Transistor (FinFET) (1581; Fig. 15; ¶ 0069) on a semiconductor substrate (1501), wherein the first dielectric layer is over the semiconductor substrate and FinFET (Fig. 15; ¶0071), and wherein the thin-film omega transistor overlaps the FinFET (Fig. 15; ¶0071).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Sato as modified to include the finFET of Dewey in order to facilitate a compact circuit to improve reliability.
Claims 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Sato et al. (“Sato”), US 2023/0092244, Park et al. (“Park”), US 2008/0258141, and Jung et al. (“Jung”), US 2009/0305468 as applied to Claim 15 supra, and further in view of Jeong et al. (“Jeong”), US 2012/0052609.
Regarding Claim 16, Sato as modified does not disclose that the additional oxide semiconductor layer has a higher conductivity value than the oxide semiconductor layer.
Jeong discloses wherein the additional oxide semiconductor layer has a higher conductivity value than the oxide semiconductor layer (Jeong, ¶¶ 0042, 0045 “oxide semiconductor layer 13 may include a GaInZnO (GIZO) bilayer structure including a lower layer 13a and an upper layer 13b”, and “in the GIZO bilayer structure, the In concentration of the lower layer 13a may be higher than the In concentration of the upper layer 13b”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Sato as modified to have the oxide semiconductor bilayer of Jeong in order to “ensure semiconducting characteristics” and “obtain desired electrical characteristics” (Jeong, ¶ 0051) to reduce the power loss of the structure.
Regarding Claim 17, Sato as modified does not disclose wherein both of the oxide semiconductor layer and the additional oxide semiconductor layer comprise indium oxide, and wherein the additional oxide semiconductor layer has a higher indium atomic percentage than the oxide semiconductor layer.
Jeong discloses wherein both of the oxide semiconductor layer and the additional oxide semiconductor layer comprise indium oxide (Jeong, ¶ 0042 “upper layer 13b may have a different indium (In) concentration than the lower layer 13a ”), and wherein the additional oxide semiconductor layer has a higher indium atomic percentage than the oxide semiconductor layer (Jeong, ¶ 0051 “the In concentration of the GIZO lower layer 13a may be about 40 to about 60 at. %, and the In concentration of the GIZO upper layer 13b may be about 30 to about 50 at. %”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Sato as modified to have the atomic percentage characteristics of the oxide semiconductor bilayer of Jeong in order to “ensure semiconducting characteristics” and “obtain desired electrical characteristics” (Jeong, ¶ 0051) to reduce the power loss of the structure.
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Sato et al. (“Sato”), US 2023/0092244, Park et al. (“Park”), US 2008/0258141, and Jeong et al. (“Jeong”), US 2012/0052609, as applied to Claim 7 supra.
Regarding claim 21, Sato discloses the conductivity types of the first oxide semiconductor layer and the additional oxide semiconductor layer (Sato ¶ 0054 “channel material” may be “N- or P-type”, ¶ 0065 element 610 may have “an N-type dopant or a P-type dopant”).
Sato as modified lacks specifically stating wherein the first oxide semiconductor layer and the additional oxide semiconductor layer are doped to a same conductivity type.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Sato to have the first oxide semiconductor layer and the additional oxide semiconductor layer are doped to a same conductivity type as there are only two options, the layers could be different or they could be the same, therefore, it would be obvious to try each of the two combinations and have a final product where each of the conductivity types are the same to have the semiconductor device function effectively.
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Sato et al. (“Sato”), US 2023/0092244, Park et al. (“Park”), US 2008/0258141, and Jung et al. (“Jung”), US 2009/0305468 as applied to Claim 12 supra.
Regarding Claim 23, Sato as modified discloses wherein the gate fin (Park 42; Fig. 4; ¶ 0048) forms a second interface (Park Fig. 4; ¶ 0048 “gate 42 is formed on a substrate 40” in this instance a second interface is where gate fin 42 contacts 40) with the first dielectric layer (Park 40; Fig. 4; ¶ 0048).
Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Sato et al. (“Sato”), US 2023/0092244 and Park et al. (“Park”), US 2008/0258141, as applied to Claim 18 supra.
Regarding Claim 18, Sato as modified discloses wherein the gate dielectric (Park 44; Fig. 4; ¶ 0048) contacts the top surface (Park Fig. 4; ¶ 0048 “gate insulating layer 44…is formed on the substrate 40” in this instance the gate dielectric 44 physically contacts 40) of the first dielectric layer (Park 40; Fig. 4; ¶ 0048) to form an additional interface (Park Fig. 4 in this instance an additional interface is where gate dielectric 44 contacts 40), and the interface is joined to the additional interface (Park Fig. 4).
Response to Arguments
The Applicant submits (pages 7-8) that amended Claim 18 is allowable over Sato. As explained supra, amended independent Claim 18 is now rejected as being unpatentable over Sato et al. (“Sato”), US 2023/0092244, in view of Park et al. (“Park”), US 2008/0258141, listed in the IDS dated 11/11/2025. Independent Claim 18 is not patentable for at least the reasons stated supra.
Independent Claims 1, 12, and 18 are rejected for at least the reasons explained supra. Dependent Claims 2-4, 6-11, 13, 15-17, 19, 21, and 23-24 are rejected for at least the reasons stated supra. The new rejections are presented based on the new interpretation of Park et al. (“Park”), US 2008/0258141, listed in the IDS dated 11/11/2025, presented supra.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Rose Keagy whose telephone number is (571) 270-3455. The examiner can normally be reached Mon-Fri. 8am-5pm (CT).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff Natalini can be reached at (571) 272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/R.K./Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818