DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
Acknowledgement is made of the amendment received on 5/26/2026. Claims 1-12, 14-15, and 21-26 are pending in this application. Claims 1, 11, 21, and 23 are amended.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 7-8, 10, 21-23, and 26 are rejected under 35 U.S.C. 103 as being unpatentable Yu et al. (US 2020/0043896: hereinafter ‘Yu’) in view of Hou et al. (US 2022/0149002; hereinafter ‘Hou’).
Regarding claim 1, Yu teaches a method [0007] comprising:
directly bonding (shown in FIG. 14, [0043]) a first wafer (W1) to a second wafer (W2),
wherein the first wafer (W1) comprises a first interconnect structure (a first interconnect structure including 1200, 1300, and 1400, [0013]; hereinafter ‘IS1’) on a first substrate (1100),
wherein the second wafer (W2) comprises a second interconnect structure (a second interconnect structure including 5200, 5300, and 5400, [0024]; hereinafter ‘IS2’) on a second substrate (5100),
wherein the bonding electrically connects the first interconnect structure of the first wafer (IS1) to the second interconnect structure of the second wafer (IS2),
wherein the second interconnect structure (IS2) comprises a plurality of conductive lines (5210 of 5200, FIGS. 11 and 14, [0026]) in a plurality of dielectric layers (5220 of 5200 is a multilayer dielectric structure that has the same structure as 220, FIGS. 1 and 14, [0015, 0026]);
forming (shown in FIG. 14, [0043]) a plurality of through substrate vias (5120, [0025]) extending fully through the second substrate (5100),
wherein the plurality of through substrate vias physically contact surfaces of the plurality of conductive lines (5120 physically contact respective surfaces of 5210);
directly bonding (shown in FIG. 15, [0045]) a plurality of first semiconductor devices (200) to the second wafer (W2),
wherein the bonding electrically connects the plurality of first semiconductor devices (200) to the second interconnect structure (IS2) by the plurality of through substrate vias (5120);
encapsulating (shown in FIG. 16, [0046]) the plurality of first semiconductor devices (200) with a first encapsulant (3000); and
forming (shown in FIG. 17, [0047]) solder bumps (7000) over the plurality of first semiconductor devices (200).
Yu does not teach the method comprising: thinning the second substrate; and after thinning the second substrate, forming a plurality of through substrate vias extending fully through at least one dielectric layer of the plurality of dielectric layers of the second interconnect structure.
Hou teaches a method [0003] comprising:
thinning the second substrate (thinning the second substrate 708, [0059]); and
after thinning the second substrate, forming a plurality of through substrate vias (forming a through substrate vias 714, FIG. 11, [0059]) extending fully through at least one dielectric layer of the plurality of dielectric layers of the second interconnect structure (714 extending fully through 740 of the second interconnect structure that includes 740, 760, 770, 780, and 788, FIG. 11, [0038, 0042]).
As taught by Hou, one of ordinary skill in the art would utilize and modify the above teaching into Yu to obtain and achieve the method comprising: thinning the second substrate; and after thinning the second substrate, forming a plurality of through substrate vias extending fully through at least one dielectric layer of the plurality of dielectric layers of the second interconnect structure as claimed, because it provides backside electrical access to the buried metal interconnect structures and formed through substrate conductive paths terminating in external metal bonding pads for subsequent electrical connection and bonding [0061-0062].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Hou in combination with Yu due to the above reason.
Regarding claim 2, Yu in view of Hou teaches the method of claim 1, wherein directly bonding the first wafer to the second wafer comprises dielectric-to-dielectric bonding and metal-to-metal bonding (Yu: W1 and W2 are bonded with a dielectric-to-dielectric bond and a metal-to-metal bond, [0043]).
Regarding claim 3, Yu in view of Hou teaches the method of claim 1, wherein sidewalls of the second wafer are free of the first encapsulant (Yu: 3000 is formed over W2, FIG. 16, [0046]).
Regarding claim 4, Yu in view of Hou teaches the method of claim 1 further comprising performing a singulation process between two neighboring first semiconductor devices of the plurality of first semiconductor devices (Yu: singulation process is performed to cut 3000 between two neighboring 200, FIGS. 17 and 18, [0047]).
Regarding claim 5, Yu in view of Hou teaches the method of claim 1, wherein directly bonding the plurality of first semiconductor devices to the second wafer comprises forming (Yu: shown in FIG. 16, [0040]) a first bonding layer (4100) and first bonding pads (4200) on the second wafer and directly bonding the plurality of first semiconductor devices to the first bonding layer and the first bonding pads (shown in FIG. 16).
Regarding claim 7, Yu in view of Hou teaches the method of claim 1, wherein the through substrate vias extend from an outer surface of the second substrate to a conductive feature within the second interconnect structure of the second wafer (Yu: 5120 extends from RS2 of 5100 to 5400 within IS2, FIGS. 11 and 14, [0025]).
Regarding claim 8, Yu in view of Hou teaches the method of claim 1,
after directly bonding the plurality of first semiconductor devices to the second wafer, forming (Yu: shown in FIG. 16) through vias (212, [0046]) in the first semiconductor devices of the plurality of first semiconductor devices; and
forming (shown in FIG. 17) a second bonding layer (6100”, [0047]) and second bonding pads (6200”) on the plurality of first semiconductor devices.
Regarding claim 10, Yu in view of Hou teaches the method of claim 8, but does not explicitly teach the method further comprising directly bonding a fourth wafer to the second bonding layer and the second bonding pads.
Yu, however, teaches the method further comprising directly bonding (shown in FIG. 11, [0040]) a fourth wafer (W2’) to the second bonding layer and the second bonding pads (4100 and 4200 of FIG. 11, which are functionally corresponding to 6100” and 6200” formed on 200 in FIG. 17).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to control and optimize the method of Yu by applying further comprising directly bonding a fourth wafer to the second bonding layer and the second bonding pads as claimed, because additionally stacking another wafer over a wafer-over-semiconductor device structure through hybrid bonding enables miniaturization, reduces overall weight, simplifies assembly processes, lower production costs, and enhances electrical performance [0055]. Further, it has been held that that rearranging part of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Regarding claim 21, Yu teaches a method [0004] comprising:
bonding (shown in FIG. 1) a plurality of first semiconductor devices (200, [0012]) to a first interconnect structure (a first interconnect structure including 1200, 1300, and 1400, [0013]; hereinafter ‘IS1’) using a first direct bonding process (a first bonding process between 200 and W1, hereinafter ‘FB1’);
depositing (shown in FIG. 2) an encapsulant (3000’, [0020]) that surrounds each first semiconductor device of the plurality of first semiconductor devices (each of 200);
after depositing the encapsulant, forming (shown in FIG. 3) a respective through via (212, which are exposed at RS, thereby forming through vis, [0021]) in each first semiconductor device of the plurality of first semiconductor devices (each of 200);
forming (shown in FIG. 4) a first bonding layer (4000, [0023]) extending over the encapsulant (3000) and the plurality of first semiconductor devices (200);
forming (shown in FIG. 4) a plurality of first bonding pads (4200, [0023]) in the first bonding layer (4000), wherein each first bonding pad (4000) directly contacts the respective through via (212) of a respective first semiconductor device (200);
placing (shown in FIG. 5) a wafer (W2, [0024]) on the first bonding layer (4000),
wherein the wafer (W2) comprises a second interconnect structure (a second interconnect structure including 5200, 5300, and 5400, [0024]; hereinafter ‘IS2’) on a semiconductor substrate (5100, [0024]),
wherein the second interconnect structure (IS2) comprises a plurality of conductive features (5210 of 5200, FIGS. 11 and 14, [0026]);
performing (shown in FIG. 5) a second direct bonding process (a second bonding process between 200 and W2, [0027]; hereinafter ‘FB2’) that directly bonds the second interconnect structure (IS2) to the first bonding layer (4000) and to the plurality of first bonding pads (4200); and
forming (shown in FIG. 5) a plurality of through substrate vias (5120, [0025]) in the semiconductor substrate (5100),
wherein the plurality of through substrate vias (5120) directly contact the plurality of conductive features (5210) of the second interconnect structure (IS2),
wherein at least one through substrate via of the plurality of through substrate vias (one of 5120) continuously extends a vertical distance from a surface of the semiconductor substrate to a conductive features of the plurality of conductive features (5120 continuously extends a vertical distance from RS2 of 5100 to 5210, FIG. 5, [0025]).
Yu does not teach the method comprising: after performing the second direct bonding process, forming a plurality of through substrate vias in the semiconductor substrate, wherein the vertical distance of the through substrate vias is greater than a thickness of the semiconductor substrate.
Hou teaches a method [0003] comprising:
after performing the second direct bonding process (performing the first metal-to-metal bonding process between the first bonding pads 788 and the second bonding pads 988, FIG. 9, [0053]),
forming a plurality of through substrate vias in the semiconductor substrate (forming a through substrate via 714 in 708, FIG. 11, [0059]),
wherein the vertical distance of the through substrate vias is greater than a thickness of the semiconductor substrate (a vertical distance of 714 is greater than a thickness of 708, FIG. 11).
As taught by Hou, one of ordinary skill in the art would utilize and modify the above teaching into Yu to obtain and achieve the method comprising: after performing the second direct bonding process, forming a plurality of through substrate vias in the semiconductor substrate, wherein the vertical distance of the through substrate vias is greater than a thickness of the semiconductor substrate as claimed, because it provides backside electrical access to the buried metal interconnect structures and formed through substrate conductive paths terminating in external metal bonding pads for subsequent electrical connection and bonding [0061-0062].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Hou in combination with Yu due to the above reason.
Regarding claim 22, Yu in view of Hou teaches the method of claim 21, wherein sidewalls of the wafer are free of the encapsulant (Yu: sidewalls of W2 are free of 3000, which is formed for 3000’ in FIG. 2, FIG. 5, [0021]).
Regarding claim 23, Yu in view of Hou teaches the method of claim 21 further comprising:
forming (Yu: shown in FIG. 6) a second bonding layer (6000, [0028]), extending over the semiconductor substrate (5100); and
forming (shown in FIG. 6) a plurality of second bonding pads (6200, [0028]) in the second bonding layer (6000), wherein each second bonding pad (6200) directly contacts a respective through substrate via (5120).
Regarding claim 26, Yu in view of Hou teaches the method of claim 21, wherein surfaces of the plurality of through substrate vias and the semiconductor substrate are level (Yu: surfaces of 5120 and 5100 are level, FIG. 5).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable Yu (US 2020/0043896) in view of Hou (US 2022/0149002), and further in view of Su et al. (US 2017/0133351; hereinafter ‘Su’).
Regarding claim 6, Yu in view of Hou teaches the method of claim 1, but does not teach the method further comprising directly bonding a third wafer to the first wafer, wherein the bonding electrically connects a third interconnect structure of the first wafer to the first interconnect structure of the first wafer.
Su teaches a method [0038] further comprising directly bonding (FIG. 16, [0043]) a third wafer (lower layer of device die 534; hereinafter ‘L534’) to the first wafer (middle layer of 534; hereinafter ‘M534’), wherein the bonding electrically connects a third interconnect structure of the first wafer (solder regions 536 between L534 and) to the first interconnect structure of the first wafer (536 over M534).
As taught by Su, one of ordinary skill in the art would utilize and modify the above teaching into Yu in view of Hou to obtain and achieve the method further comprising directly bonding a third wafer to the first wafer, wherein the bonding electrically connects a third interconnect structure of the first wafer to the first interconnect structure of the first wafer as claimed, because the structure is vertically stacked, the package achieves higher integration without increasing the footprint [0044]. Further, it has been held that that rearranging part of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Su in combination with Yu in view of Hou due to the above reason.
Claims 9 and 24 are rejected under 35 U.S.C. 103 as being unpatentable Yu (US 2020/0043896) in view of Hou (US 2022/0149002), and further in view of Kim et al. (US 2018/0006006; hereinafter ‘Kim’).
Regarding claim 9, Yu in view of Hou teaches the method of claim 8, but does not teach the method further comprising: directly bonding a plurality of second semiconductor devices to the second bonding layer and the second bonding pads; and encapsulating the plurality of second semiconductor devices with a second encapsulant.
Kim teaches a method [0010] further comprising:
directly bonding (shown in FIG. 7) a plurality of second semiconductor devices (C3, [0049]) to the second bonding layer (144, [0050]), and the second bonding pads (238, [0041]); and
encapsulating (shown in FIG. 8) the plurality of second semiconductor devices with a second encapsulant (160, [0051]).
As taught by Kim, one of ordinary skill in the art would utilize and modify the above teaching into Yu in view of Hou to obtain and achieve the method further comprising: directly bonding a plurality of second semiconductor devices to the second bonding layer and the second bonding pads; and encapsulating the plurality of second semiconductor devices with a second encapsulant as claimed, because the structure is vertically stacked, semiconductor packages achieve higher integration and miniaturization to meet the increasing demands for multifunctional electronic devices [0003]. Further, it has been held that that rearranging part of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Kim in combination with Yu in view of Hou due to the above reason.
Regarding claim 24, Yu in view of Hou teaches the method of claim 23, but does not teach the method further comprising bonding a plurality of second semiconductor devices to the second bonding layer and to the plurality of second bonding pads using a third direct bonding process.
Kim teaches a method [0083] further comprising bonding (shown in FIG. 11) a plurality of second semiconductor devices (C2 of M2, [0084]) to the second bonding layer (142 of M2, [0043]) and to the plurality of second bonding pads (138, FIG. 4, [0041]) using a third direct bonding process (a bonding process between C1 and C2)
As taught by Kim, one of ordinary skill in the art would utilize and modify the above teaching into Yu in view of Hou to obtain and achieve the method further comprising bonding a plurality of second semiconductor devices to the second bonding layer and to the plurality of second bonding pads using a third direct bonding process as claimed, because the structure is vertically stacked, semiconductor packages achieve higher integration and miniaturization to meet the increasing demands for multifunctional electronic devices [0003]. Further, it has been held that that rearranging part of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Kim in combination with Yu in view of Hou due to the above reason.
Claims 11, 14-15, and 25 are rejected under 35 U.S.C. 103 as being unpatentable Yu (US 2020/0043896) in view of Hou (US 2022/0149002), and further in view of Yu et al. (US 2020/0381397; hereinafter ‘Yu397’).
Regarding claim 11, Yu teaches a method [0007] comprising:
forming (shown in FIG. 14, [0043]) a first dielectric layer (5300, [0043]) on a first side of a first semiconductor substrate (WS1, [0043]);
forming (shown in FIG. 14) first conductive features (5210, [0026]) over the first dielectric layer (5300);
forming (shown in FIG. 14) first bonding pads (5400, [0043]) over the first conductive features (5210);
forming (shown in FIG. 14) second bonding pads (1400) on a first side of a second semiconductor substrate (WS2);
bonding (shown in FIG. 14) the first bonding pads (5400) to the second bonding pads (1400) using a first metal-to-metal bonding process (a metal-to-metal bond, [0043]);
depositing first conductive material (depositing conductive material for through semiconductor vias 5120 in 5100, [0037, 0043]; hereinafter ‘CM5120’) in the first openings (openings in 5100 for 5120, [0037]; hereinafter ‘O5120’) and on the first conductive features (5210);
performing a first planarization process (performing a planarization process, [0037]; hereinafter ‘PP1’) on the first conductive material (CM5120) to form first through vias (5120) within the first semiconductor substrate (5100),
wherein after performing the first planarization process (PP1) the second side of the first semiconductor substrate (the surface of the semiconductor substrate 5100 facing away from the bonding layer 4000’, [0044]; hereinafter ‘5100SS’) is free of the first conductive material (since the planarization process removes excess conductive material such that CM5120 remains only within the via openings O5120 and not on 5100SS, as evidenced by the exposed 5100SS prior to formation of bonding layer 4100, FIG. 14);
forming (shown in FIG. 14) third bonding pads (4200, [0044]) on the second side of the first semiconductor substrate (5100SS),
wherein the third bonding pads (4200) are electrically connected to the first through vias (5120);
bonding (shown in FIG. 15, [0045]) a semiconductor die (200, [0045]) to the third bonding pads (4200) using a second metal-to-metal bonding process (a metal-to-metal bond, [0045]);
after performing the second metal-to-metal bonding process, laterally surrounding (shown in FIG. 16, [0046]) the semiconductor die (200) with an encapsulant (3000, [0046]); and
forming (shown in FIG. 16, [0046]) second through vias (212, [0046]) in the semiconductor die (200); and
depositing second conductive material (depositing conductive material for through semiconductor vias 212 in 210, [0037, 0046]; hereinafter ‘CM212’) in the second openings (openings in 210 for 212, [0037]; hereinafter ‘O212’) to form second through vias (212) in the semiconductor die (200).
Yu does not teach the method comprising: after performing the first metal-to-metal bonding process forming first openings in a second side of the first semiconductor substrate that extend completely through the first semiconductor substrate and completely through the first dielectric layer, wherein the first openings expose the first conductive features.
Hou teaches a method [0003] comprising:
after performing the first metal-to-metal bonding process (performing the first metal-to-metal bonding process between the first bonding pads 788 and the second bonding pads 988, FIG. 9, [0053]) forming first openings (forming first openings for through substrate via 714, FIG. 11, [0059]; hereinafter ‘O714’) in a second side of the first semiconductor substrate (a backside of 708, [0059])
that extend completely through the first semiconductor substrate (O714 extends completely through 708) and completely through the first dielectric layer (O714 extends completely through 740, [0060]),
wherein the first openings expose the first conductive features (expose 780 before filling with 714L and 714C, [0061]).
As taught by Hou, one of ordinary skill in the art would utilize and modify the above teaching into Yu to obtain and achieve the method comprising: after performing the first metal-to-metal bonding process forming first openings in a second side of the first semiconductor substrate that extend completely through the first semiconductor substrate and completely through the first dielectric layer, wherein the first openings expose the first conductive features as claimed, because it provides backside electrical access to the buried metal interconnect structures and formed through substrate conductive paths terminating in external metal bonding pads for subsequent electrical connection and bonding [0061-0062].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Hou in combination with Yu due to the above reason.
Yu in view of Hou does not teach the method comprising: after performing the second metal-to-metal bonding process, laterally surrounding the semiconductor die and the first semiconductor substrate with an encapsulant; after laterally surrounding the semiconductor die and the first semiconductor substrate with an encapsulant.
Yu397 teaches a method [0009] comprising: after performing the second metal-to-metal bonding process (performing metal-to-metal bonding between bond pads 160 of package 262’ and bond pads 342 of wafer 310 (310’ of FIG. 16), FIG. 9, [0035-0036]), laterally surrounding the semiconductor die and the first semiconductor substrate with an encapsulant (350, [0044]; laterally surrounding 262’ and laterally surrounding 320 of 310’ with 350).
As taught by Yu397, one of ordinary skill in the art would utilize and modify the above teaching into Yu in view of Hou to obtain and achieve the method comprising: after performing the second metal-to-metal bonding process, laterally surrounding the semiconductor die and the first semiconductor substrate with an encapsulant; after laterally surrounding the semiconductor die and the first semiconductor substrate with an encapsulant as claimed, because the lateral encapsulant, being disposed flush with the periphery of the semiconductor die and the underlying substrate serves to protects the wafer and the bonded devices during subsequent wafer-level processes, thereby enhancing process robustness and improving overall manufacturing yield [0031].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Yu397 in combination with Yu in view of Hou due to the above reason.
Although Yu in view of Hou and Yu397 does not explicitly teach the method comprising: after laterally surrounding the semiconductor die and the first semiconductor substrate with an encapsulant, forming second openings in the semiconductor die; and depositing second conductive material in the second openings to form second through vias in the semiconductor die.
Yu teaches second through vias 212 located in semiconductor die 200.
Yu397 teaches that laterally encapsulating the semiconductor die 262’ and the semiconductor substrate 320 with the encapsulant 360 and subsequently forming through-vias 352 (FIG. 16, [0044]).
Hou further teaches that, after performing metal-to-metal bonding, through-vias 714 are formed by forming backside openings through a semiconductor substrate 708 and dielectric material layer 740 to expose buried conductive features 780 and depositing conductive material in the openings to form conductive through substrate via structures 714 (FIG. 11, [0059-0062]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to apply Hou’s post-bonding backside via process to Yu’s semiconductor die after the lateral encapsulation taught by Yu 397, because the lateral encapsulant protects the wafer and bonded devices during subsequent wafer-level processes, and the later through-via formation-performed at the final stage after bonding-achieves better alignment of the conductive path, thereby enhancing electrical interconnection while maintaining package integrity and yield.
Regarding claim 14, Yu in view of Hou and Yu397 teaches the method of claim 11 further comprising, after laterally surrounding the semiconductor die and the first semiconductor substrate with the encapsulant, performing a second trimming process to remove encapsulant from sidewalls of the first semiconductor substrate (Yu: after forming 3000, a planarization process is performed to remove excess encapsulant from the sidewall of 5100, [0021]).
Regarding claim 15, Yu in view of Hou and Yu397 teaches the method of claim 11 further comprising forming solder bumps on the semiconductor die (Yu: I/O terminals 7000 are formed on 200, FIG. 17, [0047]).
Regarding claim 25, Yu in view of Hou and Yu397 teaches the method of claim 11, wherein after performing the first planarization process of the first through vias and the second side of the first semiconductor substrate are level (Yu: 5120 is coplanar with 5100SS, FIG. 14, [0025]).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable Yu (US 2020/0043896) in view of Hou (US 2022/0149002) and Yu397 (US 2020/0381397), and further in view of Huang et al. (US 2021/0134663; hereinafter ‘Huang’).
Regarding claim 12, Yu in view of Hou and Yu397 teaches the method of claim 11, but does not teach the method further comprising, before performing the first metal-to-metal bonding process, performing a first trimming process on sidewalls of the first semiconductor substrate.
Huang teaches a method [0011] further comprising, before performing the first metal-to-metal bonding process, performing a first trimming process on sidewalls of the first semiconductor substrate (‘before bonding, the outer edge of the wafers trimming is performed’, [0012]).
As taught by Huang, one of ordinary skill in the art would utilize and modify the above teaching into Yu in view of Hou and Yu397to obtain and achieve the method further comprising, before performing the first metal-to-metal bonding process, performing a first trimming process on sidewalls of the first semiconductor substrate as claimed, because edge trimming creates a planarized bonding surface, it prevents chipping or flaking that may occur during subsequent grinding or handling [0012].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Huang in combination with Yu in view of Hou and Yu397 due to the above reason.
Response to Arguments
Applicant's arguments with respect to claims have been considered but are moot in view of the new grounds of rejection. Response to arguments on newly added limitations are responded to in the above rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
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/JIYOUNG OH/Examiner, Art Unit 2818
/DUY T NGUYEN/Primary Examiner, Art Unit 2818 8/17/26
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