DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/08/2025 has been entered.
Status of the Application
Acknowledgement is made of the amendment received on 12/08/2025. Claims 1-12, 14-15, and 21-26 are pending in this application. Claims 1, 7, 11, 21, and 23-24 are amended. Claim 13 is canceled. Claims 25-26 are new.
Claims 1-12, 14-15, and 21-26 are presented in this Office Action.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 21-24 and 26 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 21 recites the limitation “wherein each first bonding pad directly contacts a through via of a respective first semiconductor device” in lines 10-12. However, it is unclear whether the recited “a through via” is the same respective through via previously formed in each first semiconductor device (as recited earlier in claim 21) or whether it encompasses any through via that may be present in the respective first semiconductor device. As a result, the identity of the “a through via” that is directly contacted by each first bonding pad, and thus the scope of the claim, is indefinite.
For best understand and examination purpose, the claim will be best considered based on drawings, disclosure, and/or any applicable prior arts; and the claim limitation “wherein each first bonding pad directly contacts a through via of a respective first semiconductor device” will be interpreted as “wherein each first bonding pad directly contacts the respective through via formed in the corresponding first semiconductor device” in the instant Office Action.
Claims 22-24 and 26 are rejected due to their dependency.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 7-8, 10, 21-23, and 26 are rejected under 35 U.S.C. 103 as being unpatentable Yu et al. (US 2020/0043896: hereinafter ‘Yu’) in view of Maling et al. (US 2015/0332966; hereinafter ‘Maling’).
Regarding claim 1, Yu teaches a method [0007] comprising:
directly bonding (shown in FIG. 14, [0043]) a first wafer (W1) to a second wafer (W2),
wherein the first wafer (W1) comprises a first interconnect structure (1200, 1300, and 1400, [0013]; hereinafter ‘IS1’) on a first substrate (1100),
wherein the second wafer (W2, FIG. 5) comprises a second interconnect structure (5200, 5210 conductively connected to 5400, 5300, and 5400, [0024, 0026]; hereinafter ‘IS2’) on a second substrate (5100),
wherein the bonding electrically connects the first interconnect structure of the first wafer (IS1) to the second interconnect structure of the second wafer (IS2),
wherein the second interconnect structure (IS2) comprises a plurality of dielectric layers (5220 and 5300 are dielectric layers; FIG. 5, [0024]);
forming (shown in FIG. 14, [0043]) a plurality of through substrate vias (a through-substrate via including 5120 and 5210 vertically aligned with and electrically connected to 5120, FIG. 5; hereinafter ‘TSV’) extending fully through the second substrate (5100) and fully through at least one dielectric layer of the plurality of dielectric layers (5200);
directly bonding (shown in FIG. 15, [0045]) a plurality of first semiconductor devices (200) to the second wafer (W2),
wherein the bonding electrically connects the plurality of first semiconductor devices (200) to the second interconnect structure (IS2) by the plurality of through substrate vias (5120);
encapsulating (shown in FIG. 16, [0046]) the plurality of first semiconductor devices (200) with a first encapsulant (3000); and
forming (shown in FIG. 17, [0047]) solder bumps (7000) over the plurality of first semiconductor devices (200).
Yu does not explicitly teach the method comprising: thinning the second substrate.
Yu, however, discloses that a substrate of a semiconductor wafer is thinned during processing to reduce the overall thickness of the stacked structure [0022].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Yu to obtain and achieve the method comprising: thinning the second substrate as claimed, because substrate thinning is a routine post-bond process option to control the overall thickness of wafer-level stacked structures, thereby obtaining a smaller-size 3D IC structure [0022, 0055].
Yu does not teach the method comprising: after thinning the second substrate, forming a through substrate via.
Maling teaches a method (FIG. 3a, [0020]) comprising: after thinning (thinned substrate by grinding) the second substrate (12), forming a through substrate vias (16 and 20).
As taught by Maling, one of ordinary skill in the art would utilize and modify the above teaching into Yu to obtain and achieve the method comprising: after thinning the second substrate, forming a through substrate via as claimed, because it provides exposure of frontside interconnects and thus extends a continuous and well-aligned conductive path from wafer to wafer [0012].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Maling in combination with Yu due to above reason.
Regarding claim 2, Yu in view of Maling teaches the method of claim 1, wherein directly bonding the first wafer to the second wafer comprises dielectric-to-dielectric bonding and metal-to-metal bonding (Yu: W1 and W2 are bonded with a dielectric-to-dielectric bond and a metal-to-metal bond, [0043]).
Regarding claim 3, Yu in view of Maling teaches the method of claim 1, wherein sidewalls of the second wafer are free of the first encapsulant (Yu: 3000 is formed over W2, FIG. 16, [0046]).
Regarding claim 4, Yu in view of Maling teaches the method of claim 1 further comprising performing a singulation process between two neighboring first semiconductor devices of the plurality of first semiconductor devices (Yu: singulation process is performed to cut 3000 between two neighboring 200, FIGS. 17 and 18, [0047]).
Regarding claim 5, Yu in view of Maling teaches the method of claim 1, wherein directly bonding the plurality of first semiconductor devices to the second wafer comprises forming (Yu: shown in FIG. 11, [0040]) a first bonding layer (4100) and first bonding pads (4200) on the second wafer and directly bonding the plurality of first semiconductor devices to the first bonding layer and the first bonding pads (shown in FIG. 11).
Regarding claim 7, Yu in view of Maling teaches the method of claim 1, wherein the through substrate vias extend from an outer surface of the second substrate to a conductive feature within the second interconnect structure of the second wafer (Yu: TSV extend from RS2 of 5100 to 5400 within IS2, FIGS. 5 and 14, [0025]).
Regarding claim 8, Yu in view of Maling teaches the method of claim 1,
after directly bonding the plurality of first semiconductor devices to the second wafer, forming (Yu: shown in FIG. 16) through vias (212, [0046]) in the first semiconductor devices of the plurality of first semiconductor devices; and
forming (shown in FIG. 17) a second bonding layer (6100”, [0047]) and second bonding pads (6200”) on the plurality of first semiconductor devices.
Regarding claim 10, Yu in view of Maling teaches the method of claim 8, but does not explicitly teach the method further comprising directly bonding a fourth wafer to the second bonding layer and the second bonding pads.
Yu, however, teaches the method further comprising directly bonding (shown in FIG. 11, [0040]) a fourth wafer (W2’) to the second bonding layer and the second bonding pads (4100 and 4200 of FIG. 11, which are functionally corresponding to 6100” and 6200” formed on 200 in FIG. 17).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to control and optimize the method of Yu by applying further comprising directly bonding a fourth wafer to the second bonding layer and the second bonding pads as claimed, because additionally stacking another wafer over a wafer-over-semiconductor device structure through hybrid bonding enables miniaturization, reduces overall weight, simplifies assembly processes, lower production costs, and enhances electrical performance [0055]. Further, it has been held that that rearranging part of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Regarding claim 21, Yu teaches a method [0004] comprising:
bonding (shown in FIG. 1) a plurality of first semiconductor devices (200, [0012]) to a first interconnect structure (1200, [0013]) using a first direct bonding process (a first bonding process between 200 and 1200, hereinafter ‘FB1’);
depositing (shown in FIG. 2) an encapsulant (3000’, [0020]) that surrounds each first semiconductor device of the plurality of first semiconductor devices (each of 200);
after depositing the encapsulant (3000’), forming (shown in FIG. 3) a respective through via (212, which are exposed at RS, thereby forming through vis, [0021]) in each first semiconductor device of the plurality of first semiconductor devices (each of 200);
forming (shown in FIG. 4) a first bonding layer (4000, [0023]) extending over the encapsulant (3000) and the plurality of first semiconductor devices (200);
forming (shown in FIG. 4) a plurality of first bonding pads (4200, [0023]) in the first bonding layer (4000), wherein each first bonding pad (4000) directly contacts a through via (212) of a respective first semiconductor device (200);
placing (shown in FIG. 5) a wafer (W2, [0024]) on the first bonding layer (4000), wherein the wafer (W2) comprises a second interconnect structure (5200, 5210 conductively connected to 5400, 5300, and 5400, [0024, 0026]; hereinafter ‘IS2R’) on a semiconductor substrate (5100, [0024]);
performing (shown in FIG. 5) a second direct bonding process (a second bonding process between 200 and W2, [0027]; hereinafter ‘FB2’) that directly bonds the second interconnect structure (IS2R) to the first bonding layer (4000) and to the plurality of first bonding pads (4200); and
forming (shown in FIG. 5) a plurality of through substrate vias (a through-substrate via including 5120 and 5210 vertically aligned with and electrically connected to 5120, FIG. 5; hereinafter ‘TSVR’) in the semiconductor substrate (5100), wherein the plurality of through substrate vias (TSVR) directly contact the second interconnect structure (IS2R), wherein at least one through substrate via of the plurality of through substrate vias (TSVR) extends a vertical distance that is greater than a thickness of the semiconductor substrate (TSVR extends completely through the substrate 5100 and further extends into interconnection layer 5200, therefore having a vertical extension greater than the thickness of 5100).
Yu does not teach the method comprising: after performing the second direct bonding process, forming a plurality of through substrate vias in the semiconductor substrate.
Maling teaches a method [0009] comprising: after performing the second direct bonding process (a bonding process between 10 and 14’, FIG. 2, [0014, 0019]), forming a plurality of through substrate vias (16 and 20, FIG. 3a, [0020]) in the semiconductor substrate (20b).
As taught by Maling, one of ordinary skill in the art would utilize and modify the above teaching into Yu to obtain and achieve the method comprising: after performing the second direct bonding process, forming a plurality of through substrate vias in the semiconductor substrate as claimed, because it provides exposure of frontside interconnects and thus extends a continuous and well-aligned conductive path [0012].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Maling in combination with Yu due to above reason.
Regarding claim 22, Yu in view of Maling teaches the method of claim 21, wherein sidewalls of the wafer are free of the encapsulant (Yu: sidewalls of W2 are free of 3000, which is formed for 3000’ in FIG. 2, FIG. 5, [0021]).
Regarding claim 23, Yu in view of Maling teaches the method of claim 21 further comprising:
forming (Yu: shown in FIG. 6) a second bonding layer (6000, [0028]), extending over the semiconductor substrate (5100); and
forming (shown in FIG. 6) a plurality of second bonding pads (6200, [0028]) in the second bonding layer (6000), wherein each second bonding pad (6200) directly contacts a respective through substrate via (TSVR).
Regarding claim 26, Yu in view of Maling teaches the method of claim 21, wherein surfaces of the plurality of through substrate vias and the semiconductor substrate are level (Yu: surfaces of TSVR and 5100 are level, FIG. 5).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable Yu (US 2020/0043896) in view of Maling (US 2015/0332966), and further in view of Su et al. (US 2017/0133351; hereinafter ‘Su’).
Regarding claim 6, Yu in view of Maling teaches the method of claim 1, but does not teach the method further comprising directly bonding a third wafer to the first wafer, wherein the bonding electrically connects a third interconnect structure of the first wafer to the first interconnect structure of the first wafer.
Su teaches a method [0038] further comprising directly bonding (FIG. 16, [0043]) a third wafer (lower layer of device die 534; hereinafter ‘L534’) to the first wafer (middle layer of 534; hereinafter ‘M534’), wherein the bonding electrically connects a third interconnect structure of the first wafer (solder regions 536 between L534 and) to the first interconnect structure of the first wafer (536 over M534).
As taught by Su, one of ordinary skill in the art would utilize and modify the above teaching into Yu in view of Maling to obtain and achieve the method further comprising directly bonding a third wafer to the first wafer, wherein the bonding electrically connects a third interconnect structure of the first wafer to the first interconnect structure of the first wafer as claimed, because the structure is vertically stacked, the package achieves higher integration without increasing the footprint [0044]. Further, it has been held that that rearranging part of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Su in combination with Yu in view of Maling due to above reason.
Claims 9 and 24 are rejected under 35 U.S.C. 103 as being unpatentable Yu (US 2020/0043896) in view of Maling (US 2015/0332966), and further in view of Kim et al. (US 2018/0006006; hereinafter ‘Kim’).
Regarding claim 9, Yu in view of Maling teaches the method of claim 8, but does not teach the method further comprising: directly bonding a plurality of second semiconductor devices to the second bonding layer and the second bonding pads; and encapsulating the plurality of second semiconductor devices with a second encapsulant.
Kim teaches a method [0010] further comprising:
directly bonding (shown in FIG. 7) a plurality of second semiconductor devices (C3, [0049]) to the second bonding layer (144, [0050]), and the second bonding pads (238, [0041]); and
encapsulating (shown in FIG. 8) the plurality of second semiconductor devices with a second encapsulant (160, [0051]).
As taught by Kim, one of ordinary skill in the art would utilize and modify the above teaching into Yu in view of Maling to obtain and achieve the method further comprising: directly bonding a plurality of second semiconductor devices to the second bonding layer and the second bonding pads; and encapsulating the plurality of second semiconductor devices with a second encapsulant as claimed, because the structure is vertically stacked, semiconductor packages achieve higher integration and miniaturization to meet the increasing demands for multifunctional electronic devices [0003]. Further, it has been held that that rearranging part of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Kim in combination with Yu in view of Maling due to above reason.
Regarding claim 24, Yu in view of Maling teaches the method of claim 23, but does not teach the method further comprising bonding a plurality of second semiconductor devices to the second bonding layer and to the plurality of second bonding pads using a third direct bonding process.
Kim teaches a method [0083] further comprising bonding (shown in FIG. 11) a plurality of second semiconductor devices (C2 of M2, [0084]) to the second bonding layer (142 of M2, [0043]) and to the plurality of second bonding pads (138, FIG. 4, [0041]) using a third direct bonding process (a bonding process between C1 and C2)
As taught by Kim, one of ordinary skill in the art would utilize and modify the above teaching into Yu in view of Maling to obtain and achieve the method further comprising bonding a plurality of second semiconductor devices to the second bonding layer and to the plurality of second bonding pads using a third direct bonding process as claimed, because the structure is vertically stacked, semiconductor packages achieve higher integration and miniaturization to meet the increasing demands for multifunctional electronic devices [0003]. Further, it has been held that that rearranging part of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Kim in combination with Yu in view of Maling due to above reason.
Claims 11, 14-15, and 25 are rejected under 35 U.S.C. 103 as being unpatentable Yu (US 2020/0043896) in view of Maling (US 2015/0332966), and further in view of Yu et al. (US 2020/0381397; hereinafter ‘Yu397’).
Regarding claim 11, Yu teaches a method [0007] comprising:
forming (shown in FIG. 14, [0043]) first bonding pads (5400) on a first side of a first semiconductor substrate (WS1);
forming (shown in FIG. 14) second bonding pads (1400) on a first side of a second semiconductor substrate (WS2);
bonding (shown in FIG. 14) the first bonding pads (5400) to the second bonding pads (1400) using a first metal-to-metal bonding process (a metal-to-metal bond, [0043]);
forming first openings (forming openings in a semiconductor substrate for through semiconductor vias, [0037]; hereinafter ‘FO’) in a second side of the first semiconductor substrate (the surface of the semiconductor substrate facing away from the bonding layer, corresponding to the outward-facing surface of substrate 5100 in FIG. 14, [0024]; hereinafter ‘5100SS’) that extend completely through the first semiconductor substrate (as evidenced by through semiconductor vias 5120 penetrating completely through substrate 5100 in FIG. 14, indicating that the opening depth is selectable to penetrate completely through the substrate);
depositing first conductive material (depositing conductive material in the openings, [0037]; hereinafter ‘FCM’) in the first openings (FO);
performing a first planarization process (performing a CMP planarization process, [0037]) on the first conductive material (FCM) to form first through vias (through semiconductor vias, 5120 in FIG 14) within the first semiconductor substrate (the semiconductor substrate, 5100 in FIG. 14), wherein after performing the first planarization process the second side of the first semiconductor substrate (5100SS) is free of the first conductive material (since the planarization process removes excess conductive material such that the conductive material remains only within the via openings and not on the surface of the semiconductor substrate, as evidenced by the exposed 5100SS prior to formation of bonding layer 4100, as illustrate in FIG. 14);
forming (shown in FIG. 14) third bonding pads (4200, [0044]) on the second side of the first semiconductor substrate (5100SS), wherein the third bonding pads (4200) are electrically connected to the first through vias (5120);
bonding (shown in FIG. 15, [0045]) a semiconductor die (200) to the third bonding pads (4200) using a second metal-to-metal bonding process (a metal-to-metal bond, [0045]);
after performing the second metal-to-metal bonding process, laterally surrounding (shown in FIG. 16, [0046]) the semiconductor die (200) with an encapsulant (3000); and
forming (shown in FIG. 16, [0046]) second through vias (212) in the semiconductor die (212 200).
Yu does not teach the method comprising: after performing the first metal-to-metal bonding process forming the first through vias.
Maling teaches a method [0009] comprising:
after performing the first metal-to-metal bonding process (performing 18 in 14’ to 16 in 14 bonding forming, FIG. 2, [0019]) forming a first through vias (20 is the through vias, shown in FIG. 3a).
Although Maling does not explicitly teach that the first opening comprises a plurality of openings.
Maling, however, provides a teaching of forming a conductive path through via-last backside processing [0020], and a person of ordinary skill in the art would have recognized that such via-last processing can be readily applied to a plurality of openings as a predictable variation to meet design needs.
As taught by Maling, one of ordinary skill in the art would utilize and modify the above teaching into Yu to obtain and achieve the method comprising: after performing the first metal-to-metal bonding process forming the first through vias as claimed, because it provides exposure of frontside interconnects and thus extends a continuous and well-aligned conductive path from wafer to wafer [0012]. Further, it has been held that that rearranging part of an invention involves only routine skill in the art. In re Japikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950) & it has been held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced, In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Maling in combination with Yu due to above reason.
Yu in view of Maling does not teach the method comprising: after performing the second metal-to-metal bonding process, laterally surrounding the semiconductor die and the first semiconductor substrate with an encapsulant; after laterally surrounding the semiconductor die and the first semiconductor substrate with an encapsulant, forming second openings in the semiconductor die; and depositing second conductive material in the second openings to form second through vias in the semiconductor die.
Yu397 teaches a method [0009] comprising: after performing the second metal-to-metal bonding process (after performing 160 of 110’ to 342 of 310 (310’ of FIG. 16) bonding process, FIG. 9, [0035-0036]), laterally surrounding the semiconductor die and the first semiconductor substrate with an encapsulant (laterally surrounding 310’ and 120 with 350, [0044]).
As taught by Yu397, one of ordinary skill in the art would utilize and modify the above teaching into Yu in view of Maling to obtain and achieve the method comprising: after performing the second metal-to-metal bonding process, laterally surrounding the semiconductor die and the first semiconductor substrate with an encapsulant as claimed, because the lateral encapsulant, being disposed flush with the periphery of the semiconductor die and the underlying substrate serves to protects the wafer and the bonded devices during subsequent wafer-level processes, thereby enhancing process robustness and improving overall manufacturing yield [0031].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Yu397 in combination with Yu in view of Maling due to above reason.
Although Yu in view of Maling and Yu397 does not explicitly teach the method comprising: after laterally surrounding the semiconductor die and the first semiconductor substrate with an encapsulant, forming second openings in the semiconductor die; and depositing second conductive material in the second openings to form second through vias in the semiconductor die.
Yu397, however, teaches that laterally encapsulating the semiconductor die and the semiconductor substrate with the encapsulant and subsequently forming through-vias (352, FIG. 16, [0044]) in the encapsulant.
Maling, moreover, teaches that after performing metal-to-metal bonding, through-vias is formed in the semiconductor die by creating openings and filling them with conductive material (FIG. 3a, [0019-0021]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to control and optimize the method of Yu397 and Maling by applying after laterally surrounding the semiconductor die and the first semiconductor substrate with an encapsulant, forming second openings in the semiconductor die; and depositing second conductive material in the second openings to form second through vias in the semiconductor die as claimed, because the lateral encapsulant protects the wafer and bonded devices during subsequent wafer-level processes, and the later through-via formation-performed at the final stage after bonding-achieves better alignment of the conductive path, thereby enhancing electrical interconnection while maintaining package integrity and yield.
Regarding claim 14, Yu in view of Maling and Yu397 teaches the method of claim 11 further comprising, after laterally surrounding the semiconductor die and the first semiconductor substrate with the encapsulant, performing a second trimming process to remove encapsulant from sidewalls of the first semiconductor substrate (Yu: after forming 3000, a planarization process is performed to remove excess encapsulant from the sidewall of 5100, [0021]).
Regarding claim 15, Yu in view of Maling and Yu397 teaches the method of claim 11 further comprising forming solder bumps on the semiconductor die (Yu: I/O terminals 7000 are formed on 200, FIG. 17, [0047]).
Regarding claim 25, Yu in view of Maling and Yu397 teaches the method of claim 11, wherein after performing the first planarization process of the first through vias and the second side of the first semiconductor substrate are level (Yu: 5120 is coplanar with 5100SS, FIG. 14, [0025]).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable Yu (US 2020/0043896) in view of Maling (US 2015/0332966) and Yu397 (US 2020/0381397), and further in view of Huang et al. (US 2021/0134663; hereinafter ‘Huang’).
Regarding claim 12, Yu in view of Maling and Yu397 teaches the method of claim 11, but does not teach the method further comprising, before performing the first metal-to-metal bonding process, performing a first trimming process on sidewalls of the first semiconductor substrate.
Huang teaches a method [0011] further comprising, before performing the first metal-to-metal bonding process, performing a first trimming process on sidewalls of the first semiconductor substrate (‘before bonding, the outer edge of the wafers trimming is performed’, [0012]).
As taught by Huang, one of ordinary skill in the art would utilize and modify the above teaching into Yu in view of Maling and Yu397 to obtain and achieve the method further comprising, before performing the first metal-to-metal bonding process, performing a first trimming process on sidewalls of the first semiconductor substrate as claimed, because edge trimming creates a planarized bonding surface, it prevents chipping or flaking that may occur during subsequent grinding or handling [0012].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Huang in combination with Yu in view of Maling and Yu397 due to above reason.
Response to Arguments
Applicant's arguments with respect to claims have been considered but are moot in view of the new ground(s) of rejection. Response to arguments on newly added limitations are responded to in the above rejection.
Claim 1
Applicant submits, in page 9 of Remark, that “Maling fails to disclose "after thinning the second substrate, forming a plurality of through substrate vias extending fully through the second substrate and fully through at least one dielectric layer of the plurality of dielectric layers" as recited in claim 1.”.
The examiner respectfully disagrees.
Under the broadest reasonable interpretation, the newly added limitation reciting “a plurality of through substrate vias” includes conductively connected portions extending through the substrate and into at least one dielectric layer. Accordingly, the newly added limitation is met by the combination of conductive features 5120 and 5210 of Yu, and similarly by the combination of conductive features 20 and 16 of Maling.
Claim 11
Applicant submits, in page 10 of Remark, that “However, as shown by Maling's Figure 3a, Maling's asserted first opening does not extend "completely through" Maling's asserted first semiconductor substrate (12) as recited in claim 11. Additionally, as shown by Maling's Figure 3a, the second side (e.g., Maling's "underside") of Maling's asserted first semiconductor substrate (12) is not free of Maling's asserted first conductive material (22).”.
The examiner respectfully disagrees.
Yu teaches forming openings in a semiconductor substrate to form through semiconductor vias. Yu further expressly discloses that the openings “may or may not penetrate through the substrate”, thereby indicating that the penetrating depth of the openings is selectable and encompassing embodiments in which the openings penetrate completely through the substrate, as required by the claim [0037].
Yu also teaches performing a planarization process to remove excess conductive material such that the top surface of the through semiconductor vias and the substrate are substantially coplanar, indicating that conductive material outside the openings is removed and remains only within the openings. Moreover, such planarization, including CMP, to remove excess conductive material is a well-known and routine step in through semiconductor via fabrication.
Claim 21
Applicant submits, in page 11 of Remark, that “Applicant respectfully submits that the cited references, either individually or in combination, fail to teach or suggest the features recited in claim 21.”.
The examiner respectfully disagrees.
The examiner notes that the newly added limitation reciting “at least one through substrate via of the plurality of through substrate vias extends a vertical distance that is greater than a thickness of the semiconductor substrate” is a different expression of the same structural requirement addressed in claim 1, namely, that the through substrate via extends beyond the substrate.
Under the broadest reasonable interpretation, this requirement is satisfied by conductively connected portions extending through the substrate and into an overlying dielectric layer, as disclosed by the combination of conductive features 5120 and 5210 of Yu, and similarly by the combination of conductive features 20 and 16 of Maling.
Conclusion
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/JIYOUNG OH/Examiner, Art Unit 2818
/DUY T NGUYEN/Primary Examiner, Art Unit 2818 2/19/26