DETAILED CORRESPONDENCE
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicants’ submission, filed on 12/29/2025, in response to claims 1-6, 8, 15-18, and 20-22 rejection from the non-final office action (09/25/2025), by amending claims 1, 9, 15, 20, and 22 is entered and will be addressed below.
Election/Restrictions
Claims 9-14 remain withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected Invention group II, there being no allowable generic or linking claim.
Claim Interpretations
The previously added limitation “a plasma sheath comprising an opening configured to enable plasma to reach a surface of the semiconductor device“ of claim 15, plasma sheath is created during plasma processing and is NOT part of the apparatus. Furthermore, to reach the wafer/semiconductor device, plasma has to be present at the wafer center without “opening”. But as this is not part of the apparatus structure, no 112(b) rejection is applied for the meaning of “opening”.
The “wherein a first distance that is between the top surface of the circular top portion and a bottom surface of the circular bottom portion is greater than a second distance that is between the top surface of the semiconductor device and a bottom surface of the electrostatic chuck” of claim 4 and similar claim 17 is ostensibly shown in Fig. 1D. However, Fig. 1D omitted a bottom portion of the electrostatic chuck 120 of Fig. 1A which shows the edge ring is on a peripheral step of the electrostatic chuck 120. Therefore, a bottom surface of the electrostatic chuck of Fig. 1D is really a bottom surface of the edge ring 125 and will be examined accordingly.
The “a circular bottom portion with an opening … a circular top portion … a circular chamfer portion” of claim 1 and as shown in Fig. 1B, the circular portion with an opening is actually an annular shape and will be examined accordingly.
The “an electrostatic chuck supporting a semiconductor device … wherein a distance between a top surface of the semiconductor device and a top surface of the circular top portion is in a range from zero millimeters to 3.75 millimeters … wherein the inner surface of the circular chamfer portion extends below the top surface of the semiconductor device to connect to the top surface of the circular bottom portion, a distance between an edge of the semiconductor device and the inner surface a distance is greater than zero millimeters and less than or equal to four millimeters” of claims 1 and 15 and “wherein the distance between the edge of the semiconductor device and the inner surface of the circular chamfer portion is less than or equal to two millimeters” of claims 2 and 18, the semiconductor device is a substrate process by the plasma etcher and not part of the apparatus. An apparatus that is capable of processing substrate/semiconductor device of various diameter and thickness is considered read into this portion of claims 1, 15, and 2, 18.
It has been held that claim language that simply specifies an intended use or field of use for the invention generally will not limit the scope of a claim (Walter, 618 F.2d at 769, 205 USPQ at 409; MPEP 2106). Additionally, in apparatus claims, intended use must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim (In re Casey, 152 USPQ 235 (CCPA 1967); In re Otto, 136 USPQ 458, 459 (CCPA 1963); MPEP2111.02). When the structure recited in the reference is substantially identical to that of the claims, claimed properties or functions are presumed to be inherent (In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977); MPEP 2112.01).
The “to connect” of claims 1 and 15 includes direct or indirect connection.
The “a distance between an edge of the semiconductor device and the inner surface of the circular chamfer portion is greater than zero millimeters and less than or equal to four millimeters” of claims 1 and 15, the distance is not limited to a horizontal distance.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-6, 8, 15-18, and 20-21 are rejected under 35 U.S.C. 103 as being unpatentable over Koshiishi (US 20070215279, hereafter ‘279), in view of Likhanskii et al. (US 20180082824, hereafter ‘824).
‘279 teaches some limitations of:
Claim 1: The present invention relates to a plasma processing apparatus and a plasma processing method for applying plasma processing such as etching to a substrate to be processed such as, for example a semiconductor wafer, and further relates to a focus ring and a focus ring component included in the plasma processing apparatus ([0003]), In the process chamber 10, the focus ring 25 is disposed around an upper surface of the mounting table 11 so as to surround a periphery of the semiconductor wafer W placed on the mounting table 11. The focus ring 25 includes a ring-shaped insulating member 26 placed directly on the mounting table 11 and a ring-shaped conductive member 27 disposed on top of the insulating member 26 (Figs. 1-2, [0045], the ring-shaped conductive member 27 reads into the claimed “An edge ring for a plasma etcher, the edge ring being a monolithic component and comprising”):
The mounting table 11 includes a not-shown electrostatic chuck for suction-holding the semiconductor wafer W placed on an upper surface thereof ([0043], includes the claimed “a circular bottom portion with an opening sized to receive an electrostatic chuck supporting a semiconductor device”),
during the plasma processing, if an inner edge of the inner ring portion 31 is too close to the mounting table 11, there is a possibility that abnormal discharge occurs between the mounting table 11 and the conductive member 27 due to the potential difference Ve therebetween. On the other hand, if the inner edge of the inner ring portion 31 is too apart from the mounting table 11, the inner ring portion 31 cannot sufficiently enter the area under the peripheral edge portion of the semiconductor wafer W and the above-described collision of the ions I in the plasma P with the lower surface of the peripheral edge portion of the semiconductor wafer W does not take place, so that the operation and effect of reducing the deposition cannot be obtained. Therefore, an interval L3 between the inner edge of the inner ring portion 31 and the mounting table 11 shown in FIG. 2 is preferably within a range from 0.5 mm to 1 mm ([0066], includes the claimed “wherein a distance between an inner surface of the circular bottom portion and an edge of the electrostatic chuck is greater than zero millimeters”);
As shown in FIG. 2, the conductive member 27 includes: an outer ring portion 30 disposed on an outer side of the periphery of the semiconductor wafer W placed on the mounting table 11 ([0046], includes the claimed “a circular top portion integrally connected to a first top part of the circular bottom portion”),
the interval L2 between the upper surface of the inner ring portion 31 and the lower surface of the peripheral edge portion of the semiconductor wafer W is 0.2 mm to 1 mm” ([0063], includes the claimed “wherein a distance between a top surface of the semiconductor device and a top surface of the circular top portion is in a range from zero millimeters to 3.75 millimeters”);
an inclined surface portion 30a disposed around the periphery of the semiconductor wafer W placed on the mounting table 11 and gradually becoming higher toward the outer side ([0048], includes the claimed “and a circular chamfer portion integrally connected to a second top part of the circular bottom portion and integrally connected to a side of the circular top portion” and “wherein an inner surface of the circular chamfer portion is angled radially outward from the opening at less than ninety degrees”, by processing a wafer of varying thickness, the apparatus is capable of “wherein the distance between the top surface of the semiconductor device and the top surface of the circular top portion is different from a thickness of the circular chamfer portion”),
By processing a thicker wafer than as shown in Fig. 2, it reads into the claimed “wherein the inner surface of the circular chamfer portion extends below the top surface of the semiconductor device to connect to the top surface of the circular bottom portion”),
the Preferable ranges of the interval L1 between the outer circumferential surface of the semiconductor wafer W and the inner circumferential surface 30c of the outer ring portion 30 and the interval L2 between the upper surface of the inner ring portion 31 and the lower surface of the peripheral edge portion of the semiconductor wafer W cannot be uniquely decided since they vary depending on the magnitude of the potential difference Ve generated between the semiconductor wafer W and the conductive member 27, the diameter and thickness of the semiconductor wafer W, the height of the inner circumferential surface 30c, and so on, but, for example, the interval L1 between the outer circumferential surface of the semiconductor wafer W and the inner circumferential surface 30c of the outer ring portion 30 is 1 mm to 5 1 is too small, abnormal discharge sometimes occurs between the outer circumferential surface of the semiconductor wafer W and the outer ring portion 30, and if, on the other hand, this interval L1 is too large, there is a possibility that later-described plasma sheath on the semiconductor wafer W and plasma sheath on the outer ring portion 30 become discontinuous ([0062], note L2 label is misplaced, should be between arrows right above label “27”, includes the claimed “wherein a distance between an edge of the semiconductor device and the inner surface of the circular chamfer portion is greater than zero millimeters and less than or equal to four millimeters”).
Claim 15: The present invention relates to a plasma processing apparatus and a plasma processing method for applying plasma processing such as etching to a substrate to be processed such as, for example a semiconductor wafer, and further relates to a focus ring and a focus ring component included in the plasma processing apparatus ([0003]), In the process chamber 10, the focus ring 25 is disposed around an upper surface of the mounting table 11 so as to surround a periphery of the semiconductor wafer W placed on the mounting table 11. The focus ring 25 includes a ring-shaped insulating member 26 placed directly on the mounting table 11 and a ring-shaped conductive member 27 disposed on top of the insulating member 26 (Figs. 1-2, [0045], includes the claimed “A plasma etcher, comprising: a chamber”);
a gas introduction portion 46 is provided ([0051], includes the claimed “a plasma gas inlet attached to the chamber and to receive a plasma gas”),
The mounting table 11 includes a not-shown electrostatic chuck for suction-holding the semiconductor wafer W placed on an upper surface thereof ([0043], includes the claimed “an electrostatic chuck provided in the chamber and to support a semiconductor device”),
an incident angle of the ions I on the peripheral edge portion of the semiconductor wafer W is influenced by the difference in thickness between the plasma sheaths formed on the semiconductor wafer W and on the outer ring portion 30 of the conductive member 27 during the plasma processing ([0068], includes the claimed “a plasma sheath comprising an opening configured to enable plasma to reach a surface of the semiconductor device”; the conductive member 27 reads into the claimed “a monolithic edge ring provided in the chamber and to surround the electrostatic chuck and the semiconductor device” and “wherein the monolithic edge ring includes: a circular bottom portion with an opening sized to receive the electrostatic chuck”);
during the plasma processing, if an inner edge of the inner ring portion 31 is too close to the mounting table 11, there is a possibility that abnormal discharge occurs between the mounting table 11 and the conductive member 27 due to the potential difference Ve therebetween. On the other hand, if the inner edge of the inner ring portion 31 is too apart from the mounting table 11, the inner ring portion 31 cannot sufficiently enter the area under the peripheral edge portion of the semiconductor wafer W and the above-described collision of the ions I in the plasma P with the lower surface of the peripheral edge portion of the semiconductor wafer W does not take place, so that the operation and effect of reducing the deposition cannot be obtained. Therefore, an interval L3 between the inner edge of the inner ring portion 31 and the mounting table 11 shown in FIG. 2 is preferably within a range from 0.5 mm to 1 mm ([0066], includes the claimed “wherein a distance between an inner surface of the circular bottom portion and an edge of the electrostatic chuck is greater than zero millimeters”);
As shown in FIG. 2, the conductive member 27 includes: an outer ring portion 30 disposed on an outer side of the periphery of the semiconductor wafer W placed on the mounting table 11 ([0046], includes the claimed “a circular top portion integrally connected to a first top part of the circular bottom portion”),
an inclined surface portion 30a disposed around the periphery of the semiconductor wafer W placed on the mounting table 11 and gradually becoming higher toward the outer side ([0048], includes the claimed “and a chamfer portion integrally connected to a second top part of the circular bottom portion and integrally connected to a side of the circular top portion, wherein an inner surface of the chamfer portion is angled radially outward from an edge of the semiconductor device”),
by processing a wafer of varying thickness, the apparatus is capable of “wherein the distance between the top surface of the semiconductor device and the top surface of the circular top portion is different from a thickness of the circular chamfer portion”),
the interval L2 between the upper surface of the inner ring portion 31 and the lower surface of the peripheral edge portion of the semiconductor wafer W is 0.2 mm to 1 mm” ([0063], includes the claimed “wherein a distance between a top surface of the semiconductor device and a top surface of the circular top portion is in a range from zero millimeters to 3.75 millimeters”);
By processing a thicker wafer than as shown in Fig. 2, it reads into the claimed “wherein the inner surface of the chamfer portion extends below a top surface of the semiconductor device to connect to a top surface of the circular bottom portion”),
the Preferable ranges of the interval L1 between the outer circumferential surface of the semiconductor wafer W and the inner circumferential surface 30c of the outer ring portion 30 and the interval L2 between the upper surface of the inner ring portion 31 and the lower surface of the peripheral edge portion of the semiconductor wafer W cannot be uniquely decided since they vary depending on the magnitude of the potential difference Ve generated between the semiconductor wafer W and the conductive member 27, the diameter and thickness of the semiconductor wafer W, the height of the inner circumferential surface 30c, and so on, but, for example, the interval L1 between the outer circumferential surface of the semiconductor wafer W and the inner circumferential surface 30c of the outer ring portion 30 is 1 mm to 5 1 is too small, abnormal discharge sometimes occurs between the outer circumferential surface of the semiconductor wafer W and the outer ring portion 30, and if, on the other hand, this interval L1 is too large, there is a possibility that later-described plasma sheath on the semiconductor wafer W and plasma sheath on the outer ring portion 30 become discontinuous ([0062], note L2 label is misplaced, should be between arrows right above label “27”, includes the claimed “wherein a distance between the edge of the semiconductor device and the inner surface of the chamfer portion is greater than zero millimeters and less than or equal to four millimeters”).
‘279 teaches that the inner ring portion may be, for example, one of silicon (Si), carbon (C), and silicon carbide (SiC) ([0016]). ‘279 does not teach the other limitations of:
Claim 1: and wherein the edge ring is constructed of a metal.
Claim 15: wherein the monolithic edge ring is constructed of a metal, and
‘824 is analogous art in the field of Extreme Edge Uniformity Control (title). ’824 teaches that FIG. 7 shows an embodiment in which the shield ring 350 is conductive. In this embodiment, a separate ring electrode is not needed ... Like the previous embodiments, a voltage may be applied to the shield ring 350 by the ring bias power supply 55 ([0052]), wherein the shield ring is constructed of metal and the ring bias power supply is in electrical communication with the shield ring Claim 4 of ‘824), for the purpose of adjustable control of the plasma sheath shape so as to adjust ion angles ([0006], last sentence).
Before the effective filling date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have adopted metal, as taught by ‘824, as the material of the conductive member 27 of ‘279, for the purpose of adjustable control of the plasma sheath shape so as to adjust ion angles, as taught by ‘824 ([0006], last sentence).
‘279 further teaches the limitations of:
Claims 2 and 18: Preferable ranges of the interval L1 between the outer circumferential surface of the semiconductor wafer W and the inner circumferential surface 30c of the outer ring portion 30 and the interval L2 between the upper surface of the inner ring portion 31 and the lower surface of the peripheral edge portion of the semiconductor wafer W cannot be uniquely decided since they vary depending on the magnitude of the potential difference Ve generated between the semiconductor wafer W and the conductive member 27, the diameter and thickness of the semiconductor wafer W, the height of the inner circumferential surface 30c, and so on, but, for example, the interval L1 between the outer circumferential surface of the semiconductor wafer W and the inner circumferential surface 30c of the outer ring portion 30 is 1 mm to 5
Claims 3, 16 and 21: A height h of the inclined surface portion 30a formed in the upper surface of the outer ring portion 30 is preferably within a range from 0 mm to 6 mm, more preferably, from 2 mm to 4 m, from the upper surface of the semiconductor wafer W. Further, a horizontal length h' of the inclined surface portion 30a (length in the diameter direction of the semiconductor wafer W) is preferably within a range from 0.5 mm to 9 mm ([0065], includes the claimed “wherein the inner surface of the circular chamfer portion is angled in a range from ten degrees to seventy degrees” of claim 3 and “wherein the inner surface of the chamfer portion is angled in a range from ten degrees to seventy degrees” of claim 16, and “wherein the inner surface of the chamfer portion is angled in a range from thirty degrees to fifty degrees” of claim 21).
Claims 4-6 and 17: A height h of the inclined surface portion 30a formed in the upper surface of the outer ring portion 30 is preferably within a range from 0 mm to 6 mm, more preferably, from 2 mm to 4 m ([0065], includes the claimed “wherein a first distance that is between the top surface of the circular top portion and a bottom surface of the circular bottom portion is greater than a second distance that is between the top surface of the semiconductor device and a bottom surface of the electrostatic chuck” of claim 4, “wherein a first distance between the top surface of the circular top portion and a bottom surface of the circular bottom portion is greater than a second distance between the top surface of the semiconductor device and a bottom surface of the electrostatic chuck” of claim 17, “wherein the first distance is greater than the second distance by a range from zero millimeters to 3.75 millimeters” of claim 5 and “wherein the first distance is greater than the second distance by a range from zero millimeters to 1.5 millimeters” of claim 6).
Claims 8 and 22: Fig. 2 shows the claimed “wherein, in a cross-sectional view of the edge ring, the top surface of the circular bottom portion extends partially underneath the semiconductor device” of claim 8 and “wherein, in a cross-sectional view of the monolithic edge ring, the top surface of the circular bottom portion extends partially underneath the semiconductor device” of claim 22.
The combination of ‘279 and ‘824 further teach the limitations of:
Claim 20: a voltage may be applied to the shield ring 350 by the ring bias power supply 55 (‘824, [0052], 2nd last sentence, includes the claimed “further comprising: a power supply to provide a bias voltage to the monolithic edge ring”, for the purpose of adjustable control of the plasma sheath shape so as to adjust ion angles, [0006]).
Alternatively, claims 1-6, 8, 15-18, and 20-21 are rejected under 35 U.S.C. 103 as being unpatentable over ‘279, in view of ‘824 and Dhindsa et al. (US 20080241420, hereafter ‘420).
In case Applicants argue that the size of wafer is not an intended use of the apparatus, and “to connect” has to be in direct connection.
‘420 is analogous art in the field of APPARATUS FOR DC VOLTAGE CONTROL ON RF-POWERED ELECTRODE (title), The method includes supporting the substrate in the plasma processing chamber configured with an upper electrode (UE) and a lower electrode (LE), configuring at least one radio frequency power source to ignite plasma between the UE and the LE, and providing a conductive coupling ring, the conductive coupling ring is coupled to the LE to provide a conductive path (abstract). ’420 teaches that Plasma processing system 100 may also include a coupling ring 114. In an embodiment, arranged above coupling ring 114 is a plasma-facing-substrate-periphery (PFSP) ring 116, which may be disposed on the periphery of the substrate facing plasma 102. PFSP ring 116 may include, but are not limited to, a hot edge ring (Fig. 1, [0027]), DC bias on PFSP ring 116 ([0051]), for the purpose of sophisticated process control ([0002]). Fig. 1 of ‘420 shows “wherein the inner surface of the circular chamfer portion extends below the top surface of the semiconductor device to connect to the top surface of the circular bottom portion” (a direct connection) and “wherein the inner surface of the circular chamfer portion extends below the top surface of the semiconductor device to connect to the top surface of the circular bottom portion”.
Before the effective filling date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have changed the shape of the focus ring 25 of ‘279 to the shape of hot edge ring 116 of ‘420, for the purpose of sophisticated process control, as taught by ‘420 ([0002]).
Response to Arguments
Applicant's arguments filed 12/29/2025 have been fully considered but they are not convincing in light of the new grounds of rejection above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 20100078899 was previously cited for edge ring 117 the same shape as instant Application (Fig. 1A). Additionally, US 20210296098 (Fig. 2) and US 20210043431 (Fig. 2A) also has the same shape as instant Application (Fig. 1A).
US 8426317 is cited for varied sheath shape according to operation conditions (Figs. 4-5).
US 20040072426 is cited for focus ring 163 formed of aluminum (Fig. 1, [0021]).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KEATH T CHEN whose telephone number is (571)270-1870. The examiner can normally be reached 8:30am-5:00 pm.
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/KEATH T CHEN/Primary Examiner, Art Unit 1716
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