DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot on grounds of new rejection.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over ZHAO et al. (ZHAO) (US 2024/0023347 A1) as evidenced by or in view of Park et al. (Park) (US 2020/0203328 A1) as evidenced by or in view of MAKALA et al. (MAKALA) (US 2021/0408019 A1) or Kim et al. (Kim) (US 2019/0206933 A1).
In regards to claim 1, ZHAO (Figs. 1-8 and associated text) discloses a method, comprising: forming a plurality of transistors (write transistors) in a first wafer (First Wafer), wherein a first surface (top surface) of the first wafer (First Wafer) includes a first plurality of bonding pads (shown but not labeled) electrically coupled to the transistors (write transistors); forming a memory array (memory array including MTJ stacks) in a second wafer (Second Wafer), wherein the memory array (memory array including MTJ stacks) includes a plurality of tunnel junction stacks (MTJ stacks), and wherein a second surface (bottom surface) of the second wafer (Second Wafer) includes a second plurality of bonding pads (shown but not labeled) electrically coupled to the tunnel junction stacks (MTJ stacks); bonding the first surface (top surface) of the first wafer (First Wafer) with the second surface (bottom surface) of the second wafer (Second Wafer), such that the transistors (write transistors) are coupled to the memory array (memory array including MTJ stacks) through the first plurality of bonding pads (shown but not labeled) and the second plurality of bonding pads (shown but not labeled).
Zhao does not specifically disclose that forming only a memory array is in the second wafer.
Park (Figs. 1-8 and associated text and items) discloses forming only memory array (items 110, 130) in/on/within a device/wafer/substrate (items 111, D1, D3) and wherein the memory array includes a plurality of magnetic tunnel junctions (item 133). Park (paragraph 55) also discloses that in some embodiments that D3 may be formed on the second semiconductor device D2 even though this embodiment is not shown.
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Park for the purpose of an MRAM or RRAM fusion memory device
ZHAO as evidenced/modified by Park does not specifically disclose ferroelectric tunnel junction stacks.
As evidence by MAKALA (paragraphs 108, 109, 122, 149, 151, Figs. 1-44 and associated text), the memory array can include MTJ stacks (item 150, Fig. 30) or FTJ stacks (Fig. 1D, paragraph 55) and performing thermal anneal to improve the crystallinity of the FTJ stacks (paragraphs 58, 87) and after the performing of the thermal treatment (paragraph 58), bonding the first surface of the first wafer with the second surface of the second wafer (paragraphs, 6, 45).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of MAKALA for the purpose improving the crystallinity of the ferroelectric material (paragraphs 58, 87) and having a FTJ, MRAM, PCRAM or PRAM memory devices (paragraphs 109, 122, 149, 151).
As further evidenced by Kim (paragraph 86, Figs. 5E, 7 and associated text), a thermal treatment (item 704) can be performed to a MTJ stack before bonding (Figs. 5E and 7).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Kim as well for the purpose improving the crystallinity of the FTJ stack of ZHAO as modified by MAKALA.
Therefore ZHAO as evidenced/modified by Park and as evidenced/modified by MAKALA or Kim discloses performing a thermal anneal treatment to the FTJ stacks in the second wafer without subjecting any transistor to the thermal treatment.
In regards to claim 2, ZHAO (Figs. 1-8 and associated text) as evidenced/modified by Park (paragraph 55, Figs. 1-8 and associated text and items) as evidenced and/or modified by MAKALA (paragraphs 108, 109, 122, 149, 151, Figs. 1-44 and associated text) and/or Kim (paragraph 86, Figs. 5E, 7 and associated text) discloses wherein the forming of the memory array includes forming signal lines (WL1-WL 8 or BL1, BL2) coupled to the FTJ stacks (ZHAO stacks as modified by MAKALA), wherein at least some of the second plurality of bonding pads (shown but not labeled in ZHAO) are coupled to the signal lines of the memory array (WL1-WL 8 or BL1, BL2).
In regards to claim 3, ZHAO (Figs. 1-8 and associated text) as evidenced/modified by Park (paragraph 55, Figs. 1-8 and associated text and items) as evidenced and/or modified by MAKALA (paragraphs 108, 109, 122, 149, 151, Figs. 1-44 and associated text) and/or Kim (paragraph 86, Figs. 5E, 7 and associated text) discloses wherein the forming of the signal lines (WL1-WL 8 or BL1, BL2) includes forming word lines and bit lines (WL1-WL 8 and BL1, BL2) of the memory array.
In regards to claim 4, ZHAO (Figs. 1-8 and associated text) as evidenced/modified by Park (paragraph 55, Figs. 1-8 and associated text and items) as evidenced and/or modified by MAKALA (paragraphs 108, 109, 122, 149, 151, Figs. 1-44 and associated text) and/or Kim (paragraph 86, Figs. 5E, 7 and associated text) discloses wherein each of the signal lines (WL1-WL 8 and/or BL1, BL2) of the memory array is coupled to at least one of the second plurality of bonding pads (shown but not labeled).
In regards to claim 5, ZHAO (Figs. 1-8 and associated text) as evidenced/modified by Park (paragraph 55, Figs. 1-8 and associated text and items) as evidenced and/or modified by MAKALA (paragraphs 108, 109, 122, 149, 151, Figs. 1-44 and associated text) and/or Kim (paragraph 86, Figs. 5E, 7 and associated text) discloses wherein after the bonding the second wafer is free of transistors.
In regards to claim 6, ZHAO (Figs. 1-8 and associated text) as evidenced/modified by Park (paragraph 55, Figs. 1-8 and associated text and items) as evidenced and/or modified by MAKALA (paragraphs 108, 109, 122, 149, 151, Figs. 1-44 and associated text) and/or Kim (paragraph 86, Figs. 5E, 7 and associated text) discloses wherein after the bonding among the transistors (write transistors, ZHAO) coupled to the memory cells, each of the transistors (write transistors, ZHAO) is associated with multiple FTJ stacks (ZHAO stacks as modified by MAKALA) in the memory array.
In regards to claim 7, ZHAO (Figs. 1-8 and associated text) as evidenced/modified by Park (paragraph 55, Figs. 1-8 and associated text and items) as evidenced and/or modified by MAKALA (paragraphs 108, 109, 122, 149, 151, Figs. 1-44 and associated text) and/or Kim (paragraph 86, Figs. 5E, 7 and associated text) discloses forming a plurality of selectors (Selector transistors), wherein after the bonding each of the FTJ stacks (ZHAO stacks as modified by MAKALA) is coupled to one of the selectors (Selector transistors).
In regards to claim 8, ZHAO (Figs. 1-8 and associated text) as evidenced/modified by Park (paragraph 55, Figs. 1-8 and associated text and items) as evidenced and/or modified by MAKALA (paragraphs 108, 109, 122, 149, 151, Figs. 1-44 and associated text) and/or Kim (paragraph 86, Figs. 5E, 7 and associated text) discloses wherein the selectors (Selector transistors) are formed in the second wafer (Second Wafer).
In regards to claim 9, ZHAO (Figs. 1-8 and associated text as evidenced/modified by Park (paragraph 55, Figs. 1-8 and associated text and items) as evidenced and/or modified by MAKALA (paragraphs 108, 109, 122, 149, 151, Figs. 1-44 and associated text) and/or Kim (paragraph 86, Figs. 5E, 7 and associated text) discloses wherein the forming of the selectors (item 134) includes forming a plurality of metal-insulator-metal structures (paragraph 67).
In regards to claim 10, ZHAO (Figs. 1-8 and associated text) as evidenced/modified by Park (paragraph 55, Figs. 1-8 and associated text and items) as evidenced and/or modified by MAKALA (paragraphs 108, 109, 122, 149, 151, Figs. 1-44 and associated text) and/or Kim (paragraph 86, Figs. 5E, 7 and associated text) discloses wherein the thermal treatment comprises a temperature between about 400°C and about 1000°C (paragraphs 72, 87 MAKALA, paragraph 96, Fig.7, item 704, Kim).
In regards to claim 11, ZHAO (Figs. 1-8 and associated text) discloses a method, comprising: forming a plurality of transistors (write transistor) in a first wafer (Frist wafer); forming a first redistribution layer (layer shown above write transistor, shown but not labeled, Figs. 2, 4, 6) on the first wafer (Frist wafer), wherein the first redistribution layer (layer shown above write transistor, shown but not labeled, Figs. 2, 4, 6) includes a first plurality of bonding pads (pads and/or vias shown above write transistor, shown but not labeled, Figs. 2, 4, 6) that are associated with the plurality of transistors (write transistor); forming a plurality of memory cells (plurality of MTJ stacks) in a second wafer (Second Wafer); forming a second redistribution layer (layer shown below MTJ stacks shown but not labeled, Figs. 2, 4, 6) on the second wafer (Second Wafer), wherein the second redistribution layer (layer shown below MTJ stacks shown but not labeled, Figs. 2, 4, 6) includes a second plurality of bonding pads (pads and/or vias shown below MTJ stacks shown but not labeled, Figs. 2, 4, 6) that are associated with the plurality of memory cells (MTJ stacks); bonding the second wafer (Second Wafer) to the first wafer (First Wafer), wherein each of the first plurality of bonding pads (pads and/or vias shown above write transistor, shown but not labeled, Figs. 2, 4, 6) is bonded to a corresponding one in the second plurality of bonding pads (pads and/or vias shown below MTJ stacks shown but not labeled, Figs. 2, 4, 6)
Zhao does not specifically disclose that forming only a memory array is in the second wafer.
Park (Figs. 1-8 and associated text and items) discloses forming only memory array (items 110, 130) in/on/within a device/wafer/substrate (items 111, D1, D3) and wherein the memory array includes a plurality of magnetic tunnel junctions (item 133). Park (paragraph 55) also discloses that in some embodiments that D3 may be formed on the second semiconductor device D2 even though this embodiment is not shown.
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Park for the purpose of an MRAM or RRAM fusion memory device
ZHAO as evidenced/modified by Park does not specifically disclose but does not specifically disclose performing a thermal treatment to the plurality of memory cells in the second wafer to increase a crystallization quality of the memory cells; and after the performing of the thermal treatment, bonding the second wafer to the first wafer.
As evidence by MAKALA (paragraphs 108, 109, 122, 149, 151, Figs. 1-44 and associated text), the memory array can include MTJ stacks (item 150, Fig. 30) or FTJ stacks (Fig. 1D, paragraph 55) and performing thermal anneal to improve the crystallinity of the FTJ stacks (paragraphs 58, 87) and after the performing of the thermal treatment (paragraph 58), bonding the first surface of the first wafer with the second surface of the second wafer (paragraphs, 6, 45).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of MAKALA for the purpose of improving the crystallinity of the ferroelectric material (paragraphs 58, 87) and having a FTJ, MRAM, PCRAM or PRAM memory devices (paragraphs 109, 122, 149, 151).
As further evidenced by Kim (paragraph 86, Figs. 5E, 7 and associated text), a thermal treatment (item 704) can be performed to a MTJ stack before bonding (Figs. 5E and 7).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Kim as well for the purpose improving the crystallinity of the FTJ stack of ZHAO as modified by MAKALA.
Therefore ZHAO as evidenced/modified by Park and as evidenced/modified by MAKALA or Kim discloses performing a thermal anneal treatment to the plurality of memory cells in the second wafer to improve the crystallinity of the memory cells without subjecting any transistor to the thermal treatment.
In regards to claim 12, ZHAO (Figs. 1-8 and associated text) as evidenced/modified by Park (paragraph 55, Figs. 1-8 and associated text and items) as evidenced and/or modified by MAKALA (paragraphs 108, 109, 122, 149, 151, Figs. 1-44 and associated text) and/or Kim (paragraph 86, Figs. 5E, 7 and associated text) discloses forming top signal lines (WL1-WL-8 or BL1, BL2) and bottom signal lines (WL1-WL-8 or BL1, BL2) sandwiching the memory cells (MTJ stacks), wherein each of the top and bottom signal lines (WL1-WL-8 and BL1, BL2) is associated with one of the second plurality of bonding pads (pads and/or vias shown below MTJ stacks shown but not labeled, Figs. 2, 4, 6).
In regards to claim 13, ZHAO (Figs. 1-8 and associated text) as evidenced/modified by Park (paragraph 55, Figs. 1-8 and associated text and items) as evidenced and/or modified by MAKALA (paragraphs 108, 109, 122, 149, 151, Figs. 1-44 and associated text) and/or Kim (paragraph 86, Figs. 5E, 7 and associated text) discloses wherein the forming of the memory cells (MTJ stacks, ZHAO as modified by MAKALA) includes forming a selector (Selector Transistor) electrically coupled to a ferroelectric film (item 30L, MAKALA).
In regards to claim 14, ZHAO (Figs. 1-8 and associated text) as evidenced/modified by Park (paragraph 55, Figs. 1-8 and associated text and items) as evidenced and/or modified by MAKALA (paragraphs 108, 109, 122, 149, 151, Figs. 1-44 and associated text) and/or Kim (paragraph 86, Figs. 5E, 7 and associated text) discloses wherein the ferroelectric film (item 30L, MAKALA) has a thickness less than about 5 nm (paragraph 58, MAKALA, 2nm to 30 nm).
It would have been obvious to one having ordinary skill in the art at the time of the invention to modify the invention to include a ferroelectric film having a thickness less than about 5 nm, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art (In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980)). However, the Applicant has not given any criticality as to where this thickness yields an unexpected result or advantage.
In regards to claim 15, ZHAO (Figs. 1-8 and associated text) as evidenced/modified by Park (paragraph 55, Figs. 1-8 and associated text and items) as evidenced and/or modified by MAKALA (paragraphs 108, 109, 122, 149, 151, Figs. 1-44 and associated text) and/or Kim (paragraph 86, Figs. 5E, 7 and associated text) does not specifically disclose wherein a number of the plurality of transistors (Write transistor) is less than a number of the first plurality of bonding pads (pads and/or vias shown above write transistors shown but not labeled, Figs. 2, 4, 6).
It would have been obvious to one having ordinary skill in the art at the time of the invention to modify the invention to include a number transistors being less than the number of bonding pads for the purpose of design choice, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art (In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980)).
In regards to claim 16, ZHAO (Figs. 1-8 and associated text) as evidenced and/or modified by as evidenced/modified by Park (paragraph 55, Figs. 1-8 and associated text and items) as evidenced and/or modified by MAKALA (paragraphs 108, 109, 122, 149, 151, Figs. 1-44 and associated text) and/or Kim (paragraph 86, Figs. 5E, 7 and associated text) does not specifically disclose wherein a number of the second plurality of bonding pads (pads and/or vias shown below MTJ stacks shown but not labeled, Figs. 2, 4, 6) is less than a number of the memory cells ( MTJ stacks).
It would have been obvious to one having ordinary skill in the art at the time of the invention to modify the invention to include a number of second bonding pads less than the number of memory cells for the purpose of design choice, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art (In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980)).
In regards to claim 17, ZHAO (Figs. 1-8 and associated text) discloses a method, comprising: forming a plurality of transistors (write transistor) in a first wafer (First Wafer); forming a first interconnect structure (layer shown but not labeled on top of write transistors, Figs. 2, 4, 6) coupled to the transistors (write transistor); forming a first redistribution layer (pads shown but not labeled on top of the layer, shown but not label above the write transistors, Figs. 2, 4, 6) coupled to the first interconnect structure (layer shown but not labeled on top of write transistors, Figs. 2, 4, 6); forming a memory array (MTJ stacks) in a second wafer (Second Wafer), wherein the memory array includes a plurality of ferroelectric tunnel junction (FTJ) stacks (MTJ stacks); forming a second interconnect structure (layer shown but not labeled on below the MTJ stacks, Figs. 2, 4, 6) coupled to the memory array; forming a second redistribution layer (pads shown but not labeled below the layer, shown but not labeled, below the MTJ stacks, Figs. 2, 4, 6) coupled to the second interconnect structure (layer shown but not labeled on below the MTJ stacks, Figs. 2, 4, 6); bonding the second wafer (Second Wafer) to the first wafer (First Wafer), such that the transistors (write transistors) are coupled to the memory array (MTJ stacks) through the first interconnect structure (layer shown but not labeled on top of write transistors, Figs. 2, 4, 6), the first redistribution layer (pads shown but not labeled on top of the layer, shown but not label above the write transistors, Figs. 2, 4, 6), the second redistribution layer (pads shown but not labeled below the layer, shown but not labeled, below the MTJ stacks, Figs. 2, 4, 6), and the second interconnect structure (layer shown but not labeled on below the MTJ stacks, Figs. 2, 4, 6).
Zhao does not specifically disclose that forming only a memory array is in the second wafer.
Park (Figs. 1-8 and associated text and items) discloses forming only memory array (items 110, 130) in/on/within a device/wafer/substrate (items 111, D1, D3) and wherein the memory array includes a plurality of magnetic tunnel junctions (item 133). Park (paragraph 55) also discloses that in some embodiments that D3 may be formed on the second semiconductor device D2 even though this embodiment is not shown.
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Park for the purpose of an MRAM or RRAM fusion memory device
ZHAO as evidenced/modified by Park does not specifically disclose but does not specifically disclose performing a thermal treatment to the plurality of memory cells in the second wafer to increase a crystallization quality of the memory cells; and after the performing of the thermal treatment, bonding the second wafer to the first wafer.
As evidence by MAKALA (paragraphs 108, 109, 122, 149, 151, Figs. 1-44 and associated text), the memory array can include MTJ stacks (item 150, Fig. 30) or FTJ stacks (Fig. 1D, paragraph 55) and performing thermal anneal to improve the crystallinity of the FTJ stacks (paragraphs 58, 87) and after the performing of the thermal treatment (paragraph 58), bonding the first surface of the first wafer with the second surface of the second wafer (paragraphs, 6, 45).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of MAKALA for the purpose improving the crystallinity of the ferroelectric material (paragraphs 58, 87) and having a FTJ, MRAM, PCRAM or PRAM memory devices (paragraphs 109, 122, 149, 151).
As further evidenced by Kim (paragraph 86, Figs. 5E, 7 and associated text), a thermal treatment (item 704) can be performed to a MTJ stack before bonding (Figs. 5E and 7).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Kim as well for the purpose improving the crystallinity of the FTJ stack of ZHAO as modified by MAKALA.
Therefore ZHAO as evidenced/modified by Park and as evidenced/modified by MAKALA or Kim discloses performing a thermal anneal treatment to the second wafer to improve the crystallinity of the ferroelectric films in the FTJ stacks without subjecting any transistor to the thermal treatment.
In regards to claim 18, ZHAO (Figs. 1-8 and associated text) as evidenced/modified by Park (paragraph 55, Figs. 1-8 and associated text and items) as evidenced and/or modified by MAKALA (paragraphs 108, 109, 122, 149, 151, Figs. 1-44 and associated text) and/or Kim (paragraph 86, Figs. 5E, 7 and associated text) discloses wherein the forming of the memory array includes forming a plurality of selectors (selector transistors, ZHAO) coupled to the FTJ stacks (MTJ stacks, ZHAO as evidenced/modified by MAKALA).
In regards to claim 19, ZHAO (Figs. 1-8 and associated text) as evidenced/modified by Park (paragraph 55, Figs. 1-8 and associated text and items) as evidenced and/or modified by MAKALA (paragraphs 108, 109, 122, 149, 151, Figs. 1-44 and associated text) and/or Kim (paragraph 86, Figs. 5E, 7 and associated text) discloses wherein a number of the selectors (select transistors) equals a number of the FTJ stacks (MTJ stacks, ZHAO as evidenced/modified by MAKALA).
It would have been obvious to one having ordinary skill in the art at the time of the invention to modify the invention to include an equal number of selectors and FTJ stacks for the purpose design choice and one on one relationship, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art (In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980)).
In regards to claim 20, ZHAO (Figs. 1-8 and associated text) as evidenced/modified by Park (paragraph 55, Figs. 1-8 and associated text and items) as evidenced and/or modified by MAKALA (paragraphs 108, 109, 122, 149, 151, Figs. 1-44 and associated text) and/or Kim (paragraph 86, Figs. 5E, 7 and associated text) discloses wherein the bonding couples at least one of the transistors (write transistors) to more than one of the FTJ stacks (MTJ stacks, ZHAO as evidenced/modified by MAKALA).
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over ) Park et al. (Park) (US 2020/0203328 A1) as evidenced by or in view of ZHAO et al. (ZHAO) (US 2024/0023347 A1as evidenced by or in view of MAKALA et al. (MAKALA) (US 2021/0408019 A1) or Kim et al. (Kim) (US 2019/0206933 A1).
In regards to claim 1, Park (Figs. 1-8 and associated text and items) discloses a method, comprising: forming a plurality of transistors (item 122) in a first wafer (item 121 or D2), wherein a first surface (top surface) of the first wafer (item 121 or D2) includes a first plurality of bonding pads (item 128) electrically coupled to the transistors (item 122); forming a memory array (items 110, 130) in a second wafer (item 111, D1 or D3), wherein the memory array (items 110, 130) includes a plurality of tunnel junction stacks (item 133, MTJ stacks, paragraphs 50, 51), and wherein a second surface (top surface) of the second wafer (item 111, D1 or D3) includes a second plurality of bonding pads (item 118) electrically coupled to the tunnel junction stacks (item 133, MTJ stacks, paragraphs 50, 51); bonding the first surface (top surface) of the first wafer (item 121 or D2) with the second surface (top surface) of the second wafer (item 111, D1 or D3), such that the transistors (item 122) are coupled to the memory array (item 133, MTJ stacks, paragraphs 50, 51) through the first plurality of bonding pads (item 128) and the second plurality of bonding pads (item 118). Park (paragraph 55) disclose that in some embodiments, that D3, which includes the memory array (item 130) including MTJ stacks (item 133) may be formed on D2 which includes the plurality of transistors (item 122). Examiner notes that Park broadly teaches that the memory arrays can include NAND or magnetic tunnel junctions.
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Park for the purpose of an MRAM or RRAM device.
Alternatively, in regards to claim 1, Park (Figs. 1-4 and associated text and items) discloses a method, comprising: forming a plurality of transistors (item 122) in a first wafer (item 121 or D2), wherein a first surface (top surface) of the first wafer (item 121 or D2) includes a first plurality of bonding pads (item 128) electrically coupled to the transistors (item 122); forming a memory array (items 110, 130) in a second wafer (item 111, D1), wherein the memory array (items 110) includes a plurality of memory cells (shown but not labeled, paragraph 29), and wherein a second surface (top surface) of the second wafer (item 111, D1) includes a second plurality of bonding pads (item 118) electrically coupled memory cells (shown but not labeled); bonding the first surface (top surface) of the first wafer (item 121 or D2) with the second surface (top surface) of the second wafer (item 111, D1), such that the transistors (item 122) are coupled to the memory array (item 110) through the first plurality of bonding pads (item 128) and the second plurality of bonding pads (item 118), but does not specifically disclose wherein the memory array (items 110) includes a plurality of tunnel junction stacks.
However, Park (Figs. 5-8 and associated text) disclose wherein the memory array (items 130) includes a plurality of tunnel junction stacks (item 133). Park (paragraph 55) also discloses that in some embodiments, that D3, which includes the memory array (item 130) including MTJ stacks (item 133) may be formed on D2 which includes the plurality of transistors (item 122).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to replace the first circuit/memory array (item 110) with the third circuit/memory array (item 130) of Park for the purpose of an MRAM or RRAM device.
As evidenced by ZHAO (Figs. 1-8 and associated text) discloses that one can bond the first surface (top surface) of a first wafer (First Wafer) with a second surface (bottom surface) of the second wafer (Second Wafer), such that the transistors (write transistors) are coupled to the memory array (memory array including MTJ stacks) through the first plurality of bonding pads (shown but not labeled) and the second plurality of bonding pads (shown but not labeled).
Therefore it would have bee obvious to one of ordinary skill in the art to before the effective filing date to incorporate the teachings of ZHAO for the purpose of and electrical connection.
Park as evidenced/modified by ZHAO does not specifically disclose ferroelectric tunnel junction stacks.
As evidence by MAKALA (paragraphs 108, 109, 122, 149, 151, Figs. 1-44 and associated text), the memory array can include MTJ stacks (item 150, Fig. 30) or FTJ stacks (Fig. 1D, paragraph 55) and performing thermal anneal to improve the crystallinity of the FTJ stacks (paragraphs 58, 87) and after the performing of the thermal treatment (paragraph 58), bonding the first surface of the first wafer with the second surface of the second wafer (paragraphs, 6, 45).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of MAKALA for the purpose improving the crystallinity of the ferroelectric material (paragraphs 58, 87) and having a FTJ, MRAM, PCRAM or PRAM memory devices (paragraphs 109, 122, 149, 151).
As further evidenced by Kim (paragraph 86, Figs. 5E, 7 and associated text), a thermal treatment (item 704) can be performed to a MTJ stack before bonding (Figs. 5E and 7).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Kim as well for the purpose improving the crystallinity of the FTJ stack of ZHAO as modified by MAKALA.
Therefore Park as evidenced/modified by ZHAO and as evidenced/modified by MAKALA or Kim discloses performing a thermal anneal treatment to the FTJ stacks in the second wafer without subjecting any transistor to the thermal treatment.
In regards to claim 2, Park (paragraph 55, Figs. 1-8 and associated text and items) as evidenced/modified by ZHAO (Figs. 1-8 and associated text) as evidenced and/or modified by MAKALA (paragraphs 108, 109, 122, 149, 151, Figs. 1-44 and associated text) and/or Kim (paragraph 86, Figs. 5E, 7 and associated text) discloses wherein the forming of the memory array includes forming signal lines (WL1-WL 8 or BL1, BL2, ZHAO) coupled to the FTJ stacks (ZHAO stacks as modified by MAKALA), wherein at least some of the second plurality of bonding pads (shown but not labeled in ZHAO) are coupled to the signal lines of the memory array (WL1-WL 8 or BL1, BL2, ZHAO).
In regards to claim 3, Park (paragraph 55, Figs. 1-8 and associated text and items) as evidenced/modified by ZHAO (Figs. 1-8 and associated text) as evidenced and/or modified by MAKALA (paragraphs 108, 109, 122, 149, 151, Figs. 1-44 and associated text) and/or Kim (paragraph 86, Figs. 5E, 7 and associated text) discloses wherein the forming of the signal lines (WL1-WL 8 or BL1, BL2, ZHAO) includes forming word lines and bit lines (WL1-WL 8 and BL1, BL2, ZHAO) of the memory array.
In regards to claim 4, Park (paragraph 55, Figs. 1-8 and associated text and items) as evidenced/modified by ZHAO (Figs. 1-8 and associated text) as evidenced and/or modified by MAKALA (paragraphs 108, 109, 122, 149, 151, Figs. 1-44 and associated text) and/or Kim (paragraph 86, Figs. 5E, 7 and associated text) discloses wherein each of the signal lines (WL1-WL 8 and/or BL1, BL2, ZHAO) of the memory array is coupled to at least one of the second plurality of bonding pads (shown but not labeled, ZHAO).
In regards to claim 5, Park (paragraph 55, Figs. 1-8 and associated text and items) as evidenced/modified by ZHAO (Figs. 1-8 and associated text) as evidenced and/or modified by MAKALA (paragraphs 108, 109, 122, 149, 151, Figs. 1-44 and associated text) and/or Kim (paragraph 86, Figs. 5E, 7 and associated text) discloses wherein after the bonding the second wafer is free of transistors.
In regards to claim 6, Park (paragraph 55, Figs. 1-8 and associated text and items) as evidenced/modified by ZHAO (Figs. 1-8 and associated text) as evidenced and/or modified by MAKALA (paragraphs 108, 109, 122, 149, 151, Figs. 1-44 and associated text) and/or Kim (paragraph 86, Figs. 5E, 7 and associated text) discloses wherein after the bonding among the transistors (write transistors, ZHAO) coupled to the memory array, each of the transistors (write transistors, ZHAO) is associated with multiple FTJ stacks (ZHAO stacks as modified by MAKALA) in the memory array.
In regards to claim 7, Park (paragraph 55, Figs. 1-8 and associated text and items) as evidenced/modified by ZHAO (Figs. 1-8 and associated text) as evidenced and/or modified by MAKALA (paragraphs 108, 109, 122, 149, 151, Figs. 1-44 and associated text) and/or Kim (paragraph 86, Figs. 5E, 7 and associated text) discloses forming a plurality of selectors (Selector transistors), wherein after the bonding each of the FTJ stacks (ZHAO stacks as modified by MAKALA) is coupled to one of the selectors (Selector transistors).
In regards to claim 8, Park (paragraph 55, Figs. 1-8 and associated text and items) as evidenced/modified by ZHAO (Figs. 1-8 and associated text) as evidenced and/or modified by MAKALA (paragraphs 108, 109, 122, 149, 151, Figs. 1-44 and associated text) and/or Kim (paragraph 86, Figs. 5E, 7 and associated text) discloses wherein the selectors (Selector transistors, ZHAO) are formed in the second wafer (Second Wafer, ZHAO).
In regards to claim 9, Park (paragraph 55, Figs. 1-8 and associated text and items) as evidenced/modified by ZHAO (Figs. 1-8 and associated text) as evidenced and/or modified by MAKALA (paragraphs 108, 109, 122, 149, 151, Figs. 1-44 and associated text) and/or Kim (paragraph 86, Figs. 5E, 7 and associated text) discloses wherein the forming of the selectors (item 134) includes forming a plurality of metal-insulator-metal structures (paragraph 67).
In regards to claim 10, Park (paragraph 55, Figs. 1-8 and associated text and items) as evidenced/modified by ZHAO (Figs. 1-8 and associated text) as evidenced and/or modified by MAKALA (paragraphs 108, 109, 122, 149, 151, Figs. 1-44 and associated text) and/or Kim (paragraph 86, Figs. 5E, 7 and associated text) discloses wherein the thermal treatment comprises a temperature between about 400°C and about 1000°C (paragraphs 72, 87 MAKALA, paragraph 96, Fig.7, item 704, Kim).
In regards to claim 11, Park (Figs. 1-8 and associated text and items) discloses a method, comprising: forming a plurality of transistors (item 122) in a first wafer (item 121 or D2); forming a first redistribution layer (item 124 plus 128) on the first wafer (item 121 or D2), wherein the first redistribution layer (item 124 plus 128) includes a first plurality of bonding pads (item 128) that are associated with the plurality of transistors (item 122); forming a plurality of memory cells (110, paragraph 29) in a second wafer (item 111 or D1); forming a second redistribution layer (items 116 plus 118) on the second wafer (item 111 or D1), wherein the second redistribution layer (items 116 plus 118) includes a second plurality of bonding pads (item 118) that are associated with the plurality of memory cells (item 113, paragraph 29); bonding the second wafer (item 111 or D1) to the first wafer (item 121 or D2), wherein each of the first plurality of bonding pads (item 128) is bonded to a corresponding one in the second plurality of bonding pads (item 118). Park (Figs. 5-8 and associated text) also disclose wherein the memory cells (items 130) can include a plurality of tunnel junction stacks (item 133) and/or vertical NAND (item 110). Park (paragraph 55) also discloses that in some embodiments, that D3, which includes the memory array (item 130) including MTJ stacks (item 133) may be formed on D2 which includes the plurality of transistors (item 122). Park (Figs. 1-8 and associated text and items) further discloses forming only memory array (items 110, 130) in/on/within a device/wafer/substrate (items 111, D1, D3) and wherein the memory array include can include a plurality of magnetic tunnel junctions (item 133).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to replace the first circuit/memory array (item 110) with the third circuit/memory array (item 130) of Park for the purpose of an MRAM or RRAM device.
As evidence by ZHAO (Figs. 1-8 and associated text) a first redistribution layer (layer shown above write transistor, shown but not labeled, Figs. 2, 4, 6) can be formed the first wafer (Frist wafer), wherein the first redistribution layer (layer shown above write transistor, shown but not labeled, Figs. 2, 4, 6) includes a first plurality of bonding pads (pads and/or vias shown above write transistor, shown but not labeled, Figs. 2, 4, 6) that are associated with the plurality of transistors (write transistor); forming a plurality of memory cells (plurality of MTJ stacks) in a second wafer (Second Wafer); forming a second redistribution layer (layer shown below MTJ stacks shown but not labeled, Figs. 2, 4, 6) on the second wafer (Second Wafer), wherein the second redistribution layer (layer shown below MTJ stacks shown but not labeled, Figs. 2, 4, 6) includes a second plurality of bonding pads (pads and/or vias shown below MTJ stacks shown but not labeled, Figs. 2, 4, 6) that are associated with the plurality of memory cells (MTJ stacks); bonding the second wafer (Second Wafer) to the first wafer (First Wafer), wherein each of the first plurality of bonding pads (pads and/or vias shown above write transistor, shown but not labeled, Figs. 2, 4, 6) is bonded to a corresponding one in the second plurality of bonding pads (pads and/or vias shown below MTJ stacks shown but not labeled, Figs. 2, 4, 6).
Therefore it would have been obvious to one of ordinary skill in the art to before the effective filing date to incorporate the teachings of ZHAO for the purpose of and electrical connection.
Park as evidenced/modified by ZHAO does not specifically disclose but does not specifically disclose performing a thermal treatment to the plurality of memory cells in the second wafer to increase a crystallization quality of the memory cells without subjecting any transistor to the thermal treatment; and after the performing of the thermal treatment, bonding the second wafer to the first wafer.
As evidence by MAKALA (paragraphs 108, 109, 122, 149, 151, Figs. 1-44 and associated text), the memory array can include MTJ stacks (item 150, Fig. 30) or FTJ stacks (Fig. 1D, paragraph 55) and performing thermal anneal to improve the crystallinity of the FTJ stacks (paragraphs 58, 87) and after the performing of the thermal treatment (paragraph 58), bonding the first surface of the first wafer with the second surface of the second wafer (paragraphs, 6, 45).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of MAKALA for the purpose of improving the crystallinity of the ferroelectric material (paragraphs 58, 87) and having a FTJ, MRAM, PCRAM or PRAM memory devices (paragraphs 109, 122, 149, 151).
As further evidenced by Kim (paragraph 86, Figs. 5E, 7 and associated text), a thermal treatment (item 704) can be performed to a MTJ stack before bonding (Figs. 5E and 7).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Kim as well for the purpose improving the crystallinity of the FTJ stack of ZHAO as modified by MAKALA.
Therefore Park as evidenced/modified by ZHAO and as evidenced/modified by MAKALA or Kim discloses performing a thermal anneal treatment to the plurality of memory cells in the second wafer to improve the crystallinity of the memory cells without subjecting any transistor to the thermal treatment.
In regards to claim 12, Park (paragraph 55, Figs. 1-8 and associated text and items) as evidenced/modified by ZHAO (Figs. 1-8 and associated text) as evidenced and/or modified by MAKALA (paragraphs 108, 109, 122, 149, 151, Figs. 1-44 and associated text) and/or Kim (paragraph 86, Figs. 5E, 7 and associated text) discloses forming top signal lines (WL1-WL-8 or BL1, BL2, ZHAO) and bottom signal lines (WL1-WL-8 or BL1, BL2, ZHAO) sandwiching the memory cells (MTJ stacks, ZHAO), wherein each of the top and bottom signal lines (WL1-WL-8 and BL1, BL2, ZHAO) is associated with one of the second plurality of bonding pads (pads and/or vias shown below MTJ stacks shown but not labeled, Figs. 2, 4, 6, ZHAO).
In regards to claim 13, Park (paragraph 55, Figs. 1-8 and associated text and items) as evidenced/modified by ZHAO (Figs. 1-8 and associated text) as evidenced and/or modified by MAKALA (paragraphs 108, 109, 122, 149, 151, Figs. 1-44 and associated text) and/or Kim (paragraph 86, Figs. 5E, 7 and associated text) discloses wherein the forming of the memory cells (MTJ, Park, MTJ stacks, ZHAO as modified by MAKALA) includes forming a selector (Selector Transistor) electrically coupled to a ferroelectric film (item 30L, MAKALA).
In regards to claim 14, Park (paragraph 55, Figs. 1-8 and associated text and items) as evidenced/modified by ZHAO (Figs. 1-8 and associated text) as evidenced and/or modified by MAKALA (paragraphs 108, 109, 122, 149, 151, Figs. 1-44 and associated text) and/or Kim (paragraph 86, Figs. 5E, 7 and associated text) discloses wherein the ferroelectric film (item 30L, MAKALA) has a thickness less than about 5 nm (paragraph 58, MAKALA, 2nm to 30 nm).
It would have been obvious to one having ordinary skill in the art at the time of the invention to modify the invention to include a ferroelectric film having a thickness less than about 5 nm, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art (In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980)). However, the Applicant has not given any criticality as to where this thickness yields an unexpected result or advantage.
In regards to claim 15, Park (paragraph 55, Figs. 1-8 and associated text and items) as evidenced/modified by ZHAO (Figs. 1-8 and associated text) as evidenced and/or modified by MAKALA (paragraphs 108, 109, 122, 149, 151, Figs. 1-44 and associated text) and/or Kim (paragraph 86, Figs. 5E, 7 and associated text) does not specifically disclose wherein a number of the plurality of transistors (item 122, Park, Write transistor, ZHAO) is less than a number of the first plurality of bonding pads (pads and/or vias shown above write transistors shown but not labeled, Figs. 2, 4, 6).
It would have been obvious to one having ordinary skill in the art at the time of the invention to modify the invention to include a number transistors being less than the number of bonding pads for the purpose of design choice, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art (In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980)).
In regards to claim 16, Park (paragraph 55, Figs. 1-8 and associated text and items) as evidenced/modified by ZHAO (Figs. 1-8 and associated text) as evidenced and/or modified by MAKALA (paragraphs 108, 109, 122, 149, 151, Figs. 1-44 and associated text) and/or Kim (paragraph 86, Figs. 5E, 7 and associated text) does not specifically disclose wherein a number of the second plurality of bonding pads (item 118, Park, pads and/or vias shown below MTJ stacks shown but not labeled, Figs. 2, 4, 6) is less than a number of the memory cells ( MTJ, Park, MTJ stacks, ZHAO).
It would have been obvious to one having ordinary skill in the art at the time of the invention to modify the invention to include a number of second bonding pads less than the number of memory cells for the purpose of design choice, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art (In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980)).
In regards to claim 17, Park (paragraph 55, Figs. 1-8 and associated text and items) discloses a method, comprising: forming a plurality of transistors (item 122) in a first wafer (item 121 or D2); forming a first interconnect structure (item 123 ) coupled to the transistors (item 122); forming a first redistribution layer (items 124 plus 128) coupled to the first interconnect structure (item 123); forming a memory array (item 110) in a second wafer (item 111 or D1); forming a second interconnect structure (vias shown but not labeled between items 116 and items 117, 115, 114 and 113) coupled to the memory array (item 110); forming a second redistribution layer (item 116 plus 118) coupled to the second interconnect structure (vias under item 116); bonding the second wafer (item 111 or D1) to the first wafer (item 121 or D2), such that the transistors (item 122) are coupled to the memory array (item 110) through the first interconnect structure (item 123), the first redistribution layer (items 124 plus 128), the second redistribution layer (item 116 plus 118), and the second interconnect structure (vias shown but not labeled between items 116 and items 117, 115, 114 and 113), but does not specifically disclose wherein the memory array (item 110) includes a plurality of ferroelectric tunnel junction (FTJ) stacks (MTJ stacks).
Park (Figs. 5-8 and associated text) also disclose wherein the memory cells (items 130) can include a plurality of tunnel junction stacks (item 133) and/or vertical NAND (item 110). Park (paragraph 55) also discloses that in some embodiments, that D3, which includes the memory array (item 130) including MTJ stacks (item 133) may be formed on D2 which includes the plurality of transistors (item 122). Park (Figs. 1-8 and associated text and items) further discloses forming only memory array (items 110, 130) in/on/within a device/wafer/substrate (items 111, D1, D3) and wherein the memory array include can include a plurality of magnetic tunnel junctions (item 133).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to replace the first circuit/memory array (item 110) with the third circuit/memory array (item 130) of Park for the purpose of an MRAM or RRAM device.
As evidenced by ZHAO (Figs. 1-8 and associated text), once can form a plurality of transistors (write transistor) in a first wafer (First Wafer); form a first interconnect structure (layer shown but not labeled on top of write transistors, Figs. 2, 4, 6) coupled to the transistors (write transistor); form a first redistribution layer (pads shown but not labeled on top of the layer, shown but not label above the write transistors, Figs. 2, 4, 6) coupled to the first interconnect structure (layer shown but not labeled on top of write transistors, Figs. 2, 4, 6); form a memory array (MTJ stacks) in a second wafer (Second Wafer), wherein the memory array (MTJ stacks) includes a plurality of ferroelectric tunnel junction (FTJ) stacks (MTJ stacks); forma second interconnect structure (layer shown but not labeled on below the MTJ stacks, Figs. 2, 4, 6) coupled to the memory array (MTJ stacks); form a second redistribution layer (pads shown but not labeled below the layer, shown but not labeled, below the MTJ stacks, Figs. 2, 4, 6) coupled to the second interconnect structure (layer shown but not labeled on below the MTJ stacks, Figs. 2, 4, 6); bond the second wafer (Second Wafer) to the first wafer (First Wafer), such that the transistors (write transistors) are coupled to the memory array (MTJ stacks) through the first interconnect structure (layer shown but not labeled on top of write transistors, Figs. 2, 4, 6), the first redistribution layer (pads shown but not labeled on top of the layer, shown but not label above the write transistors, Figs. 2, 4, 6), the second redistribution layer (pads shown but not labeled below the layer, shown but not labeled, below the MTJ stacks, Figs. 2, 4, 6), and the second interconnect structure (layer shown but not labeled on below the MTJ stacks, Figs. 2, 4, 6).
Therefore it would have been obvious to one of ordinary skill in the art to before the effective filing date to incorporate the teachings of ZHAO for the purpose of and electrical connection, since it has been held that constructing a formerly integral structure in various elements involves only routine skill in the art (Nerwin v. Erlichman, 168 USPQ 177, 179).
Park as evidenced by ZHAO does not specifically disclose but does not specifically disclose performing a thermal treatment to the plurality of memory cells in the second wafer to increase a crystallization quality of the memory cells; and after the performing of the thermal treatment, bonding the second wafer to the first wafer.
As evidence by MAKALA (paragraphs 108, 109, 122, 149, 151, Figs. 1-44 and associated text), the memory array can include MTJ stacks (item 150, Fig. 30) or FTJ stacks (Fig. 1D, paragraph 55) and performing thermal anneal to improve the crystallinity of the FTJ stacks (paragraphs 58, 87) and after the performing of the thermal treatment (paragraph 58), bonding the first surface of the first wafer with the second surface of the second wafer (paragraphs, 6, 45).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of MAKALA for the purpose improving the crystallinity of the ferroelectric material (paragraphs 58, 87) and having a FTJ, MRAM, PCRAM or PRAM memory devices (paragraphs 109, 122, 149, 151).
As further evidenced by Kim (paragraph 86, Figs. 5E, 7 and associated text), a thermal treatment (item 704) can be performed to a MTJ stack before bonding (Figs. 5E and 7).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Kim as well for the purpose improving the crystallinity of the FTJ stack of ZHAO as modified by MAKALA.
Therefore ZHAO as evidenced/modified by Park and as evidenced/modified by MAKALA or Kim discloses performing a thermal anneal treatment to the second wafer to improve the crystallinity of the ferroelectric films in the FTJ stacks without subjecting any transistor to the thermal treatment.
In regards to claim 18, Park (paragraph 55, Figs. 1-8 and associated text and items) as evidenced/modified by ZHAO (Figs. 1-8 and associated text) as evidenced and/or modified by MAKALA (paragraphs 108, 109, 122, 149, 151, Figs. 1-44 and associated text) and/or Kim (paragraph 86, Figs. 5E, 7 and associated text) discloses wherein the forming of the memory array includes forming a plurality of selectors (selector transistors, ZHAO) coupled to the FTJ stacks (MTJ, Park, MTJ stacks, ZHAO as evidenced/modified by MAKALA).
In regards to claim 19, Park (paragraph 55, Figs. 1-8 and associated text and items) as evidenced/modified by ZHAO (Figs. 1-8 and associated text) as evidenced and/or modified by MAKALA (paragraphs 108, 109, 122, 149, 151, Figs. 1-44 and associated text) and/or Kim (paragraph 86, Figs. 5E, 7 and associated text) discloses wherein a number of the selectors (select transistors) equals a number of the FTJ stacks (MTJ, Park, MTJ stacks, ZHAO as evidenced/modified by MAKALA).
It would have been obvious to one having ordinary skill in the art at the time of the invention to modify the invention to include an equal number of selectors and FTJ stacks for the purpose design choice and one on one relationship, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art (In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980)).
In regards to claim 20, Park (paragraph 55, Figs. 1-8 and associated text and items) as evidenced/modified by ZHAO (Figs. 1-8 and associated text) as evidenced and/or modified by MAKALA (paragraphs 108, 109, 122, 149, 151, Figs. 1-44 and associated text) and/or Kim (paragraph 86, Figs. 5E, 7 and associated text) discloses wherein the bonding couples at least one of the transistors (item 122, Park, write transistors, ZHAO) to more than one of the FTJ stacks (MTJ stacks, ZHAO as evidenced/modified by MAKALA).
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over ) Park et al. (Park) (US 2020/0203328 A1) as evidenced by or in view of MAKALA et al. (MAKALA) (US 2021/0408019 A1) or Kim et al. (Kim) (US 2019/0206933 A1).
In regards to claim 11, Park (Figs. 1-8 and associated text and items) discloses a method, comprising: forming a plurality of transistors (item 122) in a first wafer (item 121 or D2); forming a first redistribution layer (item 124 plus 128) on the first wafer (item 121 or D2), wherein the first redistribution layer (item 124 plus 128) includes a first plurality of bonding pads (item 128) that are associated with the plurality of transistors (item 122); forming a plurality of memory cells (110, paragraph 29) in a second wafer (item 111 or D1); forming a second redistribution layer (items 116 plus 118) on the second wafer (item 111 or D1), wherein the second redistribution layer (items 116 plus 118) includes a second plurality of bonding pads (item 118) that are associated with the plurality of memory cells (item 113, paragraph 29); bonding the second wafer (item 111 or D1) to the first wafer (item 121 or D2), wherein each of the first plurality of bonding pads (item 128) is bonded to a corresponding one in the second plurality of bonding pads (item 118). Park (Figs. 5-8 and associated text) also disclose wherein the memory cells (items 130) can include a plurality of tunnel junction stacks (item 133) and/or vertical NAND (item 110). Park (paragraph 55) also discloses that in some embodiments, that D3, which includes the memory array (item 130) including MTJ stacks (item 133) may be formed on D2 which includes the plurality of transistors (item 122). Park (Figs. 1-8 and associated text and items) further discloses forming only memory array (items 110, 130) in/on/within a device/wafer/substrate (items 111, D1, D3) and wherein the memory array include can include a plurality of magnetic tunnel junctions (item 133).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to replace the first circuit/memory array (item 110) with the third circuit/memory array (item 130) of Park for the purpose of an MRAM or RRAM device.
Park does not specifically disclose but does not specifically disclose performing a thermal treatment to the plurality of memory cells in the second wafer to increase a crystallization quality of the memory cells without subjecting any transistor to the thermal treatment; and after the performing of the thermal treatment, bonding the second wafer to the first wafer.
As evidence by MAKALA (paragraphs 108, 109, 122, 149, 151, Figs. 1-44 and associated text), the memory array can include MTJ stacks (item 150, Fig. 30) or FTJ stacks (Fig. 1D, paragraph 55) and performing thermal anneal to improve the crystallinity of the FTJ stacks (paragraphs 58, 87) and after the performing of the thermal treatment (paragraph 58), bonding the first surface of the first wafer with the second surface of the second wafer (paragraphs, 6, 45).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of MAKALA for the purpose of improving the crystallinity of the ferroelectric material (paragraphs 58, 87) and having a FTJ, MRAM, PCRAM or PRAM memory devices (paragraphs 109, 122, 149, 151).
As further evidenced by Kim (paragraph 86, Figs. 5E, 7 and associated text), a thermal treatment (item 704) can be performed to a MTJ stack before bonding (Figs. 5E and 7).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Kim as well for the purpose improving the crystallinity of the FTJ stack of ZHAO as modified by MAKALA.
Therefore Park as evidenced/modified by ZHAO and as evidenced/modified by MAKALA or Kim discloses performing a thermal anneal treatment to the plurality of memory cells in the second wafer to improve the crystallinity of the memory cells without subjecting any transistor to the thermal treatment.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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TELLY D. GREEN
Examiner
Art Unit 2898
/TELLY D GREEN/Primary Examiner, Art Unit 2898 February 15, 2026