DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Office acknowledges receipt on 18 May 2026 of Applicants’ amendments in which claims 16, 21, 29, 30, and 35 are amended. In view of the amendments, the Office withdraws the drawing objections, section 112(a) rejections, section 112(b) rejections, and section 112(d) rejection identified in the Office Communication dated 18 February 2026.
Response to Arguments
Applicants’ arguments filed 11 November 2025 have been fully considered but they are not persuasive.
Applicants argue in the fourth paragraph of page 2 and with respect to independent claim 16 that the applied art does not teach the subject matter newly added to the claim whereby “a conductive line is formed in the dielectric layer,” “the first through via structure is separated from the conductive line,” and “a conductive via of the interconnection structure is coupled to the conductive line.” Amended claim 16 is rejected over the combined teachings of Chen and Hiroki. Obviousness can be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so. MPEP §2143.01. As this principle applies to the present circumstance, Chen teaches in Figs. 5A and 6: (1) a conductive line (130a of 610”) is formed in the dielectric layer (layer of 150 & 160 of 610”), (2) the first through via structure (154 of 610”) is separated from the conductive line (130a of 610”), and (3) a conductive via (114c of 610) of the interconnection structure (114 of 610) is coupled (electrically) to the conductive line (130a of 610”).
Applicants argue in the third paragraph of page 3 and with respect to independent claim 21 that the applied art does not teach the subject matter newly added to the claim whereby “the first through via structure has a first surface aligned with a top surface of the first dielectric layer and a second surface opposite to the first surface, and a width of the first surface is greater than a width of the second surface,” “forming a conductive pad over the second surface of the first through via structure,” and “the first surface of the first through via structure is coupled to the second through via structure, and the second surface of the first through via structure is coupled to the conductive pad.” Amended claim 21 is rejected over the combined teachings of Chen and Hiroki. Obviousness can be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so. MPEP §2143.01. As this principle applies to the present circumstance, Chen teaches in Figs. 5A and 6: (1) the first through via structure (154 of 610”) has a first surface (top surface in Fig. 5A) aligned with a top surface (top surface in Fig. 5A) of the first dielectric layer (150, 160 of 610”) and a second surface (bottom surface in Fig. 5A) opposite to the first surface (top surface in Fig. 5A), and a width of the first surface (top surface in Fig. 5A) is greater than a width of the second surface (bottom surface in Fig. 5A); (2) forming a conductive pad (154 of 610’) over the second surface (bottom surface in Fig. 5A, top surface in Fig. 6) of the first through via structure (154 of 610”); and (3) the first surface (top surface in Fig. 5A) of the first through via structure (154 of 610”) is coupled (electrically) to the second through via structure (154 of 610), and the second surface (bottom surface in Fig. 5A) of the first through via structure (154 of 610”) is coupled (electrically) to the conductive pad (154 of 610’).
Applicants argue in the fifth paragraph of page 4 and with respect to independent claim 30 that the applied art does not teach the subject matter newly added to the claim whereby “a top surface of the conductive via is aligned with a top surface of the optical isolation and aligned with a first surface of the second through via structure,” “forming a light-emitting element over the optical isolation, and contacting the first surface of the second through via structure and the conductive via,” and “exposing a second surface of the second through via structure opposite to the first surface, wherein a width of the first surface is greater than a width of the second surface.” Amended claim 30 is rejected over the combined teachings of Chen and Hiroki. Obviousness can be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so. MPEP §2143.01. As this principle applies to the present circumstance, Chen teaches in Figs. 5A and 6: (1) a top surface of the conductive via (172 of 610) is aligned with a top surface of the optical isolation (160 of 610) and aligned with a first surface (top surface in Figs. 1H, 5A) of the second through via structure (154 of 610) {Fig. 1H}; and (2) exposing a second surface (bottom surface in Figs. 1J, 5A) of the second through via structure (154 of 610) opposite to the first surface (top surface in Figs. 1J, 5A), wherein a width of the first surface (top surface in Figs. 1J, 5A) is greater than a width of the second surface (bottom surface in Figs. 1J, 5A). Hiroki teaches forming a light-emitting element over an optical isolation (301) and contacting a first surface (top surface in Fig. 3) of a second through via structure and a conductive via {see annotated copy of Hiroki’s Fig. 3 below; the light-emitting element includes a first electrode disposed between a light-emitting layer (303) and each of the second through via structure and the conductive via}. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chen’s method based on the teachings of Hiroki – for forming a light-emitting element over the optical isolation, and contacting the first surface of the second through via structure and the conductive via – so heat generated by the EL element can be effectively transferred to the rear surface metal layer through the second via structure, which has a low thermal resistance. Hiroki ¶0065. Additionally, the optical isolation provides separation and insulation between the two electrodes of the light-emitting element. Furthermore, the conductive supports distributing current more uniformly across the anode electrode of the light-emitting element.
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Claim(s) 16-25 and 27-35 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US20210375721A1) in view of Hiroki et al. (US20120206031A1).
Regarding claim 16, Chen teaches in Figs. 5A and 6 a method for forming a light-emitting package, comprising:
providing a first substrate (110 of 610”) having a device layer (active/passive devices of 610”) and a dielectric layer (layer of 150 & 160 of 610”) disposed thereon, wherein a conductive line (130a of 610”) is formed in the dielectric layer (layer of 150 & 160 of 610”) {¶0030; insulating layer 160 is formed of a material same as from that of insulating layer 150; ¶0047, the semiconductor device 610″ can be one of the semiconductor devices 100, 200, 300, 400, or 500; ¶0018, Active and/or passive devices, such as transistors, diodes, capacitors, resistors, etc., may be formed in and/or on the semiconductor substrate 110};
forming a first through via structure (154 of 610”) penetrating through the dielectric layer (layer of 150 & 160 of 610”), the device layer (active/passive devices of 610”) and a portion of the first substrate (110 of 610”) {Fig. 1H; ¶0032}, wherein a first surface (upper surface) of the first through via structure (154 of 610”) is aligned with a top surface of the dielectric layer (layer of 150 & 160 of 610”), and the first through via structure (154 of 610”) is separated from the conductive line (130a of 610”) {Fig. 5A};
providing a second substrate (110 of 610) having an interconnection structure (114 of 610) disposed thereon {Fig. 5A; ¶0020, interconnection structure 114; ¶0045, each of the semiconductor devices 610 and 610′ may be the semiconductor device 100, 200, 300, 400, or 500};
forming a second through via structure (154 of 610) penetrating through the interconnection structure (114 of 610) {Fig. 1E; ¶0029};
exposing the second through via structure (154 of 610) {Fig. 5A, each end of 154 is exposed}; and
bonding the interconnection structure (114 of 610) to the dielectric layer (layer of 150 & 160 of 610”) {indirectly}, wherein the second through via structure (154 of 610) is electrically connected to the first through via structure (154 of 610”) {Fig. 6; ¶0046}, and a conductive via (114c of 610) of the interconnection structure (114 of 610) is coupled (electrically) to the conductive line (130a of 610”) {Figs. 5A, 6}.
Chen does not teach forming a light-emitting element over the interconnection structure and contacting the second through via structure; and exposing the second through via structure after the forming of the light-emitting element.
In an analogous art, Hiroki teaches forming a light-emitting element over an interconnection structure and contacting a second through via structure {see annotated copy of Hiroki’s Fig. 3 below}. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chen’s method based on the teachings of Hiroki – for forming a light-emitting element over the interconnection structure and contacting the second through via structure – so heat generated by the EL element can be effectively transferred to the rear surface metal layer through the second via structure, which has a low thermal resistance. Hiroki ¶0065. Because this modification may form something (e.g., a light-emitting element) over one of the two exposed surfaces of Chen’s second through via structure (154 of 610) prior to bonding 610 to 610’ and 610”, it follows that Chen’s second through via structure (154 of 610) may be exposed after the forming of the light-emitting element (as taught by Hiroki) {e.g., Chen teaches in Figs. 1I and 1J and paragraph [0034] a need to remove intervening material (e.g., a substrate) to gain access to a through-hole conductor for subsequent interconnection}. Moreover, there are only two alternatives (both of which would have been recognized by a skilled artisan): (1) exposing the second through via structure after forming the light-emitting element and (2) exposing the second through via structure before forming the light-emitting element; and one or both ends of Chen’s second through via structure (154 of 610) is/are exposed regardless of which alternative occurs; and a person of ordinary skill has good reason to pursue the known options within his or her technical grasp. MPEP §2143((I)(E).
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Regarding claim 17, Chen as modified by Hiroki teaches the method of claim 16, but Chen does not teach wherein the second through via structure is electrically connected to the light-emitting element.
Hiroki teaches in paragraphs [0065] and [0067] the second through via structure is electrically connected to the light-emitting element {see annotated copy of Hiroki’s Fig. 3 above}. The motivation for this modification is identified with respect to base claim 16.
Regarding claim 18, Chen as modified by Hiroki teaches the method of claim 16, and Chen further teaches further comprising: performing a first thinning operation to reduce a thickness of the first substrate (110 of 610”) and to expose a second surface (bottom surface) of the first through via structure (154 of 610”) {Fig. 1J; ¶0034}.
Regarding claim 19, Chen as modified by Hiroki teaches the method of claim 18, and Chen further teaches further comprising: forming a conductive pad (182 between 610’ and 610”) over the second surface (bottom surface) of the first through via structure (154 of 610”), wherein the conductive pad (182 between 610’ and 610”) is configured (made of conductive metal, ¶0033) to receive an input voltage {Fig. 6; ¶0046}.
Examiner’s Note: alternatively or supplementary, the recitation of “receive an input voltage” constitutes a manner of operating the claimed structure (e.g., a description of what is done to the light-emitting package created by the claimed method), rather than functional language (i.e., a description of what the light-emitting package – created by the claimed method – does), and does not further limit/define the claimed method. See MPEP §2114(II).
Regarding claim 20, Chen as modified by Hiroki teaches the method of claim 16, and Chen further teaches further comprising: performing a second thinning operation to expose an end of the second through via structure (154 of 610) through the interconnection structure (114 of 610) {Fig. 1J; ¶0034}.
Regarding claim 21, Chen teaches in Figs. 5A and 6 a method for forming a light-emitting package, comprising:
providing a first substrate (110 of 610”) having a device layer (active/passive devices of 610”) and a first dielectric layer (150, 160 of 610”) disposed thereon {¶0047, the semiconductor device 610″ can be one of the semiconductor devices 100, 200, 300,400, or 500; ¶0018, Active and/or passive devices, such as transistors, diodes, capacitors, resistors, etc., may be formed in and/or on the semiconductor substrate 110; ¶0020, dielectric layers 114 a};
forming a first through via structure (154 of 610”) penetrating through the first dielectric layer (150, 160 of 610”), the device layer (active/passive devices of 610”) and a portion of the first substrate (110 of 610”) {Fig. 1E; ¶0029};
wherein the first through via structure (154 of 610”) has a first surface (top surface in Fig. 5A) aligned with a top surface (top surface in Fig. 5A) of the first dielectric layer (150, 160 of 610”) and a second surface (bottom surface in Fig. 5A) opposite to the first surface (top surface in Fig. 5A), and a width of the first surface (top surface in Fig. 5A) is greater than a width of the second surface (bottom surface in Fig. 5A) {Fig. 5A};
forming a conductive pad (154 of 610’) over the second surface (bottom surface in Fig. 5A, top surface in Fig. 6) of the first through via structure (154 of 610”) {Figs. 5A, 6};
providing a second substrate (110 of 610) having an interconnection structure (114, 120, 150 of 610) disposed thereon {Fig. 5A; ¶0020};
forming an optical isolation (160 of 610) over the interconnection structure (114, 120, 150 of 610) {Fig. 5A; ¶0030};
forming a second through via structure (154 of 610) penetrating through the interconnection structure (114, 120, 150 of 610), wherein a top surface of the second through via structure (154 of 610) is aligned with a top surface of the optical isolation (160 of 610) {Fig. 1H; ¶0032};
exposing the second through via structure (154 of 610) {Fig. 5A, each end of 154 is exposed}; and
bonding the interconnection structure (114, 120, 150 of 610) to the first dielectric layer (114a of 610”) {indirectly}, the first surface (top surface in Fig. 5A) of the first through via structure (154 of 610”) is coupled (electrically) to the second through via structure (154 of 610), and the second surface (bottom surface in Fig. 5A) of the first through via structure (154 of 610”) is coupled (electrically) to the conductive pad (154 of 610’) {Fig. 6; ¶0046}.
Chen does not teach forming a light-emitting element over the optical isolation and contacting the second through via structure; and exposing the second through via structure after the forming of the light-emitting element.
Hiroki teaches forming a light-emitting element over the optical isolation (301) and contacting the second through via structure {see annotated copy of Hiroki’s Fig. 3 below}. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chen’s method based on the teachings of Hiroki – for forming a light-emitting element over the optical isolation and contacting the second through via structure – so heat generated by the EL element can be effectively transferred to the rear surface metal layer through the second via structure, which has a low thermal resistance. Hiroki ¶0065. Additionally, the optical isolation provides separation and insulation between the two electrodes of the light-emitting element. Because this modification may form something (e.g., a light-emitting element) over one of the two exposed surfaces of Chen’s second through via structure (154 of 610) prior to bonding 610 to 610’ and 610”, it follows that Chen’s second through via structure (154 of 610) may be exposed after the forming of the light-emitting element (as taught by Hiroki) {e.g., Chen teaches in Figs. 1I and 1J and paragraph [0034] a need to remove intervening material (e.g., a substrate) to gain access to a through-hole conductor for subsequent interconnection}. Moreover, there are only two alternatives (both of which would have been recognized by a skilled artisan): (1) exposing the second through via structure after forming the light-emitting element and (2) exposing the second through via structure before forming the light-emitting element; and one or both ends of Chen’s second through via structure (154 of 610) is/are exposed regardless of which alternative occurs; and a person of ordinary skill has good reason to pursue the known options within his or her technical grasp. MPEP §2143((I)(E).
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Regarding claim 22, Chen as modified by Hiroki teaches the method of Claim 21, and Chen further teaches wherein the forming of optical isolation (160 of 610) over the interconnect structure (114 of 610) further comprises:
forming a second dielectric layer (layer containing 150, 154, 174 of 610) over the interconnection structure (114, 120, 150 of 610) {Fig. 5A; ¶0027; ¶0030, insulating layer 160 is formed of a material same as from that of insulating layer 150};
forming the optical isolation (160 of 610) in the second dielectric layer (layer containing 150, 154, 174 of 610) {Fig. 5A; ¶0030}.
Regarding claim 23, Chen as modified by Hiroki teaches the method of Claim 22, and Chen further teaches further comprising:
forming a via opening (170/152) in the second dielectric layer (layer containing 150, 154, 174 of 610) {Figs. 1D, 1G; ¶0028, 0031}; and
forming a through via opening (152/170) in the second dielectric layer (layer containing 150, 154, 174 of 610) and the interconnection structure (114, 120, 150 of 610) {Figs. 1D, 1G; ¶0028, 0031}.
Regarding claim 24, Chen as modified by Hiroki teaches the method of Claim 23, and Chen further teaches wherein the forming of the via opening (152) is prior to the forming of the through via opening (170) {Figs. 1D, 1G; ¶0028, 0031}.
Regarding claim 25, Chen as modified by Hiroki teaches the method of Claim 23, and Chen further teaches wherein the forming of the through via opening (152) is prior to the forming of the via opening (170) {Figs. 1D, 1G; ¶0028, 0031}.
Regarding claim 27, Chen as modified by Hiroki teaches the method of Claim 21, and Chen further teaches further comprising: performing a first thinning operation to reduce a thickness of the first substrate (110 of 610”) and to expose the second surface (bottom surface in Figs. 1J, 5A) of the first through via structure (154 of 610”) {Fig. 1J; ¶0034}.
Regarding claim 28, Chen as modified by Hiroki teaches the method of Claim 27, and Chen further teaches wherein the first substrate (110 of 610”) comprises a conductive line (174 of 610’) disposed in the first dielectric layer (150, 160 of 610”), and a top surface of the conductive line (174 of 610’) is aligned with the top surface of the first dielectric layer (150, 160 of 610”) and the first surface (top surface in Fig. 5A) of the first through via structure (154 of 610”).
Regarding claim 29, Chen as modified by Hiroki teaches the method of Claim 21, and Chen further teaches wherein the exposing of the second through via structure (154 of 610) comprises: performing a second thinning operation to expose an end of the second through via structure (154 of 610) through the interconnection structure (114, 120, 150 of 610) {Fig. 1J; ¶0034}.
Regarding claim 30, Chen teaches in Figs. 5A and 6 a method for forming a light-emitting package, comprising:
providing a first substrate (110 of 610”) having a first through via structure (154 of 610”) {¶0047, the semiconductor device 610″ can be one of the semiconductor devices 100, 200, 300,400, or 500; Fig. 1E; ¶0029};
providing a second substrate (110 of 610) having an interconnection structure (114, 120 of 610) disposed thereon {Fig. 5A; ¶0020;
forming an optical isolation (160 of 610) over the interconnection structure (114, 120 of 610) {Fig. 5A; ¶0030};
forming a second through via structure (154 of 610) penetrating through the interconnection structure (114, 120 of 610) and forming a conductive via (172 of 610) coupled to the interconnection structure (114, 120 of 610) {Figs. 1E, 1H; ¶0029, 0032}, wherein a top surface of the conductive via (172 of 610) is aligned with a top surface of the optical isolation (160 of 610) and aligned with a first surface (top surface in Figs. 1H, 5A) of the second through via structure (154 of 610) {Fig. 1H};
exposing a second surface (bottom surface in Figs. 1J, 5A) of the second through via structure (154 of 610) opposite to the first surface (top surface in Figs. 1J, 5A), wherein a width of the first surface (top surface in Figs. 1J, 5A) is greater than a width of the second surface (bottom surface in Figs. 1J, 5A) {Figs. 1J, 5A; ¶0034}; and
bonding the interconnection structure (114, 120 of 610) to the first substrate (110 of 610”) {Fig. 6; ¶0046}.
Chen does not teach forming a light-emitting element over the optical isolation, and contacting the first surface of the second through via structure and the conductive via.
Hiroki teaches forming a light-emitting element over an optical isolation (301) and contacting a first surface (top surface in Fig. 3) of a second through via structure and a conductive via {see annotated copy of Hiroki’s Fig. 3 below}. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chen’s method based on the teachings of Hiroki – for forming a light-emitting element over the optical isolation, and contacting the first surface of the second through via structure and the conductive via – so heat generated by the EL element can be effectively transferred to the rear surface metal layer through the second via structure, which has a low thermal resistance. Hiroki ¶0065. Additionally, the optical isolation provides separation and insulation between the two electrodes of the light-emitting element. Furthermore, the conductive supports distributing current more uniformly across the anode electrode of the light-emitting element.
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Regarding claim 31, Chen as modified by Hiroki teaches the method of Claim 30, but Chen does not teach wherein the interconnection structure is electrically connected to the light-emitting element through the conductive via.
Hiroki teaches in paragraphs [0065] and [0067] the interconnection structure is electrically connected to the light-emitting element through the conductive via {see annotated copy of Hiroki’s Fig. 3 above}. The motivation for this modification is identified with respect to base claim 30.
Regarding claim 32, Chen as modified by Hiroki teaches the method of Claim 30, and Chen further teaches further removing a portion of the first substrate (110 of 610”) to expose an end of the first through via structure (154 of 610”) {Fig. 1J; ¶0034}.
Regarding claim 33, Chen as modified by Hiroki teaches the method of Claim 32, and Chen further teaches further comprising forming a conductive pad (182 between 610’ and 610”) over the end of the first through via structure (154 of 610”) {Fig. 6; ¶0046}.
Regarding claim 34, Chen as modified by Hiroki teaches the method of Claim 30, and Chen further teaches wherein the forming of the second through via structure (154 of 610) and the conductive via (172 of 610) further comprising:
forming a via opening (170) in a dielectric layer (150) {Fig. 1G; ¶0031}; and
forming a through via opening (152) in the dielectric layer (150) and the interconnection structure (114, 120 of 610) {Fig. 1D; ¶0028}.
Claim(s) 26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Hiroki as applied to claim 23 above, and further in view of Ludowise (US20050274970A1).
Regarding claim 26, Chen as modified by Hiroki teaches the method of Claim 23, and Chen further teaches further comprising filling the through via opening (152) and the via opening (170) with a material (metal) to form the second through via structure (154) and a conductive via (172).
Chen does not teach the material is a semiconductor material.
In an analogous art, Ludowise teaches in Fig. 1A paragraph [0015] that electrically and thermally conductive vias 118 may be made of a semiconductor material or alternatively made of metal. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chen’s method as modified by Hiroki based on the teachings of Ludowise – such that Chen’s material is a semiconductor material – because [t]he selection of a known material based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Claim(s) 35 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Hiroki as applied to claim 34 above, and further in view of Leirer et al. (US20210265317A1).
Regarding claim 35, Chen as modified by Hiroki teaches the method of Claim 34, but Chen does not teach further comprising filling the through via opening (152) and the via opening (170) with a semiconductor material to form the second through via structure and the conductive via.
Chen does not teach the material filling the through via opening and the via opening is a semiconductor. However, Chen teaches in paragraph [0029] the material may be a metal.
In an analogous art, Leirer teaches in paragraph [0232] that a material of vias may be metal or a semiconductor. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chen’s method as modified by Hiroki based on the teachings of Leirer – such that the material filling the through via opening and the via opening is a semiconductor – because [t]he selection of a known material based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07. Moreover, a person of ordinary skill has good reason to pursue the known options within his or her technical grasp. MPEP §2143((I)(E). Furthermore, all the claimed elements (e.g., through via opening, via opening, semiconductor) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Leirer) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/D.W.W./Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891
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