DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicants’ submission filed on 11 November 2025 has been entered.
Response to Amendment
The Office acknowledges receipt on 11 November 2025 of Applicants’ amendments in which claims 16, 21, 29, 30, and 35 are amended.
Response to Arguments
Applicants’ arguments filed 11 November 2025 have been fully considered but they are not persuasive.
Applicants argue in the fifth paragraph of page 1 through the second paragraph of page 2 that Chen and Hiroki do not teach the newly-recited subject matter in claim 1 (and similarly recited in independent claim 21) of “removing a portion of the second substrate and a portion of the interconnection structure after the forming of the light-emitting element.” Claims 1 and 21 are rejected over the combined teachings of Chen Hiroki and Tonkikh. As interpreted by the Office in view of the 35 USC 112(a) and 112(b) rejections, claim 1 (and claim 21 similarly) recites in relevant part “removing a portion of the second substrate and a portion of the sacrificial dielectric layer after the forming of the light-emitting layer.” Obviousness can be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so. MPEP §2143.01. As this principle applies to the present circumstance, Chen teaches removing a portion of a second substrate (110 of 610) {Fig. 1J; ¶0034}. Chen further teaches in Fig. 1K and paragraph [0034] forming a dielectric layer (190) on the surface of a substrate (110) previously exposed by a thinning operation (illustrated in Fig 1J). In an analogous art, Tonkikh teaches in Fig. 3C and paragraph [0063] removing a portion of a dielectric layer (250) so that its exposed surface is coplanar with an exposed surface of a conductive contact (190) penetrating the dielectric layer (250). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chen’s method as modified by Hiroki based on the teachings of Tonkikh – for removing a portion of a sacrificial dielectric layer – so that an electrical via passing through both the substrate and the dielectric layer may electrically interconnect conductors on opposing sides of the stacked substrate and dielectric layers. Chen Fig. 6; ¶0046; Tonkikh Fig. 2; ¶0063. Still further, Chen teaches in Figs. 1I and 1J and paragraph [0034] a need to remove intervening material (e.g., a substrate) to gain access to a through-hole conductor for subsequent interconnection. There are a finite number of known alternatives (e.g., two) for the sequence of forming a light-emitting layer with respect to removing portions of intervening material (e.g., a substrate and sacrificial dielectric layer) to gain access to a through-hole conductor, and the instant application identifies no specific benefit derived from the claimed sequence. A person of ordinary skill in the art could pursue each of the known alternatives with a reasonable expectation of success. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chen’s method as modified by Hiroki and Tonkikh – to remove the portions of the second substrate and sacrificial dielectric layer after forming the light-emitting layer – because a person of ordinary skill has good reason to pursue the known options within his or her technical grasp. MPEP ¶2143((I)(E).
Applicants argue in the sixth through ninth paragraphs of page 2 that Chen and Hiroki do not teach the newly-recited subject matter in independent claim 30 of “removing the second substrate and a portion of the interconnection structure to expose an end of the second through via structure.” Claim 30 is rejected over the combined teachings of Chen Hiroki and Tonkikh. As interpreted by the Office in view of the 35 USC 112(a) and 112(b) rejections, claim 30 recites in relevant part “removing the second substrate and a portion of a sacrificial layer to expose an end of the second through via structure.” Obviousness can be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so. MPEP §2143.01. As this principle applies to the present circumstance, Chen teaches removing the second substrate (110 of 610) to expose an end of the second through via structure (154 of 610) {Fig. 1J; ¶0034}. Chen further teaches in Fig. 1K and paragraph [0034] a forming a dielectric layer (190) on the surface of the substrate (110) previously exposed by a thinning operation (illustrated in Fig 1J). Tonkikh teaches in Fig. 3C and paragraph [0063] removing a portion of a dielectric layer (250) so that its exposed surface is coplanar with an exposed surface of a conductive contact (190) penetrating the dielectric layer (250). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chen’s method as modified by Hiroki based on the teachings of Tonkikh – for removing a portion of a sacrificial layer – so that an electrical via passing through both the substrate and the dielectric layer may electrically interconnect conductors on opposing sides of the stacked substrate and dielectric layers. Chen Fig. 6; ¶0046; Tonkikh Fig. 2; ¶0063.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the following features must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Claim 16, line 10, recites “removing … a portion of the interconnection structure,” which is not illustrated by the drawings. Applicants cite Figs. 17 and 18 for illustrating this subject matter {see fifth paragraph of page 1 of Applicants’ Arguments}. However, Figs. 17 and 18 do not illustrate removing a portion of an interconnection structure (e.g., 120’).
Claim 21, line 12, recites “removing … a portion of the interconnection structure,” which is not illustrated by the drawings. Applicants cite Figs. 17 and 18 for illustrating this subject matter {see fifth paragraph of page 1 of Applicants’ Arguments}. However, Figs. 17 and 18 do not illustrate removing a portion of an interconnection structure (e.g., 120’).
Claim 29, lines 1-2, recites “removing … the portion of the interconnection structure,” which is not illustrated by the drawings. Applicants cite Figs. 17 and 18 for illustrating this subject matter {see fifth paragraph of page 1 of Applicants’ Arguments}. However, Figs. 17 and 18 do not illustrate removing a portion of an interconnection structure (e.g., 120’).
Claim 30, line 10, recites “removing … a portion of the interconnection structure,” which is not illustrated by the drawings. Applicants cite Figs. 17 and 18 for illustrating this subject matter {see fifth paragraph of page 1 of Applicants’ Arguments}. However, Figs. 17 and 18 do not illustrate removing a portion of an interconnection structure (e.g., 120’).
Claim 30, lines 10-11, recites “removing the second substrate … to expose an end of the second through via structure,” which is not illustrated by the drawings. Applicants cite Figs. 17 and 18 for illustrating this subject matter {see fifth paragraph of page 1 of Applicants’ Arguments}. However, Fig. 17 illustrates the end of the via structure (e.g., 144) is entirely covered by an inter-layer dielectric layer (122-1/126) and cannot be exposed solely by the removal of the substrate (e.g., 170).
Claim 30, lines 10-13, recites “removing the second substrate and a portion of the interconnection structure to expose an end of the second through via structure; [and] bonding the second substrate to the first substrate, wherein the second through via structure is electrically connected to the first through via structure,” which is not illustrated by the drawings. Applicants cite Fig. 18 and paragraph [0056] for disclosing this subject matter {see sixth paragraph of page 2 of Applicants’ Arguments}. However, Applicants’: (1) paragraph [0056] discloses the second substrate is removed (e.g., eliminated/destroyed) by a grinding process, chemical process, or both and (2) original application provides no disclosure of bonding a first substrate to the second substrate after the second substrate is removed (e.g., eliminated/destroyed). Moreover, the original application (e.g., drawings) does not disclose a second via structure within the second substrate for electrical connection with a first via structure within the first substrate.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 16-35 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 16, line 10, recites “removing … a portion of the interconnection structure,” which is new matter because the original application does not provide adequate support for this feature. Applicants cite Figs. 17 and 18 and paragraphs [0055] and [0056] of the specification for disclosing this subject matter {see fifth paragraph of page 1 of Applicants’ Arguments}. However, Applicants’ paragraph [0056] discloses a “thinning operation is performed to expose an end (e.g., a surface 125 b) of the conductive via 124 a-1 through the interconnection structure 120′. The thinning operation is applied to reduce the thickness of the substrate 170 and the sacrificial dielectric layer 126. In some embodiments, both the substrate 170 and the sacrificial dielectric layer 126 are removed after the thinning operation.” The specification does not disclose removing a portion of the interconnection structure (e.g., 120’).
Claim 21, line 12, recites “removing … a portion of the interconnection structure,” which is new matter because the original application does not provide adequate support for this feature. Applicants cite Figs. 17 and 18 and paragraphs [0055] and [0056] of the specification for disclosing this subject matter {see fifth paragraph of page 1 of Applicants’ Arguments}. However, Applicants’ paragraph [0056] discloses a “thinning operation is performed to expose an end (e.g., a surface 125 b) of the conductive via 124 a-1 through the interconnection structure 120′. The thinning operation is applied to reduce the thickness of the substrate 170 and the sacrificial dielectric layer 126. In some embodiments, both the substrate 170 and the sacrificial dielectric layer 126 are removed after the thinning operation.” The specification does not disclose removing a portion of the interconnection structure (e.g., 120’).
Claim 29, lines 1-2, recites “removing … the portion of the interconnection structure,” which is new matter because the original application does not provide adequate support for this feature. Applicants cite Figs. 17 and 18 and paragraphs [0055] and [0056] of the specification for disclosing this subject matter {see fifth paragraph of page 1 of Applicants’ Arguments}. However, Applicants’ paragraph [0056] discloses a “thinning operation is performed to expose an end (e.g., a surface 125 b) of the conductive via 124 a-1 through the interconnection structure 120′. The thinning operation is applied to reduce the thickness of the substrate 170 and the sacrificial dielectric layer 126. In some embodiments, both the substrate 170 and the sacrificial dielectric layer 126 are removed after the thinning operation.” The specification does not disclose removing a portion of the interconnection structure (e.g., 120’).
Claim 30, line 10, recites “removing … a portion of the interconnection structure,” which is new matter because the original application does not provide adequate support for this feature. Applicants cite Figs. 17 and 18 and paragraphs [0055] and [0056] of the specification for disclosing this subject matter {see fifth paragraph of page 1 of Applicants’ Arguments}. However, Applicants’ paragraph [0056] discloses a “thinning operation is performed to expose an end (e.g., a surface 125 b) of the conductive via 124 a-1 through the interconnection structure 120′. The thinning operation is applied to reduce the thickness of the substrate 170 and the sacrificial dielectric layer 126. In some embodiments, both the substrate 170 and the sacrificial dielectric layer 126 are removed after the thinning operation.” The specification does not disclose removing a portion of the interconnection structure (e.g., 120’).
Claim 30, lines 10-11, recites “removing the second substrate … to expose an end of the second through via structure,” which is new matter because the original application does not provide adequate support for this feature. Applicants cite Figs. 17 and 18 and paragraphs [0055] and [0056] of the specification for disclosing this subject matter {see fifth paragraph of page 1 of Applicants’ Arguments}. However, Fig. 17 illustrates the end of the via structure (e.g., 144) is entirely covered by an inter-layer dielectric layer (122-1/126) and cannot be exposed solely by the removal of the substrate (e.g., 170).
Claim 30, lines 10-13, recites “removing the second substrate and a portion of the interconnection structure to expose an end of the second through via structure; [and] bonding the second substrate to the first substrate, wherein the second through via structure is electrically connected to the first through via structure,” which is new matter because the original application does not provide adequate support for this feature. Applicants cite Fig. 18 and paragraph [0056] for disclosing this subject matter {see sixth paragraph of page 2 of Applicants’ Arguments}. However, Applicants’: (1) paragraph [0056] discloses the second substrate is removed (e.g., eliminated/destroyed) by a grinding process, chemical process, or both and (2) original application provides no disclosure of bonding a first substrate to the second substrate after the second substrate is removed (e.g., eliminated/destroyed). Moreover, the original application does not disclose a second via structure within the second substrate for electrical connection with a first via structure within the first substrate.
Claims 17-20 are rejected due to their dependence from base claim 12, claims 22-29 are rejected due to their dependence from base claim 21, and claims 31-35 are rejected due to their dependence from base claim 30.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 16-35 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 16, line 10, recites “removing … a portion of the interconnection structure,” which is indefinite for the reason identified in the corresponding section 112(a) new matter rejection. Applicants cite Figs. 17 and 18 and paragraphs [0055] and [0056] of the specification for disclosing this subject matter {see fifth paragraph of page 1 of Applicants’ Arguments}. However, Applicants’ paragraph [0056] discloses a “thinning operation is performed to expose an end (e.g., a surface 125 b) of the conductive via 124 a-1 through the interconnection structure 120′. The thinning operation is applied to reduce the thickness of the substrate 170 and the sacrificial dielectric layer 126. In some embodiments, both the substrate 170 and the sacrificial dielectric layer 126 are removed after the thinning operation.” For the purpose of compact prosecution and to comport with the drawings and the disclosure in paragraph [0056], the claim will be interpreted to recite “removing … a portion of a sacrificial dielectric layer.”
Claim 21, line 12, recites “removing … a portion of the interconnection structure,” which is indefinite for the reason identified in the corresponding section 112(a) new matter rejection. Applicants cite Figs. 17 and 18 and paragraphs [0055] and [0056] of the specification for disclosing this subject matter {see fifth paragraph of page 1 of Applicants’ Arguments}. However, Applicants’ paragraph [0056] discloses a “thinning operation is performed to expose an end (e.g., a surface 125 b) of the conductive via 124 a-1 through the interconnection structure 120′. The thinning operation is applied to reduce the thickness of the substrate 170 and the sacrificial dielectric layer 126. In some embodiments, both the substrate 170 and the sacrificial dielectric layer 126 are removed after the thinning operation.” For the purpose of compact prosecution and to comport with the drawings and the disclosure in paragraph [0056], the claim will be interpreted to recite “removing … a portion of a sacrificial dielectric layer.”
Claim 29, lines 1-2, recites “removing … the portion of the interconnection structure,” which is indefinite for the reason identified in the corresponding section 112(a) new matter rejection. Applicants cite Figs. 17 and 18 and paragraphs [0055] and [0056] of the specification for disclosing this subject matter {see fifth paragraph of page 1 of Applicants’ Arguments}. However, Applicants’ paragraph [0056] discloses a “thinning operation is performed to expose an end (e.g., a surface 125 b) of the conductive via 124 a-1 through the interconnection structure 120′. The thinning operation is applied to reduce the thickness of the substrate 170 and the sacrificial dielectric layer 126. In some embodiments, both the substrate 170 and the sacrificial dielectric layer 126 are removed after the thinning operation.” For the purpose of compact prosecution and to comport with the drawings and the disclosure in paragraph [0056], the claim will be interpreted to recite “removing … the portion of the sacrificial dielectric layer.”
Claim 30, line 10, recites “removing … a portion of the interconnection structure,” which is indefinite for the reason identified in the corresponding section 112(a) new matter rejection. Applicants cite Figs. 17 and 18 and paragraphs [0055] and [0056] of the specification for disclosing this subject matter {see fifth paragraph of page 1 of Applicants’ Arguments}. However, Applicants’ paragraph [0056] discloses a “thinning operation is performed to expose an end (e.g., a surface 125 b) of the conductive via 124 a-1 through the interconnection structure 120′. The thinning operation is applied to reduce the thickness of the substrate 170 and the sacrificial dielectric layer 126. In some embodiments, both the substrate 170 and the sacrificial dielectric layer 126 are removed after the thinning operation.” For the purpose of compact prosecution and to comport with the drawings and the disclosure in paragraph [0056], the claim will be interpreted to recite “removing … a portion of a sacrificial layer.”
Claim 30, lines 10-13, recites “removing the second substrate and a portion of the interconnection structure to expose an end of the second through via structure; [and] bonding the second substrate to the first substrate, wherein the second through via structure is electrically connected to the first through via structure,” which is indefinite for the reason identified in the corresponding section 112(a) new matter rejection. Applicants cite Fig. 18 and paragraph [0056] for disclosing this subject matter {see sixth paragraph of page 2 of Applicants’ Arguments}. However, Applicants’: (1) paragraph [0056] discloses the second substrate is removed (e.g., eliminated/destroyed) by a grinding process, chemical process, or both and (2) original application provides no disclosure of bonding a first substrate to the second substrate after the second substrate is removed (e.g., eliminated/destroyed). Applicants’ Fig. 19 and paragraph [0057] disclose an interconnection structure (120/120’) is bonded to a first substrate (110). Accordingly, for the purpose of compact prosecution and to better comport with the drawings, the specification and dependent claims 34 and 35, this claim will be interpreted to recite “removing the second substrate and a portion of a sacrificial layer to expose an end of the second through via structure; [and] bonding the interconnection structure to the first substrate, wherein the second through via structure is electrically connected to the first through via structure.”
Claim 34, line 1, recites “a sacrificial layer,” which is indefinite due to the interpretation of base claim 30 identified in the two preceding paragraphs. Accordingly, for the purpose of compact prosecution and to comport with the interpretation of base claim 30, claim 34 is interpreted to recite “the sacrificial layer.”
Claims 17-20 are rejected due to their dependence from base claim 12, claims 22-29 are rejected due to their dependence from base claim 21, and claims 31-35 are rejected due to their dependence from base claim 30.
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claim 35 is rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends.
Claim 35 is identical to the Office’s interpretation of base claim 30 due to the section 112(b) rejection of claim 30.
Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 16-25 and 27-35 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US20210375721A1) in view of Hiroki et al. (US20120206031A1) and Tonkikh et al. (US20240021753A1).
Regarding claim 16, as interpreted in view of the indefiniteness rejection, Chen teaches in Figs. 5A and 6 a method for forming a light-emitting package, comprising:
providing a first substrate (110 of 610”) having a device layer (active/passive devices of 610”) and a dielectric layer (layer of 150 & 160 of 610”) disposed thereon {¶0030; insulating layer 160 is formed of a material same as from that of insulating layer 150; ¶0047, the semiconductor device 610″ can be one of the semiconductor devices 100, 200, 300, 400, or 500; ¶0018, Active and/or passive devices, such as transistors, diodes, capacitors, resistors, etc., may be formed in and/or on the semiconductor substrate 110};
forming a first through via structure (154 of 610”) penetrating through the dielectric layer (layer of 150 & 160 of 610”), the device layer (active/passive devices of 610”) and a portion of the first substrate (110 of 610”) {Fig. 1H; ¶0032}, wherein a first surface (upper surface) of the first through via structure (154 of 610”) is aligned with a top surface of the dielectric layer (layer of 150 & 160 of 610”) {Fig. 5A};
providing a second substrate (110 of 610) having an interconnection structure (114 of 610) disposed thereon {Fig. 5A; ¶0020, interconnection structure 114; ¶0045, each of the semiconductor devices 610 and 610′ may be the semiconductor device 100, 200, 300, 400, or 500};
forming a second through via structure (154 of 610) penetrating through the interconnection structure (114 of 610) {Fig. 1E; ¶0029};
removing a portion of the second substrate (110 of 610) {Fig. 1J; ¶0034}; and
bonding the interconnection structure (114 of 610) to the dielectric layer (layer of 150 & 160 of 610”) {indirectly}, wherein the second through via structure (154 of 610) is electrically connected to the first through via structure (154 of 610”) {Fig. 6; ¶0046}.
Chen does not teach forming a light-emitting element over the interconnection structure and contacting the second through via structure.
In an analogous art, Hiroki teaches forming a light-emitting element over an interconnection structure and contacting a second through via structure {see annotated copy of Hiroki’s Fig. 3 below}. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chen’s method based on the teachings of Hiroki – for forming a light-emitting element over the interconnection structure and contacting the second through via structure – so heat generated by the EL element can be effectively transferred to the rear surface metal layer through the second via structure, which has a low thermal resistance. Hiroki ¶0065.
Chen and Hiroki do not expressly teach removing a portion of a sacrificial dielectric layer.
However, Chen teaches in Fig. 1K and paragraph [0034] forming a dielectric layer (190) on the surface of the substrate (110) previously exposed by a thinning operation (illustrated in Fig 1J). In an analogous art, Tonkikh teaches in Fig. 3C and paragraph [0063] removing a portion of a dielectric layer (250) so that its exposed surface is coplanar with an exposed surface of a conductive contact (190) penetrating the dielectric layer (250). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chen’s method as modified by Hiroki based on the teachings of Tonkikh – for removing a portion of a sacrificial dielectric layer – so that an electrical via passing through both the substrate and the dielectric layer may electrically interconnect conductors on opposing sides of the stacked substrate and dielectric layers. Chen Fig. 6; ¶0046; Tonkikh Fig. 2; ¶0063.
Chen, Hiroki, and Tonkikh do not expressly teach the portions of the second substrate and sacrificial dielectric layer are removed after forming the light-emitting layer.
However, Chen teaches in Figs. 1I and 1J and paragraph [0034] a need to remove intervening material (e.g., a substrate) to gain access to a through-hole conductor for subsequent interconnection. There are a finite number of known alternatives (e.g., two) for the sequence of forming the light-emitting layer with respect to removing portions of intervening material (e.g., a substrate and sacrificial dielectric layer) to gain access to a through-hole conductor, and the instant application identifies no specific benefit derived from the claimed sequence. A person of ordinary skill in the art could pursue each of the known alternatives with a reasonable expectation of success. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chen’s method as modified by Hiroki and Tonkikh – to remove the portions of the second substrate and sacrificial dielectric layer after forming the light-emitting layer – because a person of ordinary skill has good reason to pursue the known options within his or her technical grasp. MPEP ¶2143((I)(E).
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Regarding claim 17, Chen as modified by Hiroki and Tonkikh teaches the method of claim 16, but Chen does not teach wherein the second through via structure is electrically connected to the light-emitting element.
Hiroki teaches in paragraphs [0065] and [0067] the second through via structure is electrically connected to the light-emitting element {see annotated copy of Hiroki’s Fig. 3 above}. The motivation for this modification is identified with respect to base claim 16.
Regarding claim 18, Chen as modified by Hiroki and Tonkikh teaches the method of claim 16, and Chen further teaches further comprising: performing a first thinning operation to reduce a thickness of the first substrate (110 of 610”) and to expose a second surface (bottom surface) of the first through via structure (154 of 610”) {Fig. 1J; ¶0034}.
Regarding claim 19, Chen as modified by Hiroki and Tonkikh teaches the method of claim 18, and Chen further teaches further comprising: forming a conductive pad (182 between 610’ and 610”) over the second surface (bottom surface) of the first through via structure (154 of 610”), wherein the conductive pad (182 between 610’ and 610”) is configured (made of conductive metal, ¶0033) to receive an input voltage {Fig. 6; ¶0046}.
Examiner’s Note: alternatively or supplementary, the recitation of “receive an input voltage” constitutes a manner of operating the claimed structure (e.g., a description of what is done to the light-emitting package created by the claimed method), rather than functional language (i.e., a description of what the light-emitting package – created by the claimed method – does), and does not further limit/define the claimed method. See MPEP §2114(II).
Regarding claim 20, Chen as modified by Hiroki and Tonkikh teaches the method of claim 16, and Chen further teaches further comprising: performing a second thinning operation to expose an end of the second through via structure (154 of 610) through the interconnection structure (114 of 610) {Fig. 1J; ¶0034}.
Regarding claim 21, as interpreted in view of the indefiniteness rejection, Chen teaches in Figs. 5A and 6 a method for forming a light-emitting package, comprising:
providing a first substrate (110 of 610”) having a device layer (active/passive devices of 610”) and a first dielectric layer (114a of 610”) disposed thereon {¶0047, the semiconductor device 610″ can be one of the semiconductor devices 100, 200, 300,400, or 500; ¶0018, Active and/or passive devices, such as transistors, diodes, capacitors, resistors, etc., may be formed in and/or on the semiconductor substrate 110; ¶0020, dielectric layers 114 a};
forming a first through via structure (154 of 610”) penetrating through the first dielectric layer (114a of 610”), the device layer (active/passive devices of 610”) and a portion of the first substrate (110 of 610”) {Fig. 1E; ¶0029};
providing a second substrate (110 of 610) having an interconnection structure (114, 120, 150 of 610) disposed thereon {Fig. 5A; ¶0020};
forming an optical isolation (160 of 610) over the interconnection structure (114, 120, 150 of 610) {Fig. 5A; ¶0030};
forming a second through via structure (154 of 610) penetrating through the interconnection structure (114, 120, 150 of 610), wherein a top surface of the second through via structure (154 of 610) is aligned with a top surface of the optical isolation (160 of 610) {Fig. 1H; ¶0032};
removing a portion of the second substrate (110 of 610) {Fig. 1J; ¶0034}; and
bonding the interconnection structure (114, 120, 150 of 610) to the first dielectric layer (114a of 610”) {indirectly}, wherein the second through via structure (154 of 610) is electrically connected to the first through via structure (154 of 610”) {Fig. 6; ¶0046}.
Chen does not teach forming a light-emitting element over the optical isolation and contacting the second through via structure.
Hiroki teaches forming a light-emitting element over the optical isolation (301) and contacting the second through via structure {see annotated copy of Hiroki’s Fig. 3 below}. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chen’s method based on the teachings of Hiroki – for forming a light-emitting element over the optical isolation and contacting the second through via structure – so heat generated by the EL element can be effectively transferred to the rear surface metal layer through the second via structure, which has a low thermal resistance. Hiroki ¶0065. Additionally, the optical isolation provides separation and insulation between the two electrodes of the light-emitting element.
Chen and Hiroki do not expressly teach removing a portion of a sacrificial dielectric layer.
However, Chen teaches in Fig. 1K and paragraph [0034] forming a dielectric layer (190) on the surface of the substrate (110) previously exposed by a thinning operation (illustrated in Fig 1J). Tonkikh teaches in Fig. 3C and paragraph [0063] removing a portion of a dielectric layer (250) so that its exposed surface is coplanar with an exposed surface of a conductive contact (190) penetrating the dielectric layer (250). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chen’s method as modified by Hiroki based on the teachings of Tonkikh – for removing a portion of a sacrificial dielectric layer – so that an electrical via passing through both the substrate and the dielectric layer may electrically interconnect conductors on opposing sides of the stacked substrate and dielectric layers. Chen Fig. 6; ¶0046; Tonkikh Fig. 2; ¶0063.
Chen, Hiroki, and Tonkikh do not expressly teach the portions of the second substrate and sacrificial dielectric layer are removed after forming the light-emitting layer.
However, Chen teaches in Figs. 1I and 1J and paragraph [0034] a need to remove intervening material (e.g., a substrate) to gain access to a through-hole conductor for subsequent interconnection. There are a finite number of known alternatives (e.g., two) for the sequence of forming the light-emitting layer with respect to removing portions of intervening material (e.g., a substrate and sacrificial dielectric layer) to gain access to a through-hole conductor and, the instant application identifies no specific benefit derived from the claimed sequence. A person of ordinary skill in the art could pursue each of the known alternatives with a reasonable expectation of success. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chen’s method as modified by Hiroki and Tonkikh – to remove the portions of the second substrate and sacrificial dielectric layer after forming the light-emitting layer – because a person of ordinary skill has good reason to pursue the known options within his or her technical grasp. MPEP ¶2143((I)(E).
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Regarding claim 22, Chen as modified by Hiroki and Tonkikh teaches the method of Claim 21, and Chen further teaches wherein the forming of optical isolation (160 of 610) over the interconnect structure (114 of 610) further comprises:
forming a second dielectric layer (layer containing 150, 154, 174 of 610) over the interconnection structure (114, 120, 150 of 610) {Fig. 5A; ¶0027; ¶0030, insulating layer 160 is formed of a material same as from that of insulating layer 150};
forming the optical isolation (160 of 610) in the second dielectric layer (layer containing 150, 154, 174 of 610) {Fig. 5A; ¶0030}.
Regarding claim 23, Chen as modified by Hiroki and Tonkikh teaches the method of Claim 22, and Chen further teaches further comprising:
forming a via opening (170/152) in the second dielectric layer (layer containing 150, 154, 174 of 610) {Figs. 1D, 1G; ¶0028, 0031}; and
forming a through via opening (152/170) in the second dielectric layer (layer containing 150, 154, 174 of 610) and the interconnection structure (114, 120, 150 of 610) {Figs. 1D, 1G; ¶0028, 0031}.
Regarding claim 24, Chen as modified by Hiroki and Tonkikh teaches the method of Claim 23, and Chen further teaches wherein the forming of the via opening (152) is prior to the forming of the through via opening (170) {Figs. 1D, 1G; ¶0028, 0031}.
Regarding claim 25, Chen as modified by Hiroki and Tonkikh teaches the method of Claim 23, and Chen further teaches wherein the forming of the through via opening (152) is prior to the forming of the via opening (170) {Figs. 1D, 1G; ¶0028, 0031}.
Regarding claim 27, Chen as modified by Hiroki and Tonkikh teaches the method of Claim 21, and Chen further teaches further comprising: performing a first thinning operation to reduce a thickness of the first substrate (110 of 610”) and to expose an end of the first through via structure (154 of 610”) {Fig. 1J; ¶0034}.
Regarding claim 28, Chen as modified by Hiroki and Tonkikh teaches the method of Claim 27, and Chen further teaches further comprising forming a conductive pad (182 between 610’ and 610”) over the end of the first through via structure (154 of 610”) {Fig. 6; ¶0046}.
Regarding claim 29, as interpreted in view of the indefiniteness rejection, Chen as modified by Hiroki and Tonkikh teaches the method of Claim 21, and Chen further teaches wherein the removing of the portion of the second substrate and the portion of the sacrificial dielectric layer comprises: performing a second thinning operation to expose an end of the second through via structure (154 of 610) through the interconnection structure (114, 120, 150 of 610) {Fig. 1J; ¶0034}.
Regarding claim 30, as interpreted in view of the indefiniteness rejection, Chen teaches in Figs. 5A and 6 a method for forming a light-emitting package, comprising:
providing a first substrate (110 of 610”) having a first through via structure (154 of 610”) {¶0047, the semiconductor device 610″ can be one of the semiconductor devices 100, 200, 300,400, or 500; Fig. 1E; ¶0029};
providing a second substrate (110 of 610) having an interconnection structure (114, 120, 150 of 610) disposed thereon {Fig. 5A; ¶0020;
forming an optical isolation (160 of 610) over the interconnection structure (114, 120, 150 of 610) {Fig. 5A; ¶0030};
forming a second through via structure (154 of 610) penetrating through the interconnection structure (114, 120, 150 of 610) and forming a conductive via (172 of 610) coupled to the interconnection structure (114, 120, 150 of 610) {Figs. 1E, 1H; ¶0029, 0032}, wherein a top surface of the conductive via (172 of 610) is aligned with a top surface of the optical isolation (160 of 610) {Fig. 1H};
removing the second substrate (110 of 610) to expose an end of the second through via structure (154 of 610) {Fig. 1J; ¶0034};
bonding the interconnection structure (114, 120, 150 of 610) to the first substrate (110 of 610”), wherein the second through via structure (154/172 of 610) is electrically connected to the first through via structure (154/172 of 610”) {Fig. 6; ¶0046}.
Chen does not teach forming a light-emitting element over the optical isolation, and contacting the second through via structure and the conductive via.
Hiroki teaches forming a light-emitting element over an optical isolation (301) and contacting a second through via structure and a conductive via {see annotated copy of Hiroki’s Fig. 3 below}. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chen’s method based on the teachings of Hiroki – for forming a light-emitting element over the optical isolation, and contacting the second through via structure and the conductive via – so heat generated by the EL element can be effectively transferred to the rear surface metal layer through the second via structure, which has a low thermal resistance. Hiroki ¶0065. Additionally, the optical isolation provides separation and insulation between the two electrodes of the light-emitting element. Furthermore, the conductive supports distributing current more uniformly across the anode electrode of the light-emitting element.
Chen and Hiroki do not expressly teach removing a portion of a sacrificial layer.
However, Chen teaches in Fig. 1K and paragraph [0034] forming a dielectric layer (190) on the surface of the substrate (110) previously exposed by a thinning operation (illustrated in Fig 1J). Tonkikh teaches in Fig. 3C and paragraph [0063] removing a portion of a dielectric layer (250) so that its exposed surface is coplanar with an exposed surface of a conductive contact (190) penetrating the dielectric layer (250). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chen’s method as modified by Hiroki based on the teachings of Tonkikh – for removing a portion of a sacrificial layer – so that an electrical via passing through both the substrate and the dielectric layer may electrically interconnect conductors on opposing sides of the stacked substrate and dielectric layers. Chen Fig. 6; ¶0046; Tonkikh Fig. 2; ¶0063.
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Regarding claim 31, Chen as modified by Hiroki and Tonkikh teaches the method of Claim 30, but Chen does not teach wherein the interconnection structure is electrically connected to the light-emitting element through the conductive via.
Hiroki teaches in paragraphs [0065] and [0067] the interconnection structure is electrically connected to the light-emitting element through the conductive via {see annotated copy of Hiroki’s Fig. 3 above}. The motivation for this modification is identified with respect to base claim 30.
Regarding claim 32, Chen as modified by Hiroki and Tonkikh teaches the method of Claim 30, and Chen further teaches further removing a portion of the first substrate (110 of 610”) to expose an end of the first through via structure (154 of 610”) {Fig. 1J; ¶0034}.
Regarding claim 33, Chen as modified by Hiroki and Tonkikh teaches the method of Claim 32, and Chen further teaches further comprising forming a conductive pad (182 between 610’ and 610”) over the end of the first through via structure (154 of 610”) {Fig. 6; ¶0046}.
Regarding claim 34, as interpreted in view of the indefiniteness rejection, Chen as modified by Hiroki and Tonkikh teaches the method of Claim 30, and Chen further teaches further comprising the sacrificial layer (114a of 610) disposed between the second substrate (110 of 610) and the interconnection structure (114, 120, 150 of 610) {Fig. 5A; ¶0020}.
Regarding claim 35, Chen as modified by Hiroki and Tonkikh teaches the method of Claim 34, but Chen does not teach further comprising removing the sacrificial layer to expose the end of the second through via structure.
However, this subject matter does not further limit base claim 30 as claim 30 is interpreted by the Office with respect to the indefiniteness rejection applied under 35 USC §112(b). Accordingly, the mapping of this the prior art to this subject matter is addressed above with respect to claim 30.
Claim(s) 26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Hiroki and Tonkikh as applied to claim 23 above, and further in view of Ludowise (US20050274970A1).
Regarding claim 26, Chen as modified by Hiroki and Tonkikh teaches the method of Claim 23, and Chen further teaches further comprising filling the through via opening (152) and the via opening (170) with a material (metal) to form the second through via structure (154) and a conductive via (172).
Chen does not teach the material is a semiconductor material.
In an analogous art, Ludowise teaches in Fig. 1A paragraph [0015] that electrically and thermally conductive vias 118 may be made of a semiconductor material or alternatively made of metal. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chen’s method as modified by Hiroki based on the teachings of Ludowise – such that Chen’s material is a semiconductor material – because [t]he selection of a known material based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Citation of Pertinent Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Li (US20230207452A1) teaches a multi-stacking carrier structure includes an etch stop layer; a first tier comprising a first passivation layer positioned on the etch stop layer, a first insulating layer positioned on the first passivation layer, and a first via positioned along the first passivation layer and the first insulating layer; a second tier positioned on the first tier and comprising a second passivation layer positioned on the first insulating layer, a second insulating layer positioned on the second passivation layer, and a second via positioned along the second passivation layer and the second insulating layer, and electrically connected to the first via; and a third tier positioned on the second tier and comprising a third passivation layer positioned on the second insulating layer, a third insulating layer positioned on the third passivation layer, and a third via positioned along the third passivation layer and the third insulating layer.
Conclusion
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/D.W.W./Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891