DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 1/15/2026 has been entered.
Status of the Application
Acknowledgement is made of the amendment received on 1/15/2026. Claims 1-2, 7-9, 13-15, and 17-28 are pending in this application. Claims 1, 13, 17, and 20 are amended. Claims 3-6 are canceled. Claims 25-28 are new.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 20 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claims contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention.
Claim 20 has been amended to recite limitation “the second wafer is etched using a same etching mask used for etching the first edge portion of the first wafer” in lines 2-3. However, the originally filed specification does not reasonably convey to a person having ordinary skill in the art that the inventor had possession of this limitation at the time of filing.
Specifically, the specification describes forming an etching mask to perform a wafer edge trimming process on a wafer (e.g., [0035]-[0039]) and further describes removing the etching mask after the trimming process is completed (e.g., [0045]). The specification also describes, in separate embodiments, forming an etching mask after wafer bonding to perform a post-trimming process on bonded wafers (e.g., [0065]-[0066]). However, the specification does not describe or suggest using the same etching mask for etching both the first edge portion of the first wafer and the second wafer, as now recited in claim 20.
Accordingly, the originally filed specification does not demonstrate possession of using a same etching mask for both etching steps, as required by claim 20.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 20 and 26-27 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 20 has been amended to recites “the second wafer is etched using a same etching mask used for etching the first edge portion of the first wafer” in lines 2-3 and depends from claim 17. There is insufficient antecedent basis for this limitation in the claim, because claim 17 does not introduce an etching mask.
Accordingly, the recitation of “a same etching mask” in claim 20 lacks proper antecedent basis, rendering the scope of claim 20 unclear.
For best understand and examination purpose, the claim will be best considered based on drawings, disclosure, and/or any applicable prior arts; and the claim limitation “the second wafer is etched using a same etching mask used for etching the first edge portion of the first wafer” will be interpreted as “the second wafer is etched using an etching mask” in the instant Office Action.
Claim 26 recites “the curved bottom surface is overlapped by a downward curved portion” in lines 2-3 and depends from claim 25. However, the claim does not clearly identify which “downward curved portion” corresponds to the downward curved portion of the top surface of the first semiconductor substrate recited in claim 25, or to a different curved portion. As a result, the scope of claim 26 is unclear.
For best understand and examination purpose, the claim will be best considered based on drawings, disclosure, and/or any applicable prior arts; and the claim limitation “a downward curved portion” will be interpreted as “the downward curved portion of the top surface of the first semiconductor substrate” in the instant Office Action.
Claim 27 is rejected due to their dependency.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 7-8, 21-22, and 28 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2018/0138164; hereinafter ‘Lee’) in view of Liu et al. (CN 109659267A; hereinafter ‘Liu’) and in view of Christophersen et al. (US 2009/0092934; hereinafter ‘Christophersen’).
Regarding claim 1, Lee teaches a method ([0014-0015, 0019]) comprising:
forming (shown in FIG. 12) an etching mask (60, [0087]) over a first wafer (10, FIG. 8, [0064]) that comprises:
a semiconductor substrate (101, [0070]); and
a plurality of dielectric layers (108 and 208, FIGS. 2 and 4, [0051]) over the semiconductor substrate (101), wherein the etching mask (60) covers an inner portion of the first wafer (200cr of 10, FIGS. 5 and 11, [0057]);
performing (shown in FIG. 12) a wafer edge trimming process (55, [0091]) to trim an edge portion of the first wafer (200er, FIGS. 5and 11, [0088]), with the etching mask (60) protecting the inner portion of the first wafer (200cr) from being etched (only 200er is etched and removed, FIG. 10, [0074-0075]), wherein the edge portion (200er) forms a full ring (200er having a full ring, FIG. 6) encircling the inner portion (200cr), wherein:
in the wafer edge trimming process (55), the plurality of dielectric layers (108 and 208) are etched through (55 etching 108 and 208 in 200er, FIGS. 8 and 12, [0070]), and wherein a top surface portion of the semiconductor substrate (a top surface portion of 101 in 200er; hereinafter ‘101TP200er’) is etched (55 etching 101TP200er); and
after the wafer edge trimming process (55), a lower portion of the semiconductor substrate (a lower surface portion of 101 in 200er; hereinafter ‘101B200er’) directly underlying the top surface portion (101TP200er) has a top surface (a top surface of 101TP200er; hereinafter ‘101TS200er’), and the top surface (101TS200er) comprises a planar inner portion (a planar inner portion adjacent 200cr, FIG. 12);
removing (shown in FIG. 18) the etching mask (60, [0093]); and
bonding (shown in FIG. 19) the first wafer (10) to a second wafer (300, [0127]).
Lee does not teach the method wherein the first wafer is a carrier wafer that is free from active devices therein and wherein a raised portion on an outer side of the planar inner portion comprises a curved sidewall and a curved top surface joined to the curved sidewall.
Liu teaches a method (FIG. 3D, [0064]) wherein the first wafer (200 and 300; hereinafter ‘FW’) is a carrier wafer (FW is a carrier wafer) that is free from active devices therein (FW is a wafer used to support or carry chips to be packaged, [0052]).
As taught by Liu, one of ordinary skill in the art would utilize and modify the above teaching into Lee to obtain and achieve the method wherein the first wafer is a carrier wafer that is free from active devices therein as claimed, because the carrier wafer is conventionally incorporated into the packaging process, and it would have been routine to subject such wafers to edge trimming or etching processes in order to improve packaging integrity and yield [0055-0057].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Liu in combination with Lee due to above reason.
Lee in view of Liu does not teach the method wherein a raised portion on an outer side of the planar inner portion comprises a curved sidewall and a curved top surface joined to the curved sidewall.
Christophersen teaches a method (Fig. 14, [0061]) wherein a raised portion (the raised portion extending over positions of ~150-1000 µm) comprises a curved sidewall (at positions near the outer edges of the raised portion) and a curved top surface (at positions near the center of the raised portion) joined to the curved sidewall (shown in Fig. 14).
Christophersen does not explicitly teach that the raised portion is located on an outer side of a planar inner portion.
Christophersen, however, teaches that the remaining silicon thickness at different locations on the substrate is controllable through etching conditions [0035].
As taught by Christophersen, one of ordinary skill in the art would utilize and modify the above teaching into Lee in view of Liu to obtain and achieve the method wherein a raised portion on an outer side of the planar inner portion comprises a curved sidewall and a curved top surface joined to the curved sidewall as claimed, because the surface formation and location of the raised portion are controllable and selectable through spatially dependent etching conditions, thereby enabling local variation in remaining silicon thickness to achieve a desired surface topography of the substrate [0035, 0049, 0061].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Christophersen in combination with Lee in view of Liu due to above reason.
Regarding claim 7, Lee in view of Liu and Christophersen teaches the method of claim 1, wherein the wafer edge trimming process is performed before the first wafer is bonded to the second wafer (Lee: after 55, 10 is bonded to 300, FIGS. 12 and 19).
Regarding claim 8, Lee in view of Liu and Christophersen teaches the method of claim 1, wherein the wafer edge trimming process (Lee: shown in FIG. 23) is performed after the first wafer is bonded to the second wafer (55 is performed on 300 after 10 is bonded to 300, [0157]), and wherein in the wafer edge trimming process, both of the second wafer and the first wafer are trimmed (shown in FIG. 23).
Regarding claim 21, Lee in view of Liu and Christophersen teaches the method of claim 1, Lee in view of Christophersen does not teach the method wherein the carrier wafer comprises a dielectric substrate.
Liu teaches the method wherein the carrier wafer comprises a dielectric substrate (FW comprises a glass wafer, [0052]).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teaching as taught by Liu to obtain and achieve the method wherein the carrier wafer comprises a dielectric substrate as claimed, because glass wafer is a well-known material and widely used as a carrier wafer. Further, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended used a matter of obvious design choice. In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960).
Regarding claim 22, Lee in view of Liu and Christophersen teaches the method of claim 1, Lee in view of Christophersen does not teach the method wherein the carrier wafer comprises a substrate, and a bond layer over and contacting the substrate, wherein the bond layer physically joins the second wafer after the bonding.
Liu teaches the method wherein the carrier wafer comprises a substrate (FW comprises 300, FIG. 3D, [0064]), and a bond layer (200) over and contacting the substrate (shown in FIG. 3D), wherein the bond layer physically joins the second wafer after the bonding (200 physically joins 100 after bonding, FIG. 3E, [0067]).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teaching as taught by Liu to obtain and achieve the method wherein the carrier wafer comprises a substrate, and a bond layer over and contacting the substrate, wherein the bond layer physically joins the second wafer after the bonding as claimed, because the adhesive film is to enhance adhesion between the chip and the carrier, thereby increasing binding force and preventing die drift during molding [0068, 0070].
Regarding claim 28, Lee in view of Liu and Christophersen teaches the method of claim 1, Lee in view of Liu does not teach the method wherein in a top view of the first wafer, the raised portion forms a ring.
Christophersen teaches the method (Figs. 10 and 14, [0058, 0061]) wherein in a top view of the first wafer (shown in Fig. 10), the raised portion forms a ring (the raised portion evidenced by a 1D surface profile in Fig. 14 being distributed along a peripheral region of the wafer to define an annular 3D surface topology).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teaching as taught by Christophersen to obtain and achieve the method wherein in a top view of the first wafer, the raised portion forms a ring as claimed, because the surface formation and location of the raised portion are controllable and selectable through spatially dependent etching conditions, thereby enabling local variation in remaining silicon thickness to achieve a desired surface topography of the substrate [0035, 0049, 0061].
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 2018/0138164) in view of Liu (CN 109659267A) and Christophersen (US 2009/0092934), and further in view of Kuo et al. (US 2014/0024170; hereinafter ‘Kuo’).
Regarding claim 2, Lee in view of Liu and Christophersen teaches the method of claim 1, but does not teach the method, wherein the edge portion has a width smaller than about 1 mm.
Kuo teaches a method ([0004]), wherein the edge portion has a width smaller than about 1 mm (edge bevel removal width W1 is about 1mm, Figs. 3A and 3B, [0011]).
As taught by Kuo, one of ordinary skill in the art would utilize and modify the above teaching into Lee in view of Liu and Christophersen to obtain and achieve the method, wherein the edge portion has a width smaller than about 1 mm as claimed, because the described range is exemplary and subject to variation, thereby implicitly disclosing widths smaller than 1mm [0011]. Further it has been held that where the criticality of the claimed range is not shown and the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. MPEP §2144.05.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Kuo in combination with Lee in view of Liu and Christophersen due to above reason.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 2018/0138164) in view of Liu (CN 109659267A) and Christophersen (US 2009/0092934), and further in view of Lin et al. (US 2021/0305200; hereinafter ‘Lin’).
Regarding claim 9, Lee in view of Liu and Christophersen teaches the method of claim 1, but does not teach the method further comprising, before the first wafer is bonded to the second wafer, performing an additional wafer edge trimming process on the second wafer, and wherein the method further comprises, after the first wafer is bonded to the second wafer, thinning the second wafer.
Lin teaches a method ([0005]) further comprising, before the first wafer (first wafer, FIGS. 4 and 9, [0014]) is bonded to the second wafer (third wafer, FIG. 9, [0043]), performing an additional wafer edge trimming process on the second wafer (the third wafer is trimmed before bonding, [0045]), and wherein the method further comprises, after the first wafer is bonded to the second wafer, thinning the second wafer (the third wafer is thinned after bonding, [0045]).
As taught by Lin, one of ordinary skill in the art would utilize and modify the above teaching into Lee to obtain and achieve the method further comprising, before the first wafer is bonded to the second wafer, performing an additional wafer edge trimming process on the second wafer, and wherein the method further comprises, after the first wafer is bonded to the second wafer, thinning the second wafer as claimed, because performing edge trimming prior to bonding results the edge of the trimmed wafer to be laterally offset inward relative to the edge of the other wafer, thereby improving bonding uniformity and alignment accuracy [0012, 0045, 0045]. Further, thinning is performed after bonding to ensure mechanical support from the bonded wafer during the thinning process, thebe by minimizing the risk of wafer breakage, improving overall handling stability, and avoiding undesirable particle formation [0012].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Lin in combination with Lee due to above reason.
Claims 13-15 and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Huang (US 2022/0157761) in view of Kuo (US 2014/0024170) and Christophersen (US 2009/0092934).
Regarding claim 13, Huang teaches a method [0022] comprising:
applying (shown in Fig. 3) a photoresist (241, [0024]) over a first wafer (210, 220, and 230, Fig. 2, [0022]), wherein the first wafer comprises a semiconductor substrate (210) and at least one dielectric layer (231, Fig. 2, [0023]) over the semiconductor substrate;
performing a lithography process (shown in Fig. 4) to pattern the photoresist (forming 240’, [0024]), so that the photoresist covers an inner portion of the first wafer (240 is used for the edge trimming process, [0024]);
performing a first etching process (shown in Fig. 5) to etch the at least one dielectric layer in an edge portion of the first wafer, so that a first top surface of the semiconductor substrate is exposed (shown in Fig. 5); and
removing the photoresist (shown in Fig. 6, [0030]).
Huang does not teach the method comprising: wherein the first wafer has a round top-view shape, the photoresist covers a round inner portion of the first wafer, and performing a second etching process to etch the semiconductor substrate in the edge portion of the first wafer, so that the semiconductor substrate is recessed to have a second top surface lower than the first top surface, wherein the second top surface comprises a planar inner portion, and a raised portion on an outer side of the planar inner portion, and wherein the raised portion comprises a curved sidewall and a curved top surface joined to the curved sidewall.
Kuo teaches a method [0004] comprising:
wherein the first wafer has a round top-view shape (20 has a round top-view shape, Fig. 3B, [0011]),
the photoresist covers a round inner portion of the first wafer (the passivation layer 48 serves as a mask that covers a round inner portion of 20 during the edge trimming process, Fig. 5, [0015]); and
performing a second etching process (shown in Fig. 5) to etch the semiconductor substrate in the edge portion of the first wafer (removing edge portion material in EBR region 44 with 38 and the first trim process is applied to 23 of 22, [0011, 0016]), so that the semiconductor substrate is recessed to have a second top surface lower than the first top surface (22 is recessed to have the top surface of 23 lower than the top surface of 22), wherein the second top surface comprises a planar inner portion (the top surface of 23 comprises a planar portion located on an inner side of 23 and facing the top surface of 22).
As taught by Kuo, one of ordinary skill in the art would utilize and modify the above teaching into Huang to obtain and achieve the method comprising: wherein the first wafer has a round top-view shape, the photoresist covers a round inner portion of the first wafer, and performing a second etching process to etch the semiconductor substrate in the edge portion of the first wafer, so that the semiconductor substrate is recessed to have a second top surface lower than the first top surface, wherein the second top surface comprises a planar inner portion as claimed, because the round shape of wafers and the use of photoresist as a mask for the trimming process are well-known and widely adopted in the art, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended used a matter of obvious design choice. In re Leshin, 125 USPQ 416. Further, the wafer edge trimming process extends into the semiconductor substrate to remove the weak portions of the dielectric layers formed over it, which may otherwise peel or crack in subsequent process steps [0022].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Kuo in combination with Huang due to above reason.
Huang in view of Kuo does not teach the method wherein a raised portion on an outer side of the planar inner portion comprises a curved sidewall and a curved top surface joined to the curved sidewall.
Christophersen teaches a method (Fig. 14, [0061]) wherein a raised portion (the raised portion extending over positions of ~150-1000 µm) comprises a curved sidewall (at positions near the outer edges of the raised portion) and a curved top surface (at positions near the center of the raised portion) joined to the curved sidewall (shown in Fig. 14).
Christophersen does not explicitly teach that the raised portion is located on an outer side of a planar inner portion.
Christophersen, however, teaches that the remaining silicon thickness at different locations on the substrate is controllable through etching conditions [0035].
As taught by Christophersen, one of ordinary skill in the art would utilize and modify the above teaching into Huang in view of Kuo to obtain and achieve the method wherein a raised portion on an outer side of the planar inner portion comprises a curved sidewall and a curved top surface joined to the curved sidewall as claimed, because the surface formation and location of the raised portion are controllable and selectable through spatially dependent etching conditions, thereby enabling local variation in remaining silicon thickness to achieve a desired surface topography of the substrate [0035, 0049, 0061].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Christophersen in combination with Huang in view of Kuo due to above reason.
Regarding claim 14, Huang in view of Kuo and Christophersen teaches the method of claim 13, wherein the first wafer comprises a plurality of bond pads (Huang: 233, Fig. 3, [0023]) in a top dielectric layer (231, [0023]) in the at least one dielectric layer, and the photoresist covers the plurality of bond pads (241 covers 233), and wherein the edge portion of the first wafer is free from metal features therein (241a is free from 233 and 223, [0024-0025]).
Regarding claim 15, Huang in view of Kuo and Christophersen teaches the method of claim 13, further comprising bonding a second wafer to the first wafer through wafer-to-wafer bonding (Huang: bonding 310 and 330 to 210, 220, and 230, Fig. 7, [0031]).
Regarding claim 24, Huang in view of Kuo and Christophersen teaches the method of claim 13, wherein the first etching process is performed using the photoresist (Huang: 240 includes 241, [0024]).
Huang in view of Kuo and Christophersen does not explicitly teach the method wherein the second etching process are performed using the photoresist.
Huang, however, discloses that the etching process is performed using a photoresist, and the bonding process requires alignment and joining with the corresponding recess on the other wafer (Fig. 7, [0024, 0031]).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teaching as taught by Huang to obtain and achieve the method wherein the second etching process are performed using the photoresist as claimed, because applying the same etching technique to the second wafer in order to ensure proper alignment, matching recess dimensions, and reliable hybrid bonding.
Claims 17, 20, and 25-27 are rejected under 35 U.S.C. 103 as being unpatentable over Kuo (US 2014/0024170) in view of Lee (US 2018/0138164) and Seki et al. (US 5145554; hereinafter ‘Seki’).
Regarding claim 17, Kuo teaches a method ([0004]) comprising:
forming (shown in Fig. 1) a first plurality of dielectric layers (30, [0008-0009]) over a first semiconductor substrate (22, [0007]) to form a first wafer (20, [0010]);
etching (shown in Fig. 5) a first edge portion of the first wafer (44, [0016]) to etch-through the first plurality of dielectric layers (removing edge portion material in EBR region 44 with 38, [0011]) and to recess the first semiconductor substrate (shown in Fig. 5), wherein the first edge portion of the first wafer has a ring shape (44 has a ring shape, Fig. 8B, [0019]); and
bonding (shown in Fig. 6) a second wafer to the first wafer (bonding 54 to 20, [0017]).
Kuo does not teach that the etching of the first edge portion is performed through an anisotropic etching process.
Lee teaches a method of removing an edge region of a wafer or substrate using a dry etching process at a wafer level [0066-0068].
As taught by Lee, one of ordinary skill in the art would utilize and modify the above teaching into Kuo to obtain and achieve the method comprising: etching a first edge portion of the wafer through a dry etching process as claimed, because it is used at a wafer level to remove an edge or bevel region of a wafer to form a trimmed substrate [0065].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Lee in combination with Kuo due to above reason.
Kuo in view of Lee does not teach that the dry etching is an anisotropic etching process.
Seki teaches a method of dry etching that achieves anisotropic etching of a semiconductor structure (col. 1, lines 14-17).
As taught by Seki, one of ordinary skill in the art would utilize and modify the above teaching into Kuo in view of Lee to obtain and achieve the method comprising: etching a first edge portion of the wafer through an anisotropic etching process as claimed, because the anisotropic dry etching is well -known choice for providing the predictable benefit of directional etch profiles while minimizing surface or structural damage (col. 1, lines 17-23, col. 12, lines 22-26).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Seki in combination with Kuo in view of Lee due to above reason.
Regarding claim 20, Kuo in view of Lee and Seki teaches the method of claim 17, Kuo in view of Seki does not teach the method wherein the second wafer is etched after the second wafer is bonded to the first wafer, and wherein the second wafer is etched using a same etching mask used for etching the first edge portion of the first wafer.
Lee teaches the method [0085], wherein the second wafer is etched after the second wafer is bonded to the first wafer (200 is etched after bonding to 10, FIGS. 11 and 12, [0064, 0087, 0091]), and wherein the second wafer is etched using a same etching mask used for etching the first edge portion of the first wafer (200 is etched using 60, [0087]; see the 112 rejection above).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Lee to obtain and achieve the method wherein the second wafer is etched after the second wafer is bonded to the first wafer, and wherein the second wafer is etched using a same etching mask used for etching the first edge portion of the first wafer as claimed, because performing the edge trimming after bonding the first and second wafer avoids mechanical stress and contamination issues, and also enables the formation of stacked chip dies without requiring an additional lamination process [0078, 0080]. Further, using an etching mask enables selectively exposing the edge region of the wafer, thereby improving process controllability and preventing unintended etching of the wafer interior [0092].
Regarding claim 25, Kuo in view of Lee and Seki teaches the method of claim 17, wherein after the first edge portion of the first wafer is etched, a top surface of the first semiconductor substrate comprises a planar inner portion (Kuo: a top surface of 22 includes a planar inner portion, Fig. 5).
Kuo in view of Seki does not teach the method, wherein after the first edge portion of the first wafer is etched, a top surface of the first semiconductor substrate comprises a downward curved portion on an outer side of the planar inner portion.
Lee teaches the method (FIG. 8), wherein after the first edge portion of the first wafer is etched, a top surface of the first semiconductor substrate comprises a downward curved portion on an outer side of the planar inner portion (etching process 50 etched an edge region of 101 adjacent to the planar inner portion, thereby forming a downward curved portion on the outer side of the planar inner portion, [0070]).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Lee to obtain and achieve the method, wherein after the first edge portion of the first wafer is etched, a top surface of the first semiconductor substrate comprises a downward curved portion on an outer side of the planar inner portion as claimed, because the edge etching process is performed without a mask pattern, such that the etch naturally transitions from an unetched planar inner portion to a recessed edge region, inherently forming a downward curved profile [0067-0068].
Regarding claim 26, Kuo in view of Lee and Seki teaches the method of claim 25, Kuo in view of Seki does not teach the method wherein the first edge portion of the first wafer comprises a curved bottom surface of the first semiconductor substrate, and wherein the curved bottom surface is overlapped by a downward curved portion.
Lee teaches the method (FIG. 8), wherein the first edge portion of the first wafer comprises a curved bottom surface of the first semiconductor substrate (10 in 200er includes a curved 100b, [0057, 0082]) and wherein the curved bottom surface is overlapped by a downward curved portion (the curved 100b is vertically overlapped by the downward curved portion of the top surface of 101 formed in the same edge region).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Lee to obtain and achieve the method wherein the first edge portion of the first wafer comprises a curved bottom surface of the first semiconductor substrate, and wherein the curved bottom surface is overlapped by a downward curved portion as claimed, because a wafer bevel edge having a curved bottom surface is originally provided for stress distribution [0003-0004, 0057-0058], and a downward curved top surface is formed by edge etching [0070], resulting in vertical overlap of the curved surface within the same edge region.
Regarding claim 27, Kuo in view of Lee and Seki teaches the method of claim 25, Kuo in view of Seki does not teach the method wherein the downward curved portion of the top surface of the first semiconductor substrate is joined to the curved bottom surface.
Lee teaches the method (FIG. 8), wherein the downward curved portion of the top surface of the first semiconductor substrate is joined to the curved bottom surface (the downward curved portion of the top surface of 101 is continuously joined to the curved 100b in 200er, [0071]).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Lee to obtain and achieve the method wherein the downward curved portion of the top surface of the first semiconductor substrate is joined to the curved bottom surface as claimed, because the edge etching process forms a semiconductor profile at the wafer edge, such that the downward curved top surface naturally meets and joins the curved bottom surface without a discontinuity [0071].
Claims 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Kuo (US 2014/0024170) in view of Lee (US 2018/0138164) and Seki (US 5145554), and further in view of Lin (US 2021/0305200)
Regarding claim 18, Kuo in view of Lee and Seki teaches the method of claim 17 further comprising: wherein the etching the first edge portion forms a first recess (Kuo: 52, Fig. 5, [0016]) extending into the first wafer (shown in Fig. 5) and at a time after the second wafer is bonded to the first wafer (54 is bonded to 20, Fig. 6, [0017]) the first recess is joined to the second recess (52 is joined to the recess of 54).
Kuo does not explicitly teach the method further comprising the etching the second edge portion forms a second recess extending into the second wafer.
Kuo, however, recognizes that the second wafer defines a corresponding recess at its edge. While the formation mechanism of the recess in the second wafer is not expressly described, it would have been obvious to one of ordinary skill in the art to apply the same etching process disclosed for forming the first recess in the first wafer to the second wafer as well, so that the two recesses can properly align and join after bonding.
Kuo in view of Lee and Seki does not teach the method further comprising: etching a second edge portion of the second wafer to etch-through a second plurality of dielectric layers and a second semiconductor substrate in the second wafer.
Lin teaches a method ([0005]) further comprising, etching (70, FIG. 4, [0028]) a second edge portion of the second wafer (52E of the third wafer, FIG. 9, [0028]) to etch-through a second plurality of dielectric layers (154, 158, and 164, [0020-0043]) and a second semiconductor substrate (152, [0043]) in the second wafer.
As taught by Lin, one of ordinary skill in the art would utilize and modify the above teaching into Kuo in view of Lee and Seki to obtain and achieve the method further comprising: etching a second edge portion of the second wafer to etch-through a second plurality of dielectric layers and a second semiconductor substrate in the second wafer as claimed, because performing edge trimming results the edge of the trimmed wafer to be laterally offset inward relative to the edge of the other wafer, thereby improving bonding uniformity and alignment accuracy [0012, 0045, 0045].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Lin in combination with Kuo in view of Lee and Seki due to above reason.
Regarding claim 19, Kuo in view of Lee, Seki, and Lin teaches the method of claim 18, Kuo in view of Lee and Seki does not teach the method wherein the second wafer is etched before the second wafer is bonded to the first wafer, and the method further comprises thinning the second wafer to reveal a through-via in the second semiconductor substrate.
Lin teaches the method wherein the second wafer is etched before the second wafer is bonded to the first wafer (the third wafer is trimmed before bonding to the first wafer, [0045]), and the method further comprises thinning the second wafer to reveal a through-via in the second semiconductor substrate (thinning the third wafer to revel 156 in 152, FIG. 9, [0043]).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Lin to obtain and achieve the method, wherein the second wafer is etched before the second wafer is bonded to the first wafer, and the method further comprises thinning the second wafer to reveal a through-via in the second semiconductor substrate as claimed, because performing edge trimming prior to bonding results the edge of the trimmed wafer to be laterally offset inward relative to the edge of the other wafer, thereby improving bonding uniformity and alignment accuracy [0012, 0045, 0045]. Further, thinning process to reveal the via in the substrate is a well-known and routinely practiced technique in the semiconductor field.
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 2018/0138164) in view of Liu (CN 109659267A) and Christophersen (US 2009/0092934), and further in view of Bae et al. (KR 101223633B1; hereinafter ‘Bae’).
Regarding claim 23, Lee in view of Liu and Christophersen teaches the method of claim 1, but does not teach the method wherein the second wafer is a device wafer.
Bae teaches a method [0001] wherein the second wafer is a device wafer (a second wafer is a device wafer).
As taught by Bae, one of ordinary skill in the art would utilize and modify the above teaching into Lee in view of Liu and Christophersen to obtain and achieve the method wherein the second wafer is a device wafer as claimed, because in the of fabricating a 3D integrated circuit based on a chip stack, the device wafer is temporarily mounted on a carrier wafer and transferred to each processing machine for subsequent process steps, in order to enable thinning and handling during the manufacturing flow [0004, 0006, 0008].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Bae in combination with Lee in view of Liu and Christophersen due to above reason.
Response to Arguments
Applicant's arguments with respect to claims have been considered but are moot in view of the new ground of rejection. Response to arguments on newly added limitations are responded to in the above rejection.
Conclusion
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/JIYOUNG OH/Examiner, Art Unit 2818
/DUY T NGUYEN/Primary Examiner, Art Unit 2818 2/18/26