DETAILED ACTION
This Office action is in response to the amendment filed 26 June 2025. By this amendment, claims 1, 8, 13, and 15 are amended. Claims 1-20 are currently pending; claims 4-5, 11-12, and 15-20 stand withdrawn.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 26 June 2025 have been fully considered but they are not persuasive; the rejections of the claims have been modified in response to Applicant’s amendments to the claims. The amended limitations and Applicant’s arguments regarding the amended limitations are addressed by the modified rejections below.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3 and 6-7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2009/0206406 A1 to Rachmady et al. (hereinafter “Rachmady”).
Regarding independent claim 1, Rachmady (Fig. 1) discloses a structure comprising:
a gate structure comprising a gate dielectric layer 116 (¶ 0021) and a gate conductor layer 118 (¶ 0021) and having a first portion and a second portion, wherein the first portion (lower portion of 118/116) is on a semiconductor body 102/104 (¶ 0011) and the second portion (upper portion of 118/116) is on the first portion and has edge region that extends laterally beyond the first portion (Fig. 1); and
a gate sidewall spacer 112/114 (¶ 0014) having a first section 112 and a second section 114,
wherein the first section 112 and the second section 114 include continuous portions of a sidewall spacer material layer (¶ 0014, Fig. 1e - 112 includes continuous portion of a sidewall spacer material spanning across semiconductor body 102/104; 114 includes a continuous portion of a sidewall spacer material spanning across semiconductor body 102/104),
wherein the first section 112 is positioned laterally adjacent to the first portion (lower portion of 118) of the gate structure between the edge region of the second portion (upper portion of 118) of the gate structure and the semiconductor body (Fig. 1f), wherein the second section is positioned laterally adjacent to the first section and to the second portion of the gate structure, and wherein the gate sidewall spacer 112/114 is physically separated from the gate conductor layer 118 by the gate dielectric layer 116 (Fig. 1f).
Regarding claim 2, Rachmady (Fig. 1) discloses the structure of claim 1, wherein the gate dielectric layer 116 comprises at least a high-K dielectric layer (¶ 0022) and wherein the gate conductor layer 118 comprises at least a layer of any of a metal and a metal alloy (¶ 0022).
Regarding claim 3, Rachmady (Fig. 1) discloses the structure of claim 1, wherein the gate structure comprises the gate dielectric layer 116 lining a gate opening and the gate conductor layer 118 on the gate dielectric layer within the gate opening (Fig. 1f), wherein the gate dielectric layer 116 is within the first portion and the second portion (Fig. 1f), and wherein surfaces of the semiconductor body 102/104, the first section 112 of the gate sidewall spacer, and the second section 114 of the gate sidewall spacer are immediately adjacent to the gate dielectric layer 116 and separated from the gate conductor layer 118 by the gate dielectric layer 116 (Fig. 1f).
Regarding claim 6, Rachmady (Fig. 1) discloses the structure of claim 1, wherein the semiconductor body comprises a semiconductor fin 104, and wherein the gate structure 116/118 and the gate sidewall spacer 112/114 are on a top surface and adjacent opposing sides of the semiconductor fin (Fig. 1).
Regarding claim 7, Rachmady (Fig. 1) discloses the structure of claim 1, wherein the gate structure comprises a replacement metal gate (¶ 0012).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 8-10 and 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Rachmady in view of US 2020/0098759 A1 to Su et al. (hereinafter “Su”).
Regarding independent claim 8, Rachmady (Fig. 1) discloses a structure comprising:
a substrate;
a field effect transistor on the substrate and comprising:
a semiconductor fin 104 (¶ 0011);
a gate structure comprising a gate dielectric layer 116 (¶ 0021) and a gate conductor layer 118 (¶ 0021) and having a first portion and a second portion, wherein the first portion (lower portion of 118/116) is on a top surface and opposing sides of the semiconductor fin and the second portion (upper portion of 118/116) is on the first portion and has edge region that extends laterally beyond the first portion (Fig. 1f); and
a gate sidewall spacer 112/114 (¶ 0014) having a first section 112 and a second section 114,
wherein the first section 112 and the second section 114 include continuous portions of a sidewall spacer material layer (¶ 0014, Fig. 1e - 112 includes continuous portion of a sidewall spacer material spanning across semiconductor body 102/104; 114 includes a continuous portion of a sidewall spacer material spanning across semiconductor body 102/104),
wherein the first section is positioned laterally adjacent to the first portion (lower portion of 118/116) of the gate structure between the edge region of the second portion (upper portion of 118/116) of the gate structure and the semiconductor fin, wherein the second section 114 is positioned laterally adjacent to the first section and to the second portion (upper portion of 118/116) of the gate structure, and wherein the gate sidewall spacer 112/114 is physically separated from the gate conductor layer 118 by the gate dielectric layer 116 (Fig. 1f).
Rachmady fails to expressly disclose: an additional field effect transistor on the substrate, wherein the additional field effect transistor comprises an additional gate structure with a longer effective gate length than the gate structure; and an additional gate sidewall spacer adjacent to the additional gate structure, and wherein the gate sidewall spacer and the additional gate sidewall spacer have different shapes. In the same field of endeavor, Su discloses field effect transistors on a substrate, wherein each field effect transistor comprises a gate structure, one gate structure with a longer effective gate length than the gate structure of another field effect transistor (Su, ¶ 0024), and an additional gate sidewall spacer 65 (Fig. 1; ¶ 0016) adjacent to the additional gate structure 60 (Fig. 1; ¶ 0016). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the structure of Rachmady to include an additional field effect transistor on the substrate, wherein the additional field effect transistor comprises an additional gate structure with a longer effective gate length than the gate structure, and an additional gate sidewall spacer having a different shape than the gate sidewall spacer, for the purpose of forming devices suitable for differing applications on the same substrate, using conventional and art-recognized configurations of field effect transistors (Su, ¶ 0025).
Regarding claim 9, Rachmady and Su disclose the structure of claim 8, Rachmady discloses wherein the gate dielectric layer 116 comprises at least a high-K dielectric layer (¶ 0022) and wherein the gate conductor layer 118 comprises at least a layer of any of a metal and a metal alloy (¶ 0022).
Regarding claim 10, Rachmady and Su disclose the structure of claim 8, Rachmady discloses wherein the gate structure comprises the gate dielectric layer 116 lining a gate opening and the gate conductor layer 118 on the gate dielectric layer within the gate opening (Fig. 1f), wherein the gate dielectric layer 116 is within the first portion and the second portion, and wherein surfaces of the semiconductor fin 104, the first section 112 of the gate sidewall spacer, and the second section 114 of the gate sidewall spacer are immediately adjacent to the gate dielectric layer 116 and separated from the gate conductor layer 118 by the gate dielectric layer 116 (Fig. 1).
Regarding claim 13, Rachmady and Su disclose the structure of claim 8, Su discloses wherein the additional gate structure comprises an additional semiconductor fin and has approximately equal lengths proximal to the additional semiconductor fin and distal to the additional semiconductor fin (Su, Fig. 33A), however, Rachmady and Su fail to express disclose: the additional gate sidewall spacer includes a discrete portion of the sidewall spacer material. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the additional gate sidewall spacer using the sidewall spacer material (of the first section or second section of the gate sidewall spacer) for the purpose of efficiency in manufacturing, i.e., sidewall spacers of the same material may be formed during the same deposition step.
Regarding claim 14, Rachmady and Su disclose the structure of claim 8, wherein the gate structure and the additional gate structure comprise replacement metal gates (Rachmady, ¶ 0012).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Candice Y. Chan whose telephone number is (571)272-9013. The examiner can normally be reached 8:30 am - 5 pm ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven B. Gauthier can be reached at 571-270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
CANDICE Y. CHAN
Examiner
Art Unit 2813
21 October 2025
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813