Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to independent claim(s) 1, 11 and 21 and dependent claims 2, 12, 9 and 23 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Office now relies on new/additional teaching of the same reference Mrunal Abhijith as explained below in the rejection, as necessitated by Applicant’s amendment. Applicant argues, regarding claims 1, 11 and 21, that Mrunal Abhijith does not teach the amended “a barrier layer serving as a sidewall and a bottom of the second patterned conductive layer, wherein a bottom of the oxide structure partially contacts the barrier layer and partially contacts the second patterned conductive layer”. However, Mrunal Abhijith teaches, in Fig. 1A, the layers 40s/3 that correspond to the barrier layer serving as a sidewall and a bottom of the second patterned conductive layer #4 on the left; and further teaches a bottom of the oxide structure #19 in the center partially contacting the layer 40s and partially contacts the second patterned conductive layer #4 on the left. The amendments of dependent claims 2, 9, 12-13 are also taught by Mrunal Abhijith as explained below.
Hence, the rejection for claims 1-16 and 21-24 is maintained.
Claim Objections
Claim 22 objected to because of the following informalities:
Claim 22 recites “…wherein the first patterned conductive layer is disposed over a conductive structure and is separated by the conductive structure by the barrier layer”. This should be corrected to “…wherein the first patterned conductive layer is disposed over a conductive structure and is separated from the conductive structure by the barrier layer”. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-9, 21-24 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Mrunal Abhijith (US 20210225762 A1).
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Re: Independent Claim 1 (Currently amended), Mrunal Abhijith discloses a semiconductor structure comprising:
a semiconductor substrate (Mrunal Abhijith, Fig 1A, #1);
a first patterned conductive layer (Mrunal Abhijith, Fig1A annotated above, conductive contact #4 in the center) disposed on the semiconductor substrate;
a second patterned conductive layer (Mrunal Abhijith, Fig1A annotated above, conductive contact #4 on the left) disposed on the semiconductor substrate;
a first dielectric layer (Mrunal Abhijith, Fig 1A, #10) disposed on the semiconductor substrate and surrounding the first patterned conductive layer and the second patterned conductive layer;
a third patterned conductive layer (Mrunal Abhijith, Fig1A annotated above, #5’ in the center) disposed on the first patterned conductive layer;
a fourth patterned conductive layer (Mrunal Abhijith, Fig 1A #5’ on the left) disposed on the second patterned conductive layer;
a second dielectric layer (Mrunal Abhijith, Fig1A, #20) disposed on the first dielectric layer;
an oxide structure (Mrunal Abhijith, ¶ [0047], Fig 1A annotated above, #41s on either sides of 5’ in the left and #19 (made of silicon oxynitride) and #40t on the bottom of #20 in the center) in contact with the second dielectric layer, a side surface of the fourth patterned conductive layer (Mrunal Abhijith, Fig 1A annotated above, side surface of #5’ in the left), and a side surface of the third patterned conductive layer (Mrunal Abhijith, Fig 1A annotated above, side surface of #5’ in the center),
and a barrier layer serving as a sidewall and a bottom of the second patterned conductive layer (Mrunal Abhijith, Fig 1A, layer 40s/3 serves as sidewall and bottom of #4 on the left are the claimed barrier layer), wherein a bottom of the oxide structure partially contacts the barrier layer and partially contacts the second patterned conductive layer (Mrunal Abhijith, Fig 1A, bottom of #19 in the center partially contacts the barrier layer 40s and partially contacts #4 on the left).
Re: Claim 2 (Currently amended), Mrunal Abhijith discloses all the limitations of claim 1 on which this claim depends. Mrunal Abhijith further discloses,
a bottom of the first patterned conductive layer contacts a top of the semiconductor substrate (Mrunal Abhijith, Fig1A annotated above, conductive contact #4 in the center contacts the substrate 1 through gate structure 2 in the center).
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Re: Claim 3 (original), Mrunal Abhijith discloses all the limitations of claim 1 on which this claim depends.
Mrunal Abhijith further discloses,
further comprising a third dielectric layer (Mrunal Abhijith, Fig 1A annotated above, #20 in the center) disposed in the first dielectric layer; and
a second oxide structure (Mrunal Abhijith, Fig 1A annotated above, #41s in the center) in contact with the third dielectric layer and the side surface of the third patterned conductive layer.
Re: Claim 4 (original), Mrunal Abhijith discloses all the limitations of claim 1 on which this claim depends.
Mrunal Abhijith further discloses,
wherein the second oxide structure is formed by oxidizing the third dielectric layer (Mrunal Abhijith, Fig 1A annotated above, ¶ [0047], the second densified dielectric layer #41s is formed by performing oxidation operation on the exposed surfaces of the third dielectric layer #20 in the center).
Re: Claim 5 (original), Mrunal Abhijith discloses all the limitations of claim 1 on which this claim depends. Mrunal Abhijith further discloses,
wherein an elevation level of a bottom surface (Mrunal Abhijith, Fig 1A, bottom surface of #5’) of the fourth patterned conductive layer is lower than an elevation level of a top surface (Mrunal Abhijith, Fig 1A, top surface of #4) of the second patterned conductive layer.
Re: Claim 6 (original), Mrunal Abhijith discloses all the limitations of claim 1 on which this claim depends.
Mrunal Abhijith further discloses,
wherein an elevation level of a bottom surface of the fourth patterned conductive layer (Mrunal Abhijith, Fig 1A, bottom surface of #5’) is lower than an elevation level of a bottom end of the oxide structure (Mrunal Abhijith, Fig 1A, bottom end of 41s).
Re: Claim 7 (original), Mrunal Abhijith discloses all the limitations of claim 3 on which this claim depends.
Mrunal Abhijith further discloses,
wherein an elevation level of a bottom end of the second oxide structure (Mrunal Abhijith, Fig 1A annotated above, bottom end of #41s in the center) is aligned with an elevation level of a top surface of the first patterned conductive layer (Mrunal Abhijith, Fig 1A annotated above, top surface of #4 in the center).
Re: Claim 8 (Previously presented), Mrunal Abhijith discloses all the limitations of claim 3 on which this claim depends.
Mrunal Abhijith further discloses,
wherein a third portion (Mrunal Abhijith, Fig 1A annotated above, #5C3) of the side surface of the third patterned conductive layer is disposed between a first portion (Mrunal Abhijith, Fig 1A annotated above, #5C1) of the side surface of the third patterned conductive layer and a second portion (Mrunal Abhijith, Fig 1A annotated above, #5C2) of the side surface of the third patterned conductive layer, and wherein the third portion of the side surface of the third patterned conductive layer is surrounded by the first dielectric layer (Mrunal Abhijith, Fig 1A annotated above, #5C3 is surrounded by first dielectric layer #10).
Re: Claim 9 (Currently amended), Mrunal Abhijith discloses all the limitations of claim 8 on which this claim depends.
Mrunal Abhijith further discloses,
further comprising a fourth dielectric layer (Mrunal Abhijith, Fig 1A, #19 on the left) disposed on the second dielectric layer and on the oxide structure (#19 on the left is disposed on #20 and on oxide structure #40t on the left), wherein a second portion (Mrunal Abhijith, Fig 1A annotated above, #5L2) of the side surface of the fourth patterned conductive layer disposed above the first portion of the side surface of the fourth patterned conductive layer is surrounded by the fourth dielectric layer (Mrunal Abhijith, Fig 1A annotated above, #5L2 deposited over #5L1 is surrounded by fourth dielectric layer #19), wherein a top of the fourth dielectric layer is aligned with a top of the fourth patterned conductive layer (Mrunal Abhijith, Fig 1A annotated above, top of #19 on the left is aligned with top of #5L2), and wherein an interface between the fourth patterned conductive layer and the oxide structure is coplanar with an interface between the fourth patterned conductive layer and the fourth dielectric layer (Interface between #5’ in the left and #41s is coplanar with interface between #5’ in the left and #19 on the left).
Re: Independent Claim 21 (Currently amended), Mrunal Abhijith discloses a semiconductor structure comprising:
a first patterned conductive layer (Mrunal Abhijith, Fig 1A annotated above fig1A, conductive contact #4 in the left);
a second patterned conductive layer (Mrunal Abhijith, Fig 1A annotated above fig1A #5' in the left) disposed on the first patterned conductive layer;
a first dielectric layer (Mrunal Abhijith, Fig 1A annotated above, #10 is dielectric layer) surrounding the first patterned conductive layer;
a second dielectric layer (Mrunal Abhijith, Fig 1A annotated above, #19 on the left) disposed on the first dielectric layer and surrounding the second conductive layer (Mrunal Abhijith, Fig 1A annotated above, #19 disposed on #10 and surrounding #5' in the left);
an oxide structure (Mrunal Abhijith, Fig 1A annotated above, #41s on either side of 5’ in the left, #19 (made of silicon oxynitride) in the center and #40t on the bottom of #20 in the center and left) sandwiched by the second dielectric layer and the second patterned conductive layer (Mrunal Abhijith, Fig 1A annotated above, #41s is sandwiched by #19 on the left and #5’ in the left);
and a barrier layer serving as a sidewall and a bottom of the first patterned conductive layer (Mrunal Abhijith, Fig 1A, layer 40s/3 serves as sidewall and bottom of #4 on the left are the claimed barrier layer), wherein a bottom of the oxide structure partially contacts the barrier layer and partially contacts the first patterned conductive layer (Mrunal Abhijith, Fig 1A, bottom of #19 in the center partially contacts the barrier layer 40s and partially contacts #4 on the left).
Re: Claim 22 (Currently amended), Mrunal Abhijith discloses all the limitations of claim 21 on which this claim depends.
Mrunal Abhijith further discloses,
wherein the first patterned conductive layer (Mrunal Abhijith, Fig 1A, conductive contact #4 in the left) is disposed over a conductive structure (Mrunal Abhijith, Fig 1A, conductive region EP) and is separated by the conductive structure by the barrier layer (#4 is separated from the conductive structure EP by barrier layer 3).
Re: Claim 23 (Currently amended), Mrunal Abhijith discloses all the limitations of claim 21 on which this claim depends.
Mrunal Abhijith further discloses,
further comprising a third dielectric layer disposed on the second dielectric layer and on the oxide structure (Mrunal Abhijith, Fig 1A annotated above, dielectric layer #20 on the left is disposed on #19 on the left and #40t on the left), wherein a top of the third dielectric layer is aligned with a top of the second patterned conductive layer (Mrunal Abhijith, Fig 1A annotated above, a top of #20 on the left (where the level of #20 is same as 5’) is aligned with top of #5' in the left), and wherein an interface between the second patterned conductive layer and the oxide structure is coplanar with an interface between the second patterned conductive layer and the third dielectric layer (Interface between #5’ in the left and #41s is coplanar with interface between #5’ in the left and #20 on the left).
Re: Claim 24 (original), Mrunal Abhijith discloses all the limitations of claim 21 on which this claim depends.
Mrunal Abhijith further discloses,
wherein the barrier layer comprises a non-oxide material (Mrunal Abhijith teaches, in ¶ [0025], the barrier layer 3 is silicide layer, i.e., non-oxide).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Mrunal Abhijith (US 20210225762 A1) in the view of Hsiao (US 20230178614 A1).
Re: Claim 10 (original), Mrunal Abhijith discloses all the limitations of claim 9 on which this claim depends.
Mrunal Abhijith further discloses,
wherein a fourth portion (Mrunal Abhijith, Fig 1A annotated above, #5C4) of the side surface of the third patterned conductive layer disposed above the first portion of the side surface of the third patterned conductive layer is surrounded by the third dielectric layer (Mrunal Abhijith, Fig 1A annotated above, #5C4 disposed above #5C1 is surrounded by #20 in the center).
Mrunal Abhijith is silent regarding:
wherein a bottom end of the fourth portion of the side surface of the third patterned conductive layer is aligned with a top end of the oxide structure.
However, Hsiao teaches a bottom end of the fourth portion of the side surface of the third patterned conductive layer (Hsiao, Fig 1, bottom end of #14) is aligned with a top end of the oxide structure (Hsiao, Fig 1, ¶ [0057], #13). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention, to adopt the alignment of the portion of side surface of patterned conductive layer with a top end of the oxide structure in the structure of Mrunal Abhijith in order to ensure the insulating layers are positioned effectively to prevent unwanted current leakage.
Claims 11-16 are rejected under 35 U.S.C. 103 as being unpatentable over Mrunal Abhijith (US 20210225762 A1).
Re: Independent Claim 11 (Currently amended), Mrunal Abhijith discloses a semiconductor structure comprising:
a semiconductor substrate (Mrunal Abhijith, fig 1A, #1);
a first patterned conductive layer (Mrunal Abhijith, Fig1A, conductive contact #4 in the center) disposed on the semiconductor substrate;
a second patterned conductive layer (Mrunal Abhijith, Fig1A, conductive contact #4 in the left) disposed on the semiconductor substrate;
a first dielectric layer (Mrunal Abhijith, Fig 1A, #10 is dielectric layer) disposed on the semiconductor substrate and surrounding the first patterned conductive layer and the second patterned conductive layer (Mrunal Abhijith, Fig 1A annotated above, #10 surrounds #4 in the center and #4 in the left);
a second dielectric layer (Mrunal Abhijith, fig1A annotated above, #20 in the left) disposed on the first patterned conductive layer and the second patterned conductive layer;
first and second oxide ring structures surrounded by the second dielectric layer (Mrunal Abhijith, Fig 1A annotated above, ¶ [0028] #41s/#19 on either side of #5’ in the center and #41s/#19 on either side of #5’ in the left side, both of #41s/#19 surround #5’. While Mrunal Abhijith does not explicitly refer to the oxide structure as a “ring”, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to recognize or form this structure in a ring-like geometry, as the oxide structure of Mrunal Abhijith surrounds the conductive layer, which is functionally and structurally consistent with a ring in order to provide encapsulation, isolation or structural stability);
a third patterned conductive layer (Mrunal Abhijith, Fig1A annotated above, #5' in the center and right side) disposed on the first patterned conductive layer, wherein a first portion of a side surface of the third patterned conductive layer (Mrunal Abhijith, Fig1A annotated above, portion of side surface of #5' in the center) is surrounded by the first oxide ring structure (Mrunal Abhijith, Fig1A annotated above, #41s on either side of #5 in the center);
a fourth patterned conductive layer (Mrunal Abhijith, Fig1A annotated above, #5 in the left) disposed on the second patterned conductive layer, wherein a first portion of a side surface of the fourth patterned conductive layer (Mrunal Abhijith, Fig1A annotated above, #5L1 in the annotated figure above) is surrounded by the second oxide ring structure (Mrunal Abhijith, Fig1A annotated above, #41s on either side of #5 in the left side); and
a barrier layer serving as a sidewall and a bottom of the second patterned conductive layer (Mrunal Abhijith, Fig 1A, layer 40s/3 serves as sidewall and bottom of #4 on the left are the claimed barrier layer),
wherein a bottom of the second oxide ring structure partially contacts the barrier layer and partially contacts the second patterned conductive layer (Mrunal Abhijith, Fig 1A, bottom of #19 in the left partially contacts the barrier layer 40s and partially contacts #4 on the left), and
wherein a lateral width of the first oxide ring structure (Mrunal Abhijith, Fig 1A annotated above, lateral width of #41s on either side of #5 in the center) is less than a lateral width of the first patterned conductive layer (Mrunal Abhijith, Fig1A annotated above, lateral width of conductive contact #4 in the center), and a lateral width of the second oxide ring structure (Mrunal Abhijith, Fig 1A annotated above, lateral width of #41s on either sides of #5 in the left side) is less than a lateral width of the second patterned conductive layer (Mrunal Abhijith, Fig1A annotated above, Lateral Width of conductive contact #4 on the left side).
Re: Claim 12 (Currently amended), Mrunal Abhijith discloses all the limitations of claim 11 on which this claim depends.
Mrunal Abhijith further discloses,
wherein a bottom of the first patterned conductive layer contacts a top of the semiconductor substrate (Mrunal Abhijith, Fig1A annotated above, conductive contact #4 in the center contacts the substrate 1 through gate structure 2 in the center).
Re: Claim 13 (original), Mrunal Abhijith discloses all the limitations of claim 11 on which this claim depends.
Mrunal Abhijith further discloses,
further comprising a third dielectric layer (Mrunal Abhijith, Fig1A annotated above, #20 in the center and right side) disposed in the first dielectric layer;
and a third oxide ring structure (oxide structures #41s in the either side of 5' in the right side. While Mrunal Abhijith does not explicitly refer to the oxide structure as a “ring”, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to recognize or form this structure in a ring-like geometry, as the oxide structure of Mrunal Abhijith surrounds the conductive layer, which is functionally and structurally consistent with a ring in order to provide encapsulation, isolation or structural stability) surrounding a second portion of the side surface of the third patterned conductive layer (Mrunal Abhijith, Fig1A annotated above, portion of side surface of #5' in the right).
Re: Claim 14 (original), Mrunal Abhijith discloses all the limitations of claim 13 on which this claim depends.
Mrunal Abhijith further discloses,
wherein the third oxide ring structure is formed by oxidizing a portion of the third dielectric layer (Mrunal Abhijith, Fig1A annotated above Fig 1A, ¶ [0028], #41s in the either side of 5’ is formed by oxidizing #20 in the center and right side).
Re: Claim 15 (Currently amended), Mrunal Abhijith discloses all the limitations of claim 11 on which this claim depends.
Mrunal Abhijith further discloses,
wherein an elevation level of a bottom surface of the fourth patterned conductive layer (Mrunal Abhijith, Fig1A annotated above, bottom surface of #5 in the left) is lower than an elevation level of a top surface of the second patterned conductive layer (Mrunal Abhijith, Fig1A annotated above, top surface of conductive contact #4 on the left side),
and an elevation level of a bottom surface of the fourth patterned conductive layer is lower than an elevation level of a bottom end of the second oxide ring structure (elevation of bottom surface of #5 in the left is lower than elevation of bottom end of #41s/#19 on either side of #5’ in the left side).
Re: Claim 16 (Currently amended), Mrunal Abhijith discloses all the limitations of claim 11 on which this claim depends.
Mrunal Abhijith further discloses,
Wherein a bottom of the first patterned conductive layer contacts a top of the semiconductor substrate (Mrunal Abhijith, Fig1A annotated above, conductive contact #4 in the center contacts the substrate 1 through gate structure 2 in the center).
Conclusion
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/BIPANA ADHIKARI DAWADI/Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898
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