DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, 6-10, and 12-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bergmann et al. (US 2017/0229431) in view of Edmond et al. (US 2017/0294418).
With regard to claim 1, Bergmann teaches, in Figs 1A-1G, a method comprising: providing a light-emitting diode (LED) wafer (100) comprising a plurality of LED chips (each instance of 114, 162, etc.), each LED chip of the plurality of LED chips comprising an anode contact (160) and a cathode contact (170); providing a submount wafer (180) comprising a first metallization pattern (184, 186) on a frontside of the submount wafer and a second metallization pattern (192, 194) on a backside of the submount wafer, the second metallization pattern being electrically coupled to the first metallization pattern ([0055]); bonding the LED wafer to the frontside of the submount wafer such that the anode contact and the cathode contact of each LED chip are electrically coupled to the first metallization pattern (see Fig. 1C); and singulating the LED wafer and the submount wafer to form a plurality of light-emitting devices (Fig. 1F - Fig. 1G), each light-emitting device of the plurality of light-emitting devices comprising a substrate (110’) formed from the LED wafer, an array of LED chips (110) of the plurality of LED chips, and a submount (180’) formed from the submount wafer; wherein the first metallization pattern comprises a separate pair of an anode metal trace (184) and a cathode metal trace (186) that are respectively bonded to the anode contact and the cathode contact of each LED chip of the plurality of LED chips, and wherein the second metallization pattern comprises a first metal trace (184) that forms an anode mounting pad, and a third metal trace (186) that forms a cathode mounting pad.
Bergmann does not explicitly teach a second metal trace that forms part of an electrically conductive path between the first metal trace and the third metal trace.
Edmond teaches, in Figs. 12B-12E, a second metal trace (103, 107) that forms part of an electrically conductive path between the first metal trace and the third metal trace so that, “Multiplex sequencing may be used to permit individual control of each LED of the array while employing a smaller number of conductors than the number of LEDs in the array,” ([0233]).
Therefore, it would have been obvious to the ordinary artisan at the time of filing to combine the method of Bergmann with the electrical connections of Edmond to allow for LED control with a smaller number of conductors.
With regard to claim 2, Bergmann teaches, in Figs 1A-1G, that the LED wafer comprises a substrate structure that is subdivided to form each substrate of the plurality of light-emitting devices, and the submount wafer comprises a submount structure that is subdivided to form each submount of the plurality of light-emitting devices ([0067]).
With regard to claim 3, Bergmann teaches, in Figs 1A-1G, that the substrate structure comprises a sapphire wafer on which the plurality of LED chips are formed ([0054]).
With regard to claim 4, Bergmann teaches, in Figs 1A-1G, that the submount structure comprises aluminum oxide or aluminum nitride ([0055]).
With regard to claim 6, Edmond teaches, in Figs. 15, that the second metal trace is electrically connected between the cathode metal trace of a first LED chip of the plurality of LED chips and the anode metal trace of a second LED chip of the plurality of LED chips (through driver circuitry 126, see [0234]-[0248]).
With regard to claim 7, Edmond teaches, in Figs. 3A-3B, that a spacing between next adjacent LED chips (10) of the plurality of LED chips is less than or equal to 40 microns (µm) ([0199]).
With regard to claim 8, Edmond teaches, in Figs. 3B-3B, that the spacing is in a range from 10 µm to 40 µm ([0199]).
With regard to claim 9, Bergmann teaches, in Figs 1A-1G, that the plurality of LED chips are subdivided from a common epitaxial LED structure ([0053]).
With regard to claim 10, Bergmann teaches, in Figs 1A-1G, that bonding the LED wafer to the frontside of the submount wafer comprises thermocompression bonding, eutectic bonding, transient liquid phase bonding, bump bonding, or solder paste bonding the anode contact and the cathode contact to the first metallization pattern ([0061]).
With regard to claim 12, Edmond teaches, in Figs. 25A-25B, forming an underfill material (99) in gaps between the LED wafer and the submount wafer.
With regard to claim 13, Edmond teaches, in Figs. 12A-13E, that the array of LED chips are electrically coupled in series, in parallel, or in series and parallel ([0234]-[0235]).
With regard to claim 14, Edmond teaches, in Figs. 12A-13E, that the second metallization pattern comprises: a first pattern of metal traces configured to electrically couple the array of LED chips for a first light-emitting device of the plurality of light-emitting devices with a first electrical configuration; and a second pattern of metal traces configured to electrically couple the array of LED chips for a second light-emitting device of the plurality of light-emitting devices with a second electrical configuration ([0234]-[0235]).
With regard to claim 15, Bergmann teaches, in Figs 1A-1G, that the submount structure comprises a multiple layer ceramic structure ([0055]).
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bergmann et al. (US 2017/0229431) in view of Edmond et al. (US 2017/0294418) and Henley (US 2018/0019169).
With regard to claim 11, Bergmann/Edmond discloses the claimed invention except for the use of thermos-compression bonding instead of ceramic bonding. Henley teaches ([0024]) that ceramic bonding and thermos-compression bonding are equivalent bonding methods known in the art. Therefore, because these irreversible wafer bonding methods were art-recognized equivalents at the time of the invention was made and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, one of ordinary skill in the art would have found it obvious to substitute ceramic bonding for thermos-compression bonding since the substitution would yield predictable results. See Supreme Court decision in KSR International Co. v. Teleflex Inc., 550 U.S. _, 82 YSPQ2d 1385 (2007).
Allowable Subject Matter
Claims 16-20 and 23 are allowed.
The following is a statement of reasons for the indication of allowable subject matter: the prior art of record fails to anticipate or render obvious claimed limitations of wherein the first underfill material and the second underfill material form a ceramic bond between the LED wafer and the submount wafer, as set forth in independent claim 16, when taken in concert with all the other limitations of the claim. Claims 17-20 and 23 depend from claim 16.
Response to Arguments
Applicant's arguments filed 4/27/2026 have been fully considered but they are not persuasive.
The Applicants argue:
the Office Action points to FIGS. 12B-12E of Edmond with respect to the third metal trace. However, the series connections 103 and 107 as noted by the Office Action are part of carrier interfaces that are entirely separate from the light emitting device 12A. That is, FIGS. 12B-12D represent views of an interface element on which the light emitting device 12A may subsequently be mounted after it is singulated.
Turning back to Bergmann, singulation occurs between FIGS. iF and 1G. Accordingly, the ordinary artisan would consider that the already singulated device of FIG. 1G of Bergmann may then be mounted to an interface element like what is shown in FIGS. 12B-12D of Edmond. In contrast, amended claim 1 provides the third metal trace as part of the submount wafer that is bonded to the LED wafer before singulation.
The Examiner responds:
The claims only require the second metallization pattern to be “on a backside of the submount wafer”. Thus the cited connections 103 and 107 formed on the “interface element” of Edmond, once connected to the submount wafer of Bergmann, could be reasonably construed as part of the second metallization pattern, thus meeting the claim. The distinctions pointed out by the Applicant between the instant disclosure and the prior art are not reflected in the claims. Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). Furthermore, these arguments are directed at distinctions in intermediate manufacturing steps and not the final product, as the claims are directed to.
All other arguments have been fully addressed in prior Office Actions, the rejections set forth above, or are moot because they do not apply to the present rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RAJ R GUPTA whose telephone number is (571)270-5707. The examiner can normally be reached 9:30AM-4PM, 8PM-10PM.
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/RAJ R GUPTA/Primary Examiner, Art Unit 2893
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