DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis ( i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale , or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1-5, 9, 10, and 15 is/are rejected under 35 U.S.C. 102(a) (1)/(a) (2) as being anticipated by Bergmann et al. (US 2017/0229431) . With regard to claim 1 , Bergmann teaches, in Figs 1A-1G, a method comprising: providing a light-emitting diode (LED) wafer (100) comprising a plurality of LED chips (each instance of 114, 162, etc.) , each LED chip of the plurality of LED chips comprising an anode contact (160) and a cathode contact (170) ; providing a submount wafer (180) comprising a first metallization pattern (184, 186) on a frontside of the submount wafer and a second metallization pattern (192, 194) on a backside of the submount wafer, the second metallization pattern being electrically coupled to the first metallization pattern ([0055]) ; bonding the LED wafer to the frontside of the submount wafer such that the anode contact and the cathode contact of each LED chip are electrically coupled to the first metallization pattern (see Fig. 1C) ; and singulating the LED wafer and the submount wafer to form a plurality of light-emitting devices (Fig. 1F - Fig. 1G) , each light-emitting device of the plurality of light-emitting devices comprising a substrate (110’) formed from the LED wafer, an array of LED chips (110) of the plurality of LED chips, and a submount (180’) formed from the submount wafer. With regard to claim 2 , Bergmann teaches, in Figs 1A-1G, that the LED wafer comprises a substrate structure that is subdivided to form each substrate of the plurality of light-emitting devices, and the submount wafer comprises a submount structure that is subdivided to form each submount of the plurality of light-emitting devices ([0067]) . With regard to claim 3 , Bergmann teaches, in Figs 1A-1G, that the substrate structure comprises a sapphire wafer on which the plurality of LED chips are formed ([0054]) . With regard to claim 4 , Bergmann teaches, in Figs 1A-1G, that the submount structure comprises aluminum oxide or aluminum nitride ([0055]) . With regard to claim 5 , Bergmann teaches, in Figs 1A-1G, that the first metallization pattern comprises a separate pair of an anode metal trace (184) and a cathode metal trace (186) that are respectively bonded to the anode contact and the cathode contact of each LED chip of the plurality of LED chips. With regard to claim 9 , Bergmann teaches, in Figs 1A-1G, that the plurality of LED chips are subdivided from a common epitaxial LED structure ([0053]) . With regard to claim 1 0 , Bergmann teaches, in Figs 1A-1G, that bonding the LED wafer to the frontside of the submount wafer comprises thermocompression bonding, eutectic bonding, transient liquid phase bonding, bump bonding, or solder paste bonding the anode contact and the cathode contact to the first metallization pattern ([0061]) . With regard to claim 1 5 , Bergmann teaches, in Figs 1A-1G, that the submount structure comprises a multiple layer ceramic structure ([0055]) . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 6-8, 12-14, 16-21, and 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bergmann et al. (US 2017/0229431) in view of Edmond et al. (US 2017/0294418) . With regard to claim 6 , Bergmann teaches most of the limitations of the claim, as set forth above with regard to claim 5. Bergman also teaches , in Figs 1A-1G, that the second metallization pattern comprises a first metal trace (184) that forms an anode mounting pad, a second metal trace (186) that forms a cathode mounting pad . Bergmann does not explicitly teach a third metal trace that forms part of an electrically conductive path between the first metal trace and the second metal trace. Edmond teaches, in Figs. 12B-12E, a third metal trace (103, 107) that forms part of an electrically conductive path between the first metal trace and the second metal trace so that, “ Multiplex sequencing may be used to permit individual control of each LED of the array while employing a smaller number of conductors than the number of LEDs in the array ,” ([0233]) . Therefore, it would have been obvious to the ordinary artisan at the time of filing to combine the method of Bergmann with the electrical connections of Edmond to allow for LED control with a smaller number of conductors. With regard to claim 7 , Bergmann teaches most of the limitations of the claim, as set forth above with regard to claim 1 . Bergmann does not explicitly teach that a spacing between next adjacent LED chips of the plurality of LED chips is less than or equal to 40 microns ( µ m) . Edmond teaches, in Figs. 3 A - 3B , that a spacing between next adjacent LED chips (10) of the plurality of LED chips is less than or equal to 40 microns ( µ m) ([0199]) since, “ high resolution displays suitable for very short viewing distances, as well as vehicular headlamps, may benefit from smaller pixel pitches ,” ([0006]). Therefore, it would have been obvious to the ordinary artisan at the time of filing to combine the method of Bergmann with the pixel pitches of Edmond since high resolution displays suitable for very short viewing distances, as well as vehicular headlamps, may benefit from smaller pixel pitches . With regard to claim 8 , Edmond teaches, in Figs. 3B-3B, that the spacing is in a range from 10 µ m to 40 µ m ([0199]) . With regard to claim 12 , Bergmann teaches most of the limitations of the claim, as set forth above with regard to claim 1. Bergmann does not explicitly teach forming an underfill material in gaps between the LED wafer and the submount wafer. Edmond teaches, in Figs. 25A - 25 B, forming an underfill material (99) in gaps between the LED wafer and the submount wafer , “ to enable the coefficient of thermal expansion (CTE) to be adjusted ,” ([0232]) . Therefore, it would have been obvious to the ordinary artisan at the time of filing to combine the method of Bergmann with the underfill material of Edmond to enable the coefficient of thermal expansion (CTE) to be adjusted . With regard to claim 13 , Bergmann teaches most of the limitations of the claim, as set forth above with regard to claim 1 . Bergmann does not explicitly teach that the array of LED chips are electrically coupled in series, in parallel, or in series and parallel . Edmond teaches, in Figs. 12 A -1 3 E, that the array of LED chips are electrically coupled in series, in parallel, or in series and parallel ([0234]-[0235]) so that, “ Multiplex sequencing may be used to permit individual control of each LED of the array while employing a smaller number of conductors than the number of LEDs in the array ,” ([0233]) . Therefore, it would have been obvious to the ordinary artisan at the time of filing to combine the method of Bergmann with the electrical connections of Edmond to allow for LED control with a smaller number of conductors. With regard to claim 1 4 , Bergmann teaches most of the limitations of the claim, as set forth above with regard to claim 1. Bergmann does not explicitly teach that the second metallization pattern comprises: a first pattern of metal traces configured to electrically couple the array of LED chips for a first light-emitting device of the plurality of light-emitting devices with a first electrical configuration; and a second pattern of metal traces configured to electrically couple the array of LED chips for a second light-emitting device of the plurality of light-emitting devices with a second electrical configuration. Edmond teaches, in Figs. 12A-13E, that the second metallization pattern comprises: a first pattern of metal traces configured to electrically couple the array of LED chips for a first light-emitting device of the plurality of light-emitting devices with a first electrical configuration; and a second pattern of metal traces configured to electrically couple the array of LED chips for a second light-emitting device of the plurality of light-emitting devices with a second electrical configuration ([0234]-[0235]) so that, “ Multiplex sequencing may be used to permit individual control of each LED of the array while employing a smaller number of conductors than the number of LEDs in the array ,” ([0233]) . Therefore, it would have been obvious to the ordinary artisan at the time of filing to combine the method of Bergmann with the electrical connections of Edmond to allow for LED control with a smaller number of conductors. With regard to claim 1 6 , Bergmann teaches, in Figs 1A-1G, a method comprising: providing a light-emitting diode (LED) wafer (100) comprising a plurality of LED chips (each instance of 114, 162, etc.) on a substrate structure (120) ; providing a submount wafer (180) comprising a first metallization pattern (184, 186) on a frontside of the submount wafer and a second metallization pattern (192, 194) on a backside of the submount wafer, the second metallization pattern being electrically coupled to the first metallization pattern ([0055]) ; bonding the LED wafer to the frontside of the submount wafer such that plurality of LED chip s are electrically coupled to the first metallization pattern (see Fig. 1C) ; and singulating the LED wafer and the submount wafer to form a plurality of light-emitting devices (Fig. 1F - Fig. 1G) , each light-emitting device of the plurality of light-emitting devices comprising an array of LED chips (110) of the plurality of LED chips and a submount (180’) formed from the submount wafer Bergmann does not explicitly teach forming a first underfill material on the LED wafer . Edmond teaches, in Figs. 2 2A- 22C , forming a first underfill material (176) on the LED wafer , “ to reduce interaction between emissions of different LEDs and/or lumiphoric material regions to reduce scattering and/or optical crosstalk, thereby preserving pixel-like resolution of the resulting emissions ,” ([0007]) . Therefore, it would have been obvious to the ordinary artisan at the time of filing to combine the method of Bergmann with the underfill of Edmond for preserving pixel-like resolution of the resulting emissions . With regard to claim 1 7 , Edmond teaches, in Figs. 7 A- 7 C, that the LED wafer comprises a plurality of streets (70) that define boundaries of each LED chip (60) of the plurality of LED chips and the first underfill material (76) is arranged to fill portions of the plurality of streets. With regard to claim 1 8 , Edmond teaches, in Figs. 7A-7C, that the first underfill material comprises light- reflective materials configured to reflect or redirect light from the plurality of LED chips ([0264]) . With regard to claim 1 9 , Edmond teaches that the first underfill material is formed on the LED wafer after the LED wafer is mounted to the submount wafer ([0299]) . With regard to claim 20 , Edmond teaches, in Figs. 24A-24B , that the first underfill material is formed on the LED wafer before the LED wafer is mounted to the submount wafer. With regard to claim 2 1 , Edmond teaches, in Figs. 24A-24B, forming a second underfill material (177) on the submount wafer before the LED wafer is mounted to the submount wafer. that the first underfill material is formed on the LED wafer before the LED wafer is mounted to the submount wafer. With regard to claim 2 3 , Edmond teaches, in Figs. 12A-13E, that the array of LED chips are electrically coupled in series, in parallel, or in series and parallel ([0234]-[0235]) . Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bergmann et al. (US 2017/0229431) in view of Henley (US 201 8/0019169 ) . With regard to claim 11 , Bergmann disclose s the claimed invention except for the use of thermos-compression bonding instead of ceramic bonding . Henley teaches ( [0024] ) that ceramic bonding and thermos-compression bonding are equivalent bonding methods known in the art. Therefore, because these irreversible wafer bonding methods were art-recognized equivalents at the time of the invention was made and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, one of ordinary skill in the art would have found it obvious to substitute ceramic bonding for thermos-compression bonding since the substitution would yield predictable results. See Supreme Court decision in KSR International Co. v. Teleflex Inc., 550 U.S. _, 82 YSPQ2d 1385 (2007). Allowable Subject Matter Claim 22 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: the prior art of record fails to anticipate or render obvious claimed limitations of wherein the first underfill material and the second underfill material form a ceramic bond between the LED wafer and the submount wafer , as set forth in claim 22, when taken in concert with all the other limitations of the base claim and intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT RAJ R GUPTA whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)270-5707 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT 9:30AM-4PM, 8PM-10PM . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /RAJ R GUPTA/ Primary Examiner, Art Unit 2893