DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
Acknowledgement is made of the amendment received on 3/11/2026. Claims 1-15 and 21-25 are pending in this application. Claims 1, 9, 15, and 21 are amended.
Information Disclosure Statement
Applicant is suggested/reminded to disclose relevant prior art(s) or other information that may be material to the patentability of the invention in a pending application. The prior art information must be submitted in the form of an Information Disclosure Statement (“IDS”) (see MPEP 609 & 2001 and 37 CFR 1.56).
Claim Objections
Claims 1, 9, and 21 is objected to because of the following informalities:
In claim 1, line 11, “extending from the substrate” should read --extending from a substrate-- (emphasis added).
In claim 9, lines 5-6, “(TSV) disposed in the insulating layer and over the insulating layer” should read --(TSV) extending through and above the insulating layer--and lines 12-13, “(TSV) disposed in the insulating layer and over the insulating layer, wherein a top of the TSV is substantially coplanar with a top of the seal ring” should read --(TSV) extending through and above the insulating layer, -- (emphasis added).
In claim 21, lines 9-10, “(TSV) disposed in the insulating layer and over the insulating layer” should read --(TSV) extending through and above the insulating layer-- (emphasis added).
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-15 and 21-25 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1, 9, and 21 have been amended to recite limitation “a top of the TSV is substantially coplanar with a top of the seal ring”, which is not clear because the claims fail to clearly identify which seal ring corresponds to the recited coplanar relationship in the claimed semiconductor device.
Specifically, claims 1, 9, and 21 is directed to a semiconductor device. However, the specification describes multiple distinct seal ring-related structures formed at different fabrication stages, including intermediate seal rings 105 (FIG. 5G, [0022-0024]) and completed seal ring structures 135 formed after additional interconnect layers are subsequently stacked (FIGS. 9 and 10, [0030-0033]). The specification further describes that TSVs 120 are planarized during an intermediate fabrication stage at the level of the top ILD layer 112 (FIG. 8B, [0029]) prior to formation of the additional interconnect structure 130 and completed seal ring structure 135 (FIGS. 9-10).
Accordingly, because claim 1 is directed to a final semiconductor device, it is unclear whether the recited coplanar relationship refers to;
an intermediate seal ring formed prior to completion of the semiconductor device; or
a completed seal ring structure of the semiconductor device.
Therefore, the metes and bounds of the claimed semiconductor device cannot be determined with reasonable certainty.
For best understand and examination purpose, the claim will be best considered based on drawings, disclosure, and/or any applicable prior arts; and the claim limitation “a top of the TSV is substantially coplanar with a top of a corresponding seal ring structure” will be interpreted as “a top of the TSV is substantially coplanar with a top of the seal ring” in the instant Office Action.
Claims 2-8, 10-15, and 22-25 are rejected for being dependent on claims 1, 9, and 21, respectively.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5, and 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Kuo (US 2010/0140749) in view of Yamada et al. (US 2019/0051620; hereinafter ‘Yamada’), and Lin et al. (US 2012/0112322; hereinafter ‘Lin’).
Regarding claim 1, Kuo teaches a semiconductor device (3D package structure, FIG. 1, [0007]), comprising:
a first chip (1, [0008]); and
a second chip (2, [0009]), bonded over and electrically connected to the first chip (shown in FIG. 1), and including a seal ring (the right 332 of FIG. 3, since FIG. 3 illustrates a sectional diagram of 1 and 2, FIG. 3, [0024]; hereinafter ‘332R’) disposed at a periphery of the second chip (332R disposed at the periphery of 2, since 332R is positioned outside of 34 corresponding to 24 of FIG. 1) and within the second chip (332R being disposed within 2),
wherein the second chip (2 of FIG. 1 corresponds to the structure shown in FIG. 3) further comprises:
an insulating layer (insulating structures disposed above the circuit area 331 and between conductive features within the metal interconnect layers 33, FIG. 3, [0024]; hereinafter ‘IL’) with a transistor (transistor, [0025]; hereinafter ‘Tr’) disposed therein (Tr being disposed beneath and within the region defined by IL above 331, FIG. 3);
at least one through silicon via (TSV) (34, FIG. 3, [0024]) extending from the substrate (34) and through the insulating layer (IL); and
an interconnect structure (portions of connecting circuit 333 coupled to 331, FIG. 3, [0024]; hereinafter ‘IS’) disposed over the circuit area (331) and including a conductive line (horizontal metal layers of IS) and a conductive via (vertical interconnections of IS) electrically connecting to the transistor (Tr), and
wherein the transistor (Tr), the TSV (34) and the interconnect structure (IS) are surrounded by the seal ring (332R disposed on the periphery of 331 including Tr and on the periphery of 34 and IS, as shown in FIG. 3, wherein FIGS. 6-11 further illustrate the surrounding shelter structure 332, [0025, 0028]).
Kuo does not teach the semiconductor device wherein the second chip, from a top view, includes a first number of sides, the seal ring includes a second number of sides from the top view, the first number is greater than four, and the second number is equal to or greater than the first number.
Yamada teaches a semiconductor device (FIG. 16, [0256])
wherein the second chip (the chip defined along the scribe line corresponding to 1, [0092]; hereinafter ‘SCYamada’), from a top view (a plane view), includes a first number of sides from the tip view (SCYamada includes at least 5 sides),
the seal ring (3) includes a second number of sides from the top view (3 includes at least 5 sides),
the first number is greater than four (the first number is 5), and
the second number is equal to or greater than the first number (shown in FIG. 16).
As taught by Yamada, one of ordinary skill in the art would utilize and modify the above teaching into Kuo to obtain and achieve the semiconductor device wherein the second chip, from a top view, includes a first number of sides, the seal ring includes a second number of sides from the top view, the first number is greater than four, and the second number is equal to or greater than the first number as claimed, because a chamfered corner locally reduces stress concentration and suppresses straight-line crack propagation at the chip corner, thereby improving the protection of internal structures [0255].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Yamada in combination with Kuo due to above reason.
Kuo in view of Yamada does not teach the semiconductor device wherein a top of the TSV is substantially coplanar with a top of the seal ring.
Lin teaches a semiconductor device (50, FIG. 6, [0026]) wherein a top of the TSV is substantially coplanar with a top of the seal ring (a top of the TSV 125 is coplanar with a top of seal ring 120 by a CMP process, [0016, 0022]).
As taught by Lin one of ordinary skill in the art would utilize and modify the above teaching into Kuo in view of Yamada to obtain and achieve the semiconductor device wherein a top of the TSV is substantially coplanar with a top of the seal ring as claimed, because it provides a substantially flat surface suitable for subsequent fabrication and bonding processes [0026].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Lin in combination with Kuo in view of Yamada due to above reason.
Regarding claim 2, Kuo in view of Yamada and Lin teaches the semiconductor device of claim 1, wherein the seal ring (Kuo: 332R) extends continuously along the sides of the second chip from the top view (shown in FIGS. 6, 8, and 10).
Regarding claim 3, Kuo in view of Yamada and Lin teaches the semiconductor device of claim 1, but Kuo in view of Lin does not teach the semiconductor device wherein the sides of the second chip include a beveled edge, a chamfered edge or a fillet edge.
Yamada teaches the semiconductor device wherein the sides of the second chip include a beveled edge, a chamfered edge or a fillet edge (SCYamada includes a chamfered edge, FIG. 16).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Yamada to obtain and achieve the semiconductor device wherein the sides of the second chip include a beveled edge, a chamfered edge or a fillet edge as claimed, because a chamfered corner locally reduces stress concentration and suppresses straight-line crack propagation at the chip corner, thereby improving the protection of internal structures [0255].
Regarding claim 5, Kuo in view of Yamada and Lin teaches the semiconductor device of claim 1, but Kuo in view of Lin does not teach the semiconductor device wherein the second chip includes a buffer region at a corner intersected by two adjacent sides.
Yamada teaches the semiconductor device wherein the second chip includes a buffer region (SCYamada includes the locally recessed corner region, FIG. 16; hereinafter ‘BRYamada’) at a corner intersected by two adjacent sides (shown in FIG. 16).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Yamada to obtain and the semiconductor device wherein the second chip includes a buffer region at a corner intersected by two adjacent sides as claimed, because the buffer region locally reduces stress concentration and suppresses straight-line crack propagation at the chip corner, thereby improving the protection of internal structures [0255].
Regarding claim 7, Kuo in view of Yamada and Lin teaches the semiconductor device of claim 5, but Kuo in view of Lin does not teach the semiconductor device wherein the seal ring extends across the buffer region.
Yamada teaches the semiconductor device wherein the seal ring extends across the buffer region (3 extends across BRYamada, FIG. 16).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Yamada to obtain and achieve the semiconductor device wherein the seal ring extends across the buffer region as claimed, because it prevents a discontinuity of the protection at the buffer region, thereby improving crack blocking and moisture protection [0264, 0266].
Regarding claim 8, Kuo in view of Yamada and Lin teaches the semiconductor device of claim 5, Kuo in view of Lin does not teach the semiconductor device wherein the buffer region is in a triangular shape from the top view.
Yamada teaches the semiconductor device wherein the buffer region is in a triangular shape from the top view (BRYamada, is in a triangular shape, FIG. 16).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Yamada to obtain and achieve the semiconductor device wherein the buffer region is in a triangular shape from the top view as claimed, because the chamfered triangular buffer region locally reduces corner stress, maintains continuity of the protection structure, and prevents corner-initiated crack propagation [0264, 0266].
Claims 4 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Kuo (US 2010/0140749) in view of Yamada (US 2019/0051620) and Lin (US 2012/0112322), and further in view of Mariani et al. (US 2015/0069576; hereinafter ‘Mariani’).
Regarding claim 4, Kuo in view of Yamada and Lin teaches the semiconductor device of claim 1, but does not teach the semiconductor device wherein the second chip has a plurality of substantially rounded corners from the top view.
Mariani teaches a semiconductor device (11, FIGS. 4A and 4B, [0039-0040]) wherein the second chip (12) has a rounded outer contour (shown in FIG. 4B).
As taught by Mariani, one of ordinary skill in the art would utilize and modify the above teaching into Kuo in view of Yamada and Lin to obtain and achieve the semiconductor device wherein the second chip has a plurality of substantially rounded corners from the top view as claimed, because rounding the corners of the semiconductor chip reduces the concentration of stress at the edges or corners [0059-0060]. Further a change in shape is generally recognized as being within the level of ordinary skill in the art. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Mariani in combination with Kuo in view of Yamada and Lin due to above reason.
Regarding claim 6, Kuo in view of Yamada and Lin teaches the semiconductor device of claim 5, but Kuo in view of Yamada and Lin does not teach the semiconductor device wherein the buffer region has a longest side distant from the corner by at least 1 micrometer (μm).
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Mariani teaches a semiconductor device (11, FIGS. 4A and 4B, [0039-0040]) wherein the buffer region (a buffer region, see the annotated FIG. 1D; hereinafter referred to as ‘BRMariani’) has a longest side distant from the corner by at least 1 μm (the longest side distant is 8.75 μm when the second width w2 is 17.5 μm, [0047]).
As taught by Mariani, one of ordinary skill in the art would utilize and modify the above teaching into Kuo in view of Yamada and Lin to obtain and achieve the semiconductor device wherein the buffer region has a longest side distant from the corner by at least 1 μm as claimed, because rounding the corners of the semiconductor chip reduces the concentration of stress at the edges or corners [0059-0060]. Further a change in shape is generally recognized as being within the level of ordinary skill in the art. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Mariani in combination with Kuo in view of Yamada and Lin due to above reason.
Claims 9 and 11-14 are rejected under 35 U.S.C. 103 as being unpatentable over Rostoker et al. (US 5808330; hereinafter ‘Rostoker’) in view of Yi et al. (US 9728474; hereinafter ‘Yi’), Qian et al. (US 2015/0349004; hereinafter ‘Qian’), Kuo (US 2010/0140749), and Lin (US 2012/0112322).
Regarding claim 9, Rostoker teaches a semiconductor device (93, FIG. 1, col. 4, lines 31-32), comprising:
a bottom chip (95);
a first chip (logic gate 96 which is the larger triangular-shaped megafunction cell 207, FIGS. 1 and 19, col. 4, line 41, col. 24, lines 64-65; hereinafter referred to as ‘FCRostoker’), bonded over and electrically connected to the bottom chip (terminal 98 providing interconnections between 95 and 96, col. 4, lines 44-45); and
a second chip (96 which is the larger diamond-shaped megafunction cell, FIGS. 1 and 18, col. 4, line 41, col. 24, lines 62-63; hereinafter referred to as ‘SCRostoker’), disposed at a same level to the first chip (SCRostoker disposed at a same level to FCRostoker), bonded over and electrically connected to the bottom chip (98 providing interconnections between 95 and 96),
wherein the second chip includes a corner having an interior angle less than 90 degrees from a top view (interior angle of SCRostoker is 60 degree, FIG. 18), the first chip includes a first number of sides from the top view (FCRostoker has 3 sides), the second chip includes a second number of sides from the top view (SCRostoker has 4 sides), the second number is greater than the first number.
Rostoker does not teach the semiconductor device comprising: the first chip further includes a first seal ring inside the first chip, the second chip further includes a second seal ring inside the second chip.
Yi teaches a semiconductor device (col. 1, lines 10-13) comprising:
the first chip (16, FIG. 1, col. 1, lines 55-56) further includes a first seal ring (113, FIG. 2, col. 5, line 4) inside the first chip and
the second chip (17) further includes a second seal ring (17 includes 113) inside the second chip.
As taught by Yi, one of ordinary skill in the art would utilize and modify the above teaching into Rostoker to obtain and achieve the semiconductor device comprising: the first chip further includes a first seal ring inside the first chip, the second chip further includes a second seal ring inside the second chip as claimed, because applying different seal ring structures within chips to maximize chip area efficiency, while maintaining crack protection, is a logical design adaptation based on functional and layout considerations. Further a change in shape is generally recognized as being within the level of ordinary skill in the art. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Yi in combination with Rostoker due to above reason.
Rostoker in view of Yi does not teach the semiconductor device comprising: the first chip comprising: an insulating layer including a transistor; and an interconnect structure disposed over the insulating layer and including a conductive line and a conductive via electrically connecting to the transistor; and the second chip comprising: an insulating layer including a transistor; and an interconnect structure disposed over the insulating layer and including a conductive line and a conductive via electrically connecting to the transistor; the first chip wherein a top of the first seal ring is substantially coplanar with a top of the interconnect structure of the first chip, the second chip wherein a top of the second seal ring is substantially coplanar with a top of the interconnect structure of the second chip.
Qian teaches a semiconductor device (102, FIG. 1A, [0018])
wherein the first chip (114 of 100’ in FIG. 1A corresponds to 200 shown in FIG. 2, as well as the one die included in 306 in FIG. 3, [0020, 0022]; hereinafter ‘114Qian’) comprising:
an insulating layer (344114 is an oxide deposition) including a transistor (318114, [0024]); and
an interconnect structure (351114, 358114, M1114, M2114, M3114; hereinafter ‘IS114’) disposed over the insulating layer (344114) and including a conductive line (358114, M1114, M2114, M3114) and a conductive via (351114) electrically connecting to the transistor (IS114 electrically connecting to 318114, [0025, 0030]), and
wherein the second chip (115 of 100´; hereinafter ‘115Qian’) comprising:
an insulating layer (344115) including a transistor (318115); and
an interconnect structure (351115, 358115, M1115, M2115, M3115; hereinafter ‘IS115’) disposed over the insulating layer (344115) and including a conductive line (358115, M1115, M2115, M3115) and a conductive via (351115) electrically connecting to the transistor (IS115 electrically connecting to 318115)
the first chip (114Qian) wherein a top of the first seal ring (332114) is substantially coplanar (shown in FIG. 3) with a top of the interconnect structure of the first chip (IS114),
the second chip (115Qian) wherein a top of the second seal ring (332115) is substantially coplanar (shown in FIG. 3) with a top of the interconnect structure of the second chip (IS115).
As taught by Qian, one of ordinary skill in the art would utilize and modify the above teaching into Rostoker in view of Yi to obtain and achieve the semiconductor device comprising: the first chip comprising: an insulating layer including a transistor; and an interconnect structure disposed over the insulating layer and including a conductive line and a conductive via electrically connecting to the transistor; and the second chip comprising: an insulating layer including a transistor; and an interconnect structure disposed over the insulating layer and including a conductive line and a conductive via electrically connecting to the transistor; the first chip wherein a top of the first seal ring is substantially coplanar with a top of the interconnect structure of the first chip, the second chip wherein a top of the second seal ring is substantially coplanar with a top of the interconnect structure of the second chip as claimed, because each chip contains its own transistor structures, insulating layers, interconnect structure, and conductive path; therefore, providing a seal ring around such a chip necessarily performs the protective function for the internal active devices [0021, 0028].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Qian in combination with Rostoker in view of Yi due to above reason.
Rostoker in view of Yi and Qian does not teach that each chip includes at least one TSV disposed in the insulating layer and over the insulating layer, wherein a top of the TSV is substantially coplanar with a top of the corresponding seal ring, and wherein the transistor, the TSV and the interconnect structure are surrounded by the corresponding seal ring.
Kuo teaches a semiconductor device (3D package structure, FIG. 1, [0007]) comprising a chip (2, [0009]) includes at least one TSV (34, FIG. 4, [0026]) disposed in the insulating layer (insulating structures disposed above the circuit area 331 and between conductive features within the metal interconnect layers 33, FIG. 4, [0024]; hereinafter ‘IL’) and over the insulating layer (IL), wherein the transistor (transistor, [0025]; hereinafter ‘Tr’), the TSV (34) and the interconnect structure (portions of connecting circuit 333 coupled to 331, FIG. 4, [0024]; hereinafter ‘IS’) are surrounded by the corresponding seal ring (a shelter structure 332, which is disposed on a right side of the chip, disposed on the periphery of 331 including Tr and on the periphery of 34 and IS, as shown in FIG. 4, wherein FIGS. 6-11 further illustrate the surrounding 332, [0025, 0028]).
As taught by Kuo, one of ordinary skill in the art would utilize and modify the above teaching into Rostoker in view of Yi and Qian to obtain and achieve the semiconductor device comprising a chip includes at least one TSV disposed in the insulating layer and over the insulating layer, wherein the transistor, the TSV and the interconnect structure are surrounded by the corresponding seal ring as claimed, because surrounding the transistor, TSV, and interconnect structure with the seal ring reduces electromagnetic interference (EMI) generated by current transmitted through the TSV and interconnect structure, thereby protecting adjacent circuit structures and improving device reliability [0013, 0015].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Kuo in combination with Rostoker in view of Yi and Qian due to above reason.
Rostoker in view of Yi, Qian, and Kuo does not teach that a top of the TSV is substantially coplanar with a top of the corresponding seal ring.
Lin teaches a semiconductor device (50, FIG. 6, [0026]) wherein a top of the TSV is substantially coplanar with a top of the seal ring (a top of the TSV 125 is coplanar with a top of seal ring 120 by a CMP process, [0016, 0022]).
As taught by Lin one of ordinary skill in the art would utilize and modify the above teaching into Rostoker in view of Yi, Qian, and Kuo to obtain and achieve the semiconductor device wherein a top of the TSV is substantially coplanar with a top of the seal ring as claimed, because it provides a substantially flat surface suitable for subsequent fabrication and bonding processes [0026].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Lin in combination with Rostoker in view of Yi, Qian, and Kuo due to above reason.
Regarding claim 11, Rostoker in view of Yi, Qian, Kuo, and Lin teaches the semiconductor device of claim 9, wherein the second chip has a substantially L-shaped, U-shaped, star-shaped, cross-shaped, lightning-shaped, diamond, kite, chamfered, trapezoidal, parallelogrammatic, triangular, pentagonal, hexagonal, heptagonal or octagonal profile from the top view (Rostoker: SCRostoker has cross-shaped, diamond, kite, chamfered, trapezoidal, parallelogrammatic, triangular, hexagonal, FIG. 91).
Regarding claim 12, Rostoker in view of Yi, Qian, Kuo, and Lin teaches the semiconductor device of claim 9, but Rostoker in view of Qian, Kuo, and Lin does not teach the semiconductor device wherein the first seal ring includes at least two turning points near the corner.
Yi teaches the semiconductor device wherein the first seal ring includes at least two turning points near the corner (133 includes at least two points near the corner, FIG. 2).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Yi to obtain and achieve the semiconductor device wherein the first seal ring includes at least two turning points near the corner as claimed, because a change in shape is generally recognized as being within the level of ordinary skill in the art. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Regarding claim 13, Rostoker in view of Yi, Qian, Kuo, and Lin teaches the semiconductor device of claim 9, wherein the corner of the second chip has a plurality of continuous first polylines (Rostoker: SCRostoker has continuous polylines, FIG. 91).
Regarding claim 14, Rostoker in view of Yi, Qian, Kuo, and Lin teaches the semiconductor device of claim 13, wherein the corner has a substantially rounded profile from the top view (Rostoker: SCRostoker is made of an irregular block 4029, which has a substantially rounded profile, FIG. 91).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable Rostoker (US 5808330) in view of Yi (US 9728474), Qian (US 2015/0349004), Lin (US 2012/0112322), and Kuo (US 2010/0140749), and further in view of Mariani (US 2015/0069576).
Regarding claim 10, Rostoker in view of Yi, Qian, Kuo, and Lin teaches the semiconductor device of claim 9, wherein the corner of the second chip includes a vertex (Rostoker: SC includes a vertex, FIG. 18).
Rostoker in view of Yi, Qian, Kuo, and Lin does not teach the semiconductor device wherein the vertex is away from an intersection point of extension lines of two adjacent edges corresponding to the corner by at least 1 micrometer.
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Mariani teaches a semiconductor device wherein the vertex (a buffer region, see the annotated FIG. 1D; hereinafter referred to as ‘BRMariani’) is away from an intersection point of extension lines of two adjacent edges corresponding to the corner by at least 1 micrometer (the distant is 8.75 μm when the second width w2 is 17.5 μm, [0047]).
As taught by Mariani, one of ordinary skill in the art would utilize and modify the above teaching into Rostoker in view of Yi, Qian, Kuo, and Lin to obtain and achieve the semiconductor device wherein the vertex is away from an intersection point of extension lines of two adjacent edges corresponding to the corner by at least 1 micrometer as claimed, because rounding the corners of the semiconductor chip reduces the concentration of stress at the edges or corners [0059-0060]. Further a change in shape is generally recognized as being within the level of ordinary skill in the art. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Mariani in combination with Rostoker in view of Yi, Qian, Kuo, and Lin due to above reason.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable Rostoker (US 5808330) in view of Yi (US 9728474), Qian (US 2015/0349004), Kuo (US 2010/0140749), and Lin (US 2012/0112322), and further in view of Chien et al. (US 2014/0264710; hereinafter ‘Chien’) and Yamada (US 2019/0051620).
Regarding claim 15, Rostoker in view of Yi, Qian, Kuo, and Lin teaches the semiconductor device of claim 13, does not teach the semiconductor device wherein the second seal ring has a plurality of continuous second polylines conformal to the plurality of continuous first polylines.
Chien teaches a semiconductor device (FIG. 1, [0008]) wherein the second seal ring (10, [0014]) has a plurality of continuous second polylines (10 has multiple continuous line segments, Fig. 3C, [0025-0026]).
As taught by Chine, one of ordinary skill in the art would utilize and modify the above teaching into Rostoker in view of Yi, Qian, Kuo, and Lin to obtain and achieve the semiconductor device wherein the second seal ring has a plurality of continuous second polylines as claimed, because multiple connected line segments, rather than a single right-angle corner, significantly reduce stress concertation at the sear ring corner [0005, 0015]. Further a change in shape is generally recognized as being within the level of ordinary skill in the art. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Chine in combination with Rostoker in view of Yi, Qian, Kuo, and Lin due to above reason.
Rostoker in view of Yi, Qian, Kuo, Lin, and Chien does not teach the semiconductor device wherein the seal ring has a corner that is conformal to the corner outline of the corresponding chip.
Yamada teaches a semiconductor device (FIG. 16, [0256]) wherein the seal ring (3) has a corner that is conformal (shown in FIG. 16) to the corner outline of the corresponding chip (the chip defined along the scribe line corresponding to 1, [0092]).
As taught by Yamada, one of ordinary skill in the art would utilize and modify the above teaching into Rostoker in view of Yi, Qian, Kuo, Lin, and Chien to obtain and achieve the semiconductor device wherein the seal ring has a corner that is conformal to the corner outline of the corresponding chip as claimed, because it enhances peripheral sealing uniformity and mitigates corner-induced stress concentration and crack propagation, and avoids local gaps at the corner region [0264, 0266].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Yamada in combination with Rostoker in view of Yi, Qian, Kuo, Lin, and Chien due to above reason.
Claims 21-25 are rejected under 35 U.S.C. 103 as being unpatentable over Qian (US 2015/0349004) in view of Yamada (US 2019/0051620), Kuo (US 2010/0140749), and Lin (US 2012/0112322).
Regarding claim 21, Qian teaches a semiconductor device (102, FIG. 1A, [0018]), comprising:
a first chip (100 in FIG. 1A corresponds to 304 in FIG. 3, [0022]); and
a second chip (114 of 100’ in FIG. 1A corresponds to 200 shown in FIG. 2, as well as the one die included in 306 in FIG. 3, [0020, 0022]; hereinafter ‘114Qian’), bonded over and electrically connected to the first chip (shown in FIG. 3), wherein from a top perspective of the semiconductor device (shown in FIG. 2), the second chip (114Qian) includes a first seal ring (260114), extending continuously along a periphery of the second chip within the second chip (shown in FIG. 2),
wherein the second chip (114Qian) further comprises:
an insulating layer (344114 is an oxide deposition) including a transistor (318114, [0024]); and
an interconnect structure (351114, 358114, M1114, M2114, M3114; hereinafter ‘IS114’) disposed over the insulating layer (344114) and including a conductive line (358114, M1114, M2114, M3114) and a conductive via (351114) electrically connecting to the transistor (IS114 electrically connecting to 318114, [0025, 0030]).
Qian does not teach the semiconductor device wherein the first seal ring has at least two turning points near a corner of the second chip.
Yamada teaches a semiconductor device (FIG. 16, [0256]) wherein the first seal ring has at least two turning points (shown in FIG. 16) near a corner of the second chip (the chip defined along the scribe line corresponding to 1, [0092]; hereinafter ‘SCYamada’).
As taught by Yamada, one of ordinary skill in the art would utilize and modify the above teaching into Kuo to obtain and achieve the semiconductor device wherein the first seal ring has at least two turning points near a corner of the second chip as claimed, because a chamfered corner having a turning points locally reduces stress concentration and suppresses straight-line crack propagation at the chip corner, thereby improving the protection of internal structures [0255].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Yamada in combination with Qian due to above reason.
Qian in view of Yamada does not teach the semiconductor device wherein the second chip includes at least one through silicon via (TSV) disposed in the insulating layer and over the insulating layer, and the transistor, the TSV, and the interconnect structure are surrounded by the first seal ring.
Kuo teaches a semiconductor device (3D package structure, FIG. 1, [0007]) wherein the second chip (2, [0009]) includes at least one TSV (34, FIG. 4, [0026]) disposed in the insulating layer (insulating structures disposed above the circuit area 331 and between conductive features within the metal interconnect layers 33, FIG. 4, [0024]; hereinafter ‘IL’) and over the insulating layer (IL), and the transistor (transistor, [0025]; hereinafter ‘Tr’), the TSV (34) and the interconnect structure (portions of connecting circuit 333 coupled to 331, FIG. 4, [0024]; hereinafter ‘IS’) are surrounded by the first seal ring (a shelter structure 332, which is disposed on a right side of the chip, disposed on the periphery of 331 including Tr and on the periphery of 34 and IS, as shown in FIG. 4, wherein FIGS. 6-11 further illustrate the surrounding 332, [0025, 0028]).
As taught by Kuo, one of ordinary skill in the art would utilize and modify the above teaching into Qian in view of Yamada to obtain and achieve the semiconductor device wherein the second chip includes at least one TSV disposed in the insulating layer and over the insulating layer, and the transistor, the TSV, and the interconnect structure are surrounded by the first seal ring as claimed, because surrounding the transistor, TSV, and interconnect structure with the seal ring reduces electromagnetic interference (EMI) generated by current transmitted through the TSV and interconnect structure, thereby protecting adjacent circuit structures and improving device reliability [0013, 0015].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Kuo in combination with Qian in view of Yamada due to above reason.
Qian in view of Yamada, and Kuo does not teach that a top of the TSV is substantially coplanar with a top of the first seal ring.
Lin teaches a semiconductor device (50, FIG. 6, [0026]) wherein a top of the TSV is substantially coplanar with a top of the first seal ring (a top of the TSV 125 is coplanar with a top of seal ring 120 by a CMP process, [0016, 0022]).
As taught by Lin one of ordinary skill in the art would utilize and modify the above teaching into Qian in view of Yamada, and Kuo to obtain and achieve the semiconductor device wherein a top of the TSV is substantially coplanar with a top of the first seal ring as claimed, because it provides a substantially flat surface suitable for subsequent fabrication and bonding processes [0026].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Lin in combination with Qian in view of Yamada, and Kuo due to above reason.
Regarding claim 22, Qian in view of Yamada, Kuo, and Lin teaches the semiconductor device of claim 21, further comprising a third chip (Qian: 115 of 100’ in FIG. 1A corresponds to 200 shown in FIG. 2, as well as the one die included in 306 in FIG. 3, [0020, 0022]; hereinafter ‘115Qian’), bonded over the first chip, electrically connected to the first chip (shown in FIG. 3) and disposed adjacent to the second chip (115Qian disposed adjacent to 114Qian), wherein from the top perspective (shown in FIG. 2), the third chip (115Qian) includes a second seal ring (260115) extending continuously along a periphery of the third chip within the third chip (shown in FIG. 2).
Regarding claim 23, Qian in view of Yamada, Kuo, and Lin teaches the semiconductor device of claim 22, wherein the first seal ring includes a first number of edges from the top perspective (Qian: 260114 has 4 sides, FIG. 2), the second seal ring includes a second number of edges from the top perspective (260115 has 4 sides), and the second number is equal to or different from the first number (first number and second number are both 4).
Regarding claim 24, Qian in view of Yamada, Kuo, and Lin teaches the semiconductor device of claim 23, wherein the first number is equal to or greater than four (Qian: first number is 4, FIG. 2).
Regarding claim 25, Qian in view of Yamada, Kuo, and Lin teaches the semiconductor device of claim 21, but Qian in view of Kuo, and Lin does not teach the semiconductor device wherein the second chip includes a corner having an interior angle greater than 90 degrees from the top perspective.
Yamada teaches the semiconductor device wherein the second chip (SCYamada, FIG. 16) includes a corner having an interior angle greater than 90 degrees from the top perspective (the corner angle greater than 90 degrees).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Yamada to obtain and achieve the semiconductor device wherein the second chip includes a corner having an interior angle greater than 90 degrees from the top perspective as claimed, because a chamfered corner having a turning points locally reduces stress concentration and suppresses straight-line crack propagation at the chip corner, thereby improving the protection of internal structures [0255].
Response to Arguments
Applicant's arguments with respect to claims have been considered but are moot in view of the new ground of rejection. Response to arguments on newly added limitations are responded to in the above rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
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/JIYOUNG OH/Examiner, Art Unit 2818
/DUY T NGUYEN/Primary Examiner, Art Unit 2818 5/13/26
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