DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Election/Restrictions Claims 18-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected group, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 12/29/25 . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim (s) 1 , 2, 4-6, 8, 10, 12, 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20210210499 ( Jhorthiraman et al) in view of US 20030017267 (Mukai et al). Concerning claim 1, Jhorthiraman discloses a memory device comprising (Figs. 1 and 4A-4B) : a memory array (Fig. 1) ; and a memory block (103) coupled to the memory array, the memory block comprising: a stairwell (320) including a trench (325) ; and a reflowed doped silicon dioxide film coating (422 +424) the stairwell trench ([0050]) , wherein the reflowed doped silicon dioxide film comprising ([0115], note that the doped silicon dioxide film is annealed and the reflowing occurs during that process) : a liner film (422) formed on the trench of the stairwell of the memory device (Fig. 4B) ; and a doped silicon dioxide film (424) deposited on the liner film (Fig. 4B) , wherein doping of the doped silicon dioxide film is performed during the deposition of the doped silicon dioxide film ([0068]-[0073], note the deposition conditions for the formation of doped silicon dioxide film are disclosed with the dopants being introduced with the forming precursors) . Jhorthiraman does not disclose wherein the reflowed doped silicon dioxide film is formed through a pressurized and steamed anneal performed on the doped silicon dioxide film. However, Mukai discloses a method and apparatus for controlling dopant concentration during borophosphosilicate glass film deposition on a semiconductor wafer to reduce consumption of nitride on the semiconductor wafer (Abstract) . Mukai additionally discloses Typically, a BPSG film is deposited on a semiconductor device/substrate over of a layer/film of silicon nitride (Si.sub.3N.sub.4) which functions as an etch stop or spacer during the manufacture of the integrated circuit. Following deposition, the BPSG film generally undergoes a reflow step with wet (e.g. steam) annealing at a temperature of about 800-900.degree. C. in order to planarize the BPSG layers and to fill in any voids that may be present in the BPSG layer/film ([0007], [0055]-[0058], note that the processing conditions of the steam anneal are disclosed in these paragraphs). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the annealing process of Jhorthiraman to be a steam anneal under the conditions as disclosed by Mukai in order to planarize the BPSG layers and to fill in any voids that may be present . Continuing to claim 2, Jhorthiraman in view of Mukai discloses wherein the liner film includes a silicon nitride ( SiN ) material (Mukai [0007]) . Considering claims 4 and 5, Jhorthiraman in view of Mukai discloses wherein the liner film is to prevent diffusion into the stairwell layer of one or more of dihydrogen, oxygen, boron dopant, or phosphorus dopant and wherein the liner film is to be formed to avoid pinhole abnormalities at a temperature ranging from 500 degrees Celsius to 700 degrees Celsius ( Mukai [0007]), Functional language may also be employed to limit the claims without using the means-plus-function format. See, e.g., K-2 Corp. v. Salomon S.A., 191 F.3d 1356, 1363, 52 USPQ2d 1001, 1005 (Fed. Cir. 1999). Unlike means-plus-function claim language that applies only to purely functional limitations, Phillips v. AWH Corp., 415 F.3d 1303, 1311, 75 USPQ2d 1321, 1324 (Fed. Cir. 2005) ( en banc) ("Means-plus-function claiming applies only to purely functional limitations that do not provide the structure that performs the recited function."), functional claiming often involves the recitation of some structure followed by its function. For example, in In re Schreiber, the claims were directed to a conical spout (the structure) that "allow[ed] several kernels of popped popcorn to pass through at the same time" (the function). In re Schreiber, 128 F.3d 1473, 1478, 44 USPQ2d 1429, 1431 (Fed. Cir. 1997). As noted by the court in Schreiber, "[a] patent applicant is free to recite features of an apparatus either structurally or functionally." Id. A functional limitation must be evaluated and considered, just like any other limitation of the claim, for what it fairly conveys to a person of ordinary skill in the pertinent art in the context in which it is used. A functional limitation is often used in association with an element, ingredient, or step of a process to define a particular capability or purpose that is served by the recited element, ingredient or step. See MPEP 2173.05 (g). It is noted that the claim includes functional language which only states a problem solved or a result obtained . These solved problems/results are obtained by the use of SiN as the liner material which is disclosed by Mukai). Referring to claim 6, Jhorthiraman in view of Mukai discloses wherein the doped silicon dioxide film is doped with 3% to 5% boron or phosphorus ( Jhorthiraman [0115] and Mukai [0020]). Regarding claim 8, Jhorthiraman in view of Mukai discloses wherein the doped silicon dioxide film has a conformal deposition step coverage of greater than 50 percent ( Jhorthiraman [0028] and [0112] Table 1). Pertaining to claim 10, Jhorthiraman in view of Mukai wherein the doped silicon dioxide film is deposited via a plasma enhanced chemical vapor deposition reactor at a temperature from 300 degrees Celsius to 550 degrees Celsius ( Jhorthiraman [0065]) . As to claim 12, Jhorthiraman in view of Mukai discloses wherein a temperature of the pressurized and steamed anneal ranges from 650 degrees Celsius to 750 degrees Celsius (Mukai [0055]) . Concerning claim 14, Jhorthiraman discloses a system comprising: a memory controller (112) ; and a multi-deck non-volatile memory structure coupled to the memory controller (Fig. 1) , the multi-deck non-volatile memory structure comprising: a memory array (Fig. 1) ; and a memory block (103) coupled to the memory array, the memory block comprising: a stairwell (320) including a trench (325) ; and a reflowed doped silicon dioxide film coating (422 +424) the stairwell trench ([0050]) , wherein the reflowed doped silicon dioxide film comprising ([0115], note that the doped silicon dioxide film is annealed and the reflowing occurs during that process) : a liner film (422) formed on the trench of the stairwell of the memory device (Fig. 4B) ; and a doped silicon dioxide film (424) deposited on the liner film (Fig. 4B) , wherein doping of the doped silicon dioxide film is performed during the deposition of the doped silicon dioxide film ([0068]-[0073], note the deposition conditions for the formation of doped silicon dioxide film are disclosed with the dopants being introduced with the forming precursors). Jhorthiraman does not disclose wherein the reflowed doped silicon dioxide film is formed through a pressurized and steamed anneal performed on the doped silicon dioxide film. However, Mukai discloses a method and apparatus for controlling dopant concentration during borophosphosilicate glass film deposition on a semiconductor wafer to reduce consumption of nitride on the semiconductor wafer (Abstract). Mukai additionally discloses Typically, a BPSG film is deposited on a semiconductor device/substrate over of a layer/film of silicon nitride (Si.sub.3N.sub.4) which functions as an etch stop or spacer during the manufacture of the integrated circuit. Following deposition, the BPSG film generally undergoes a reflow step with wet (e.g. steam) annealing at a temperature of about 800-900.degree. C. in order to planarize the BPSG layers and to fill in any voids that may be present in the BPSG layer/film ([0007], [0055]-[0058], note that the processing conditions of the steam anneal are disclosed in these paragraphs). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the annealing process of Jhorthiraman to be a steam anneal under the conditions as disclosed by Mukai in order to planarize the BPSG layers and to fill in any voids that may be present. Claim(s) 3, 7, 9, 15 , and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20210210499 ( Jhorthiraman et al) in view of US 20030017267 (Mukai et al) as applied to claim s 1 and 14 above, and further in view of US 20220068636 ( Bayati et al) . Continuing to claims 3, 7, 9, 15, and 16, Jhorthiraman in view of Mukai discloses forming the liner film, wherein the liner film is to prevent diffusion into the stairwell layer of one or more of dihydrogen, oxygen, boron dopant, or phosphorus dopant, and wherein the liner film is to be formed to avoid pinhole abnormalities at a temperature ranging from 500 degrees Celsius to 700 degrees Celsius (Mukai [0007]), Functional language may also be employed to limit the claims without using the means-plus-function format. See, e.g., K-2 Corp. v. Salomon S.A., 191 F.3d 1356, 1363, 52 USPQ2d 1001, 1005 (Fed. Cir. 1999). Unlike means-plus-function claim language that applies only to purely functional limitations, Phillips v. AWH Corp., 415 F.3d 1303, 1311, 75 USPQ2d 1321, 1324 (Fed. Cir. 2005) ( en banc) ("Means-plus-function claiming applies only to purely functional limitations that do not provide the structure that performs the recited function."), functional claiming often involves the recitation of some structure followed by its function. For example, in In re Schreiber, the claims were directed to a conical spout (the structure) that "allow[ed] several kernels of popped popcorn to pass through at the same time" (the function). In re Schreiber, 128 F.3d 1473, 1478, 44 USPQ2d 1429, 1431 (Fed. Cir. 1997). As noted by the court in Schreiber, "[a] patent applicant is free to recite features of an apparatus either structurally or functionally." Id. A functional limitation must be evaluated and considered, just like any other limitation of the claim, for what it fairly conveys to a person of ordinary skill in the pertinent art in the context in which it is used. A functional limitation is often used in association with an element, ingredient, or step of a process to define a particular capability or purpose that is served by the recited element, ingredient or step. See MPEP 2173.05 (g). It is noted that the claim includes functional language which only states a problem solved or a result obtained . These solved problems/results are obtained by the use of SiN as the liner material which is disclosed by Mukai) , wherein the doped silicon dioxide film is doped with 3% to 5% boron or phosphorus ( Jhorthiraman [0115] and Mukai [0020]) , wherein the doped silicon dioxide film has a conformal deposition step coverage of greater than 50 percent ( Jhorthiraman [0028] and [0112] Table 1) , and wherein the doped silicon dioxide film is deposited via a plasma enhanced chemical vapor deposition reactor at a temperature from 300 degrees Celsius to 550 degrees Celsius ( Jhorthiraman [0065]) . Jhorthiraman in view of Mukai does not disclose wherein the liner film has a thickness ranging from 100 angstroms to 3000 angstroms, wherein the doped silicon dioxide film has a thickness ranging from 5 micrometers to 10 micrometers, wherein the doped silicon dioxide film has a deposition rate greater than 1 micrometer per minute . However, Bayati discloses i n 3D NAND, for example, thick silicon oxide films are used for isolation purposes ([0017]) . T he doped silicon oxide film may be deposited by a chemical vapor deposition (CVD) process using precursors for silicon oxide and a dopant selected from the group consisting of B, P, Ge, and combinations thereof. The silicon oxide precursor may be tetraethyl orthosilicate (TEOS). The CVD process may be plasma enhanced (PECVD) ([0021]). A sufficiently thick low stress film with high thermal stability, low moisture absorption and excellent dielectric properties, such as low dielectric constant and high breakdown voltage, would be desirable for large area gap fill and other applications in current and developing semiconductor processing techniques. For large area gap fill and other applications, such a film should allow low cost processing and avoid problems depositing to aggregate thicknesses exceeding 5 micrometers (microns ( µ m)), such as up to 10 µ m or up to 20 µ m, or more. Thick films can be deposited at thicknesses up to 20 µ m or more by a single-pass deposition. The doped silicon oxide film may be deposited at a high rate of at least 1 µ m per minute ([0018]). a method of depositing and annealing a thick doped silicon oxide film, such as in large area gap fill applications. The method involves depositing on a patterned semiconductor substrate a doped silicon oxide film, the film having a thickness of at least 5 µ m, for example up to 10 µ m, or up to 20 µ m, or more. Thick films can be deposited at thicknesses up to 20 µ m or more by a single-pass deposition. The doped silicon oxide film may be deposited at a high rate of at least 1 µ m per minute with the doped silicon oxide film deposition preceded by deposition of an undoped silicon oxide liner, for example having a thickness of about 200-2000 Å ([0020]) . The composition and processing conditions of the doped silicon oxide film may be tailored so that the film exhibits substantially zero as-deposited stress, substantially zero stress shift post-anneal, and substantially zero shrinkage post-anneal. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the invention of Jhorthiraman in view of Mukai such that the liner film has a thickness ranging from 100 angstroms to 3000 angstroms, wherein the doped silicon dioxide film has a thickness ranging from 5 micrometers to 10 micrometers, wherein the doped silicon dioxide film has a deposition rate greater than 1 micrometer per minute as disclosed by Bayati in order to obtain a sufficiently thick low stress film with high thermal stability, low moisture absorption with excellent dielectric properties, such as low dielectric constant and high breakdown voltage, that is desirable for large area gap fill and other applications in current and developing semiconductor processing techniques. Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20210210499 ( Jhorthiraman et al) in view of US 20030017267 (Mukai et al) as applied to claim s 1 and 14 above, and further in view of US 20200006063 (Chen et al) . Considering claim 11, Jhorthiraman in view of Mukai discloses performing a pressurized steam anneal. Jhorthiraman in view of Mukai does not disclose wherein a pressure ranges from 20 atmospheres to 80 atmospheres during the pressurized and steamed anneal. However, Chen discloses a method utilizing a high pressure wet (steam) anneal (55) (designated as “HPO” in FIG. 9) was performed using an annealing pressure of 20 ATMs on an insulation layer (54) which may be an oxide, such as silicon oxide, a nitride, the like, or a combination thereof, and may be formed by a high density plasma chemical vapor deposition (HDP-CVD), a flowable CVD (FCVD), or a combination thereof. ([0037], [0043]-[0045] and Fig. 9). C ompared to an atmospheric pressure anneal process, high pressure anneal process may achieve better results. H igh pressure anneal process result in the same, similar, or better results as the atmospheric anneal process using a lower annealing temperature. As such, a thermal budget improvement may be realized. Additionally, undesirably high temperatures that may degrade FinFET device may be reduced or avoided. Further, the lower temperature processing may enable insulation material to have a high density. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the anneal of Jhorthiraman in view of Mukai to be a high pressure wet (steam) anneal as disclosed by Chen in order to achieve similar results at lower temperatures thus avoiding degrading FET devices and enabling insulation materials with a high density. Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20210210499 ( Jhorthiraman et al) in view of US 20030017267 (Mukai et al) as applied to claim 13 above, and further in view of US 20090208880 ( Nemani et al) . Referring to claim 13, Jhorthiraman in view of Mukai discloses performing a pressurized steam anneal. Jhorthiraman in view of Mukai does not disclose wherein the pressurized and steamed anneal includes utilization of water, oxygen, nitrogen, and dihydrogen. Nemani discloses the materials used for a steam anneal. The anneal may occur in the present of an inert gas of in an atmosphere including N.sub.2, Ar , O.sub.2, H.sub.2O, NH.sub.3, N.sub.2/H.sub.2, and N.sub.2O. ([0009]) . The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945) . See MPEP 2144.07. Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to perform the anneal with the utilization of water, oxygen, nitrogen, and dihydrogen because these are known atmospheres that are suitable for steam anneal treatments. Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20210210499 ( Jhorthiraman et al) in view of US 20030017267 (Mukai et al) as applied to claim 14 above, and further in view of US 20200006063 (Chen et al) and US 20090208880 ( Nemani et al) . Regarding claims 17, Jhorthiraman in view of Mukai discloses wherein a temperature of the pressurized and steamed anneal ranges from 650 degrees Celsius to 750 degrees Celsius (Mukai [0055]) . Jhorthiraman in view of Mukai does not disclose wherein a pressure ranges from 20 atmospheres to 80 atmospheres during the pressurized and steamed anneal and wherein the pressurized and steamed anneal includes utilization of water, oxygen, nitrogen, and dihydrogen. However, Chen discloses a method utilizing a high pressure wet (steam) anneal (55) (designated as “HPO” in FIG. 9) was performed using an annealing pressure of 20 ATMs on an insulation layer (54) which may be an oxide, such as silicon oxide, a nitride, the like, or a combination thereof, and may be formed by a high density plasma chemical vapor deposition (HDP-CVD), a flowable CVD (FCVD), or a combination thereof. ([0037], [0043]-[0045] and Fig. 9). Compared to an atmospheric pressure anneal process, high pressure anneal process may achieve better results. High pressure anneal process result in the same, similar, or better results as the atmospheric anneal process using a lower annealing temperature. As such, a thermal budget improvement may be realized. Additionally, undesirably high temperatures that may degrade FinFET device may be reduced or avoided. Further, the lower temperature processing may enable insulation material to have a high density. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the anneal of Jhorthiraman in view of Mukai to be a high pressure wet (steam) anneal as disclosed by Chen in order to achieve similar results at lower temperatures thus avoiding degrading FET devices and enabling insulation materials with a high density. Additionally, Nemani discloses the materials used for a steam anneal. The anneal may occur in the present of an inert gas of in an atmosphere including N.sub.2, Ar , O.sub.2, H.sub.2O, NH.sub.3, N.sub.2/H.sub.2, and N.sub.2O. ([0009]). The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). See MPEP 2144.07. Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to perform the anneal with the utilization of water, oxygen, nitrogen, and dihydrogen because these are known atmospheres that are suitable for steam anneal treatments. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 20040079118 discloses formation of PECVD doped silicate glasses (Abstract) . Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT VALERIE N NEWTON whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)270-5015 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT M-F 8-5 . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, FILLIN "SPE Name?" \* MERGEFORMAT CHAD DICKE can be reached at FILLIN "SPE Phone?" \* MERGEFORMAT (571) 270-7996 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /VALERIE N NEWTON/ Examiner, Art Unit 2897 03/30/26 /CHAD M DICKE/ Supervisory Patent Examiner, Art Unit 2897