Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Applicant’s amendments have overcome the Examiner’s claim objections.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, and 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Fujiwara et al US 20210366915 A1 in view of Mojumder et al US 20230284427 A1 and Nii US 20110157965 A1. Fujiwara et al and Mojumder et al will be referenced to as Fujiwara and Mojumder henceforth.
Regarding Claim 1,
Fujiwara teaches:
“A method, comprising (FIG.7) generating a design layout comprising a first cell (second bit cell, [0054]) the first cell comprising a first (polysilicon structures 462, [0041]) gate structure, a second (polysilicon structure 464) gate structure, a third (polysilicon structure 466) gate structure, and a fourth gate structure (polysilicon structure 468) parallel to each other (FIG.7) and extending in a first direction (the first direction is vertical), wherein the first cell
a data storage element arranged in a device layer (annotated FIG. 6 #1) and comprising a first data node (node Q, [0024-0025], Q is controlled by PG0.) and a second data node (node Qbar, Qbar is controlled by PQ1.), wherein the data storage element further comprises four transistors (transistors PU0, PU1, PD0, PD1) associated with the second structure and the third gate structure (The four transistors lie on 464 and 466.);
a first access transistor (pass gate transistor PG0) and a second access transistor (pass gate transistor PG1) arranged in the device layer (annotated FIG. 6 #1) and coupled to the first data node and the second data node,
respectively ([0026]: Qbar is controlled by PG1);
a first conductive line (annotated FIG. 7 #1) configured to receive a word line select signal ([0046], FIG. 7: WL1 is electrically connected to the first conductive line by via 485.) extending in a second direction, (the second direction is horizontal) and coupled to gate structures of the first access transistor and the second access transistor,
respectively (annotated FIG. 7 #1), the first conductive line overlying a first cell boundary of the first cell, the first cell boundary extending in the second direction (annotated FIG. 7 #3);
a second conductive line (BL, [0022]) extending in the second direction and coupled to a source/drain region of the first access transistor (S/D contacts, 402, [0038], annotated FIG. 7 #1);
a third conductive line (BLB) extending in the second direction (annotated FIG. 7 #1) and transistor (S/D contacts 406, [0038], annotated FIG. 7 #1)
and
a fourth conductive line (Fujiwara: VSS, [0037], FIG.7) configured to receive a first supply voltage (Fujiwara: VSS is at a reference voltage.) and overlying a second cell boundary of the first cell (annotated FIG. 7 #3), the second cell boundary extending in the second direction (annotated FIG. 7 #3),”
Fujiwara doesn’t substantially teach:
“receiving design data of a memory device according to the design data,”
However, Mojumder teaches:
“receiving design data of a memory device (Mojumder: [0057-0064], FIG. 10: design data stored in computer files may be used with fabrication handlers to make the device.) according to the design data (Mojumder: [0057-0064]),”
Neither Fujiwara or Mojumder teaches:
“the second conductive line and the third conductive line being arranged between the first conductive line and the fourth conductive line along the first direction.”
However, Nii teaches:
“the second conductive line and the third conductive line being arranged between the first conductive line and the fourth conductive line along the first direction (Nii: [0085], [0165], annotated FIG. 42 #1).””
It would have been obvious to one with ordinary skill in the art before the effective filing
date of the invention to recognize that the device of Fujiwara is modifiable in view of Mojumder and Nii.
This is because using design data from a computer to manufacture an SRAM device is a method of manufacture as is known by one of ordinary skill in the art (Mojumder: [0057]).
Further, this is because Nii teaches that by arranging bit lines complementary to each other side by side, it’s possible to reduce the interference between ports. One of ordinary skill in the art would recognize this as an advantage as the electrical interference between ports can cause errors in the access of a memory cells which is undesirable.
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Regarding Claim 2,
Fujiwara/Mojumder/Nii teaches:
“The method of claim 1, (Fujiwara: [0019]: The SRAM architecture is manufactured.).”
Regarding Claim 9,
Fujiwara/Mojumder/Nii teaches:
“The method of claim 1 (Fujiwara: FIG. 7), wherein the data storage element (Fujiwara: S/D contact 472) and a second source/drain region (Fujiwara: S/D contact 476) arranged in the device layer (Fujiwara: annotated FIG. 6B #1) on outer sides of the second gate structure and the third gate structure (Fujiwara: FIG. 7: 464 and 466 lie between the S/D regions. Therefore, the S/D regions are on an outer side of these gate structures.),
wherein the first cell (Fujiwara: annotated FIG. 7 #1) electrically connecting the second gate structure and the second source/drain region (Fujiwara: annotated FIG. 7 #1), and an eighth conductive line (Fujiwara: annotated FIG. 7 #1) electrically connecting the third gate structure and the first source/drain region (Fujiwara: annotated FIG. 7 #1).”
Regarding Claim 10,
Fujiwara/Mojumder/Nii teaches:
“The method of claim 9, wherein the first cell comprises a ninth conductive line configured to receive the first supply voltage and overlying the fourth conductive line (Fujiwara: S/D contact 404, [0061], FIG. 7. 404 is connected to VSS and therefore receives the first supply voltage. Element 404 overlies VSS in a vertical direction. One of ordinary skill in the art would know that S/D contacts are conductive.).”
Claims 3-7 and 11-15 are rejected under 35 U.S.C. 103 as being unpatentable over Fujiwara/Mojumder/Nii as applied to claims 1-2, 9-10 above, and further in view of Augustine US 20230284427 A1. Augustine et al will be referenced to as Augustine henceforth.
Regarding Claim 3,
Fujiwara/Mojumder/Nii teaches:
“The method of claim 1, wherein the first conductive line is arranged in a first layer over the device layer (Fujiwara: FIG. 6: the M1 layer is above the polysilicon layer. The first conductive line, an M1 line, is in the M1 layer.),”
Fujiwara/Mojumder/Nii doesn’t substantially teach:
“and wherein at least one of the second conductive line or the third conductive line is arranged in a second layer below the device layer”
However, Augustine teaches:
“and wherein at least one of the second and the third conductive lines is arranged in a second layer below the device layer (Augustine: FIG. 11A: BL and BLB are on the back of the device.).”
It would have been obvious to one with ordinary skill in the art before the effective filing
date of the invention to recognize that the device of Fujiwara/Mojumder/Nii is modifiable in view of Augustine.
This is because one of ordinary skill in the art would want to move the BL and BLB to the back of a singular cell because there is more space in the back of the cell compared to the device layer allowing for compactification of the device and to provide shielding to the BL and BLB in order to reduce capacitive coupling between them by placing them next to the VCC (Augustine: [0043-0047]).
Regarding Claim 4,
Fujiwara/Mojumder/Nii/Augustine teaches:
“The method of claim 3, wherein the second conductive line and the third conductive line are arranged in the second layer (Augustine: FIG. 11A).”
Regarding Claim 5,
Fujiwara/Mojumder/Nii/Augustine teaches:
“The method of claim 4, wherein the first cell (Fujiwara: power supply VDD, [0024], FIG. 7) different than the first supply voltage ([0024]: VDD has a different supply voltage than VSS. Namely VSS may be at ground and VDD may provide power, which entails a non-reference voltage.), wherein at least one of the fourth conductive line or the fifth conductive line is arranged in the second layer (Augustine: VCC (top), [0053] FIG. 11A: VCC provides a second supply voltage and is located on the backside of the device. Two VCCs are shown in FIG. 11A, one on top ,VCC (top), and one on bottom VCC (bottom). FIG. 11A shows VCC extending both horizontally and vertically.)”
Regarding Claim 6,
Fujiwara/Mojumder/Nii/Augustine teaches:
“The method of claim 5, wherein the second conductive line, the third conductive line, the fourth conductive line or the fifth conductive line are arranged in the second layer (Augustine: FIG. 11A).”
It would have been obvious to one with ordinary skill in the art before the effective filing
date of the invention to recognize that the device of Fujiwara/Mojumder/Nii is modifiable in view of Augustine.
This is because one of ordinary skill in the art would want to place the VSS in the back of the device to further make room on the device layer allowing for more compactification of the device. One of ordinary skill in the art finds compactification advantageous because the more transistors per unit area, the more computationally powerful a device is.
Regarding Claim 7,
Fujiwara/Mojumder/Nii/Augustine teaches:
“The method of claim 5, wherein the first cell (Augustine: VCC (bottom), FIG. 11A ) extending in the second direction in the second layer (Fujiwara: VDD extends in a second direction. Therefore, one of ordinary skill in the art would find it obvious for VCC (bottom) to extend in a second direction.) and configured to receive the second supply voltage (Fujiwara: The fifth and sixth lines are VCC lines.), wherein the fifth conductive line and the sixth conductive line are separated by one of the second conductive line or the third conductive line (Augustine: FIG. 11B: The second and third lines are between the VCC lines.) and the first conductive line overlies the sixth conductive line (Augustine/Fujiwara: Augustine [0047]: VCC is between BL and BLB in order to reduce the capacitive coupling between BL and BLB. Therefore, one of ordinary skill in the art would recognize that VCC would be placed between BL and BLB in Fujiwara upon combination. Because BL and BLB overly the first conductive line and VCC lies between BL and BLB, then VCC overlies the first conductive line.).”
Regarding Claim 11,
Fujiwara/Mojumder/Nii/Augustine teaches:
“A method, comprising:
receiving design data of a memory device (Mojumder: [0057], FIG. 10: design data stored in computer files may be used with fabrication handlers to make the device.); and
generating a design layout comprising a first cell (Fujiwara: second bit cell, [0054]) according to the design data (Mojumder: [0057]), wherein the first cell comprises:
a data storage element arranged in a device layer (Fujiwara: annotated FIG. 6 #1.) and comprising a first data node (Fujiwara: node Q, [0024-0025], Q is controlled by PG0.) and a second data node (Fujiwara: Qbar, Qbar is controlled by PG1.);
a first access transistor (Fujiwara: pass gate transistor PG0) and a second access transistor (Fujiwara: pass gate transistor PG1) arranged in the device layer (Fujiwara: annotated FIG. 6 #1) and coupled to the first data node and the second data node,
respectively (Fujiwara: [0026]: Qbar is controlled by PG1.);
a first conductive line (Fujiwara: annotated FIG. 7 #1) configured to receive a word line select signal ([0046], FIG. 7: WL1 is electrically connected to the first conductive line by via 485.) and extending in a column direction (Fujiwara: the column direction is horizontal.) in a first layer over the device layer (Fujiwara: annotated FIG. 6 #1: the M1 layer is above the polysilicon layer. The first conductive line is an M1 line in the M1 layer.) and electrically connected to gate structures of the first access transistor and the second access transistor (Fujiwara: annotated FIG. 7 #1);
a second conductive line (Fujiwara: BL, [0022]) configured to receive a first bitline select signal (Fujiwara: BL is a bit line and therefore receives a bit line select signal.) and extending in the column direction (Fujiwara: FIG. 7: BL extends horizontally) and electrically connected to a source/drain region of the first access transistor (Fujiwara: S/D contacts 402, [0038], annotated FIG. 7 #1) and a third conductive line (Fujiwara: BLB) configured to receive a second bitline select signal (Fujiwara: BLB is a complementary bit line and therefore receives a bit line select signal.) and extending in the column direction (Fujiwara: annotated FIG. 7 #1) and electrically connected to a source/drain region of the second access transistor (Fujiwara: S/D contacts 406, [0038], annotated FIG. 7 #1), the first bitline select signal being different than the second bitline select signal (Fujiwara: [0044], [0048], FIG. 7, FIG. 8: BL and BLB are not directly electrically connected and therefore supply separate signals.),
wherein the third conductive line is arranged in a second layer on a second side of the device layer opposite to the first layer (Augustine: FIG. 11A: BL and BLB are on the back of the device.).”
Regarding Claim 12,
Fujiwara/Mojumder/Nii/Augustine teaches:
“The method of claim 11, wherein the design layout defines a gate pitch as a pitch between adjacent gate structures extending in a row direction (Fujiwara: the row direction is vertical.), wherein the first cell has a cell height of four times the gate pitch measured in the column direction (Fujiwara: annotated FIG. 7 #2: The cell height is 4 times that of the gate pitch. The cell height is measured from the center of one source/drain region to another as is done by the Applicant.).
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Regarding Claim 13,
Fujiwara/Mojumder/Nii/Augustine teaches:
“The method of claim 11, wherein the first cell (Fujiwara: WL1 FIGs. 6-7, annotated FIG. 6 #1: WL1 is an M2 line and extends vertically) and electrically coupled to the first conductive line (Fujiwara: [0046], WL1 is electrically coupled to the first conductive line at via 485).”
Regarding Claim 14,
Fujiwara/Mojumder/Nii/Augustine teaches:
“The method of claim 13 (Fujiwara: FIG. 7), (Fujiwara: first bit cell 410, [0047]), the second cell abutted to the first cell (Fujiwara: FIG. 7), wherein the second cell comprises:
a fifth conductive line extending in the second layer in the column direction (Fujiwara: VSS, [0037], FIG.7) and configured to control access transistors of the second cell (Fujiwara: VSS controls the power to the transistors of the device by providing a reference voltage.); and
a sixth conductive line extending in the third layer in the row direction (Fujiwara: WL0, FIG. 7), wherein both the fourth conductive line and the sixth conductive line extends across the first and the second cells (Fujiwara: FIG. 7).”
Regarding Claim 15,
Fujiwara/Mojumder/Nii/Augustine teaches:
“The method of claim 14, wherein the first cell and the second cell are symmetrically arranged about a boundary line between the first cell and the second cell (Fujiwara: FIG. 7).”
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Fujiwara/Mojumder/Nii/Augustine as applied to claims 3-7 and 11-15 above, and further in view of Nii #2 US 20180068708 A1.
Regarding Claim 8,
Fujiwara/Mojumder/Nii/Augustine teaches:
“The method of claim 7, wherein the fifth conductive line is between the second conductive line and the third conductive line along the first direction (Augustine/Fujiwara: Augustine [0047]: VCC is between BL and BLB in order to reduce the capacitive coupling between BL and BLB.),”
Fujiwara/Mojumder/Nii/Augustine doesn’t substantially teach:
“and a length of the fifth conductive line is shorter than a length of
However, Nii #2 teaches:
“and a length of the fifth conductive line is shorter than a length of (Nii #2: VDD, [0068], annotated FIG. 20 #1: The fifth conductive line is shorter than the sixth conductive line. The direction of measurement is along the long side of the VDDs as it is in Fujiwara which one of ordinary skill in the art would recognize as the second direction in Nii #2.).”
It would have been obvious to one with ordinary skill in the art before the effective filing
date of the invention to recognize that the device of Fujiwara/Mojumder/Nii/Augustine is modifiable in view of Nii #2.
This is because Fujiwara/Mojumder/Nii/Augustine teaches a pair conductive lines which provide power to a memory device. Fujiwara/Mojumder/Nii/Augustine doesn’t substantively teach a pair of conductive lines which provide power to a memory device wherein one of the conductive lines is shorter than the other as measured in a second direction. Nii #2 teaches a pair conductive lines which provide power to a memory device. Nii #2 further teaches a pair of conductive lines which provide power to a memory device wherein one of the conductive lines is shorter than the other as measured in a second direction. Because both Fujiwara/Mojumder/Nii/Augustine and Nii #2 have a pair conductive lines which provide power to a memory device, one of ordinary skill in the art would have deemed it obvious to substitute the pair conductive lines which provide power to a memory device Fujiwara/Mojumder/Nii/Augustine for pair conductive lines which provide power to a memory device wherein one of the conductive lines is shorter than the other as measured in a second direction of Nii #2 for the predictable result of providing power to a memory device.
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Fujiwara/Mojumder/Nii as applied to claims 1,2, and 9-10 above, and further in view of Sharma et al US 20240008239 A1. Sharma et al will be referenced to as Sharma henceforth.
Regarding Claim 21,
Fujiwara/Mojumder/Nii/ teaches:
“A method, comprising (Fujiwara: FIG.7):
receiving design data of a memory device (Mojumder: [0057], FIG. 10: design data stored in computer files may be used with fabrication handlers to make the device.); Fujiwara: array 600, FIG. 9) according to the design data (Mojumder: [0057-0064]), the memory array comprising a first cell (Fujiwara second bit cell 450) and a second cell abutting the first cell (Fujiwara: FIG. 7)), the first cell comprising a first gate structure (Fujiwara: polysilicon structures 462, [0041]), a second gate structure (Fujiwara: polysilicon structure 464), a third gate structure (Fujiwara: polysilicon structure 466),
and a fourth gate structure (Fujiwara: polysilicon structure 468) that are parallel to each other (Fujiwara: FIG.7) and extend in a first direction (Fujiwara: the first direction is vertical), wherein the first cell
a data storage element arranged in a device layer (Fujiwara: annotated FIG. 6 #1) and comprising a first node (Fujiwara: node Q, [0024-0025], Q is controlled by PG0.) and a second node (Fujiwara: node Qbar, Qbar is controlled by PQ1.), wherein the data storage element (Fujiwara: transistors PU0, PU1, PD0, PD1) associated with the second gate structure and the third gate structure (Fujiwara: the four transistors lie on 464 and 466.);
a first transistor (Fujiwara: pass gate transistor PG0) and a second transistor (Fujiwara: pass gate transistor PG1) arranged in the device layer and coupled to the first node and the second node, respectively (Fujiwara: [0026]: Qbar is controlled by PG1);
a first conductive line (Fujiwara: annotated FIG. 7 #1) configured to receive a word line select signal ([0046], FIG. 7: WL1 is electrically connected to the first conductive line by via 485.) extending in a second direction, (Fujiwara: the second direction is horizontal) and coupled to a gate structure of the first transistor and a gate structure of the second transistor, (Fujiwara: annotated FIG. 7 #1) the first conductive line overlying a first cell boundary of the first cell, the first cell boundary extending in the second direction (annotated FIG. 7 #3); and
a second conductive line (Fujiwara: BL, [0022]) configured to receive a first bitline select signal and extending in the second direction (Fujiwara: BL is a bit line and therefore receives a bit line select signal.);
a third conductive line (BLB) configured to receive a second bitline select signal (Fujiwara: BLB is a complementary bit line and therefore receives a bit line select signal. BLB and BL provide a complementary bit line signal and a bit line signal respectively.) and extending in the second direction (Fujiwara: annotated FIG. 7 #1) and
a fourth conductive line configured to receive a first supply voltage (Fujiwara: VSS, [0037], FIG.7: VSS is at a reference voltage.), the fourth conductive line overlying a second cell boundary of the first cell (annotated FIG. 7 #3), the second cell boundary being shared by the first cell and the second cell (Fujiwara: FIG. 7: Fujiwara teaches two abutting cells. One of ordinary skill in the art would recognize that the exact boundaries of the two cells are arbitrarily drawn. That is, the boundaries may have been drawn to be in contact with each other while each boundary contains the elements of each cell. Because of this, one of ordinary skill in the art would conclude that the two cells share the same boundary.),”
Fujiwara/Mojumder/Nii doesn’t substantially teach:
“generating a design layout comprising a row decoder”
However, Sharma teaches:
“generating a design layout comprising a row decoder (Sharma: 120, [0026], FIG. 1C ), a line decoder (Sharma: column decoder 130, FIG. 1C)”
Neither Fujiwara/Mojumder or Sharma substantially teaches:
“the second conductive line and the third conductive line being arranged between the first conductive line and the fourth conductive line along the second direction.”
However, Nii teaches:
“the second conductive line and the third conductive line being arranged between the first conductive line and the fourth conductive line along the second direction (Nii: [0085], [0165], annotated FIG. 42 #1).”
It would have been obvious to one with ordinary skill in the art before the effective filing
date of the invention to recognize that the device of Fujiwara/Mojumder is modifiable in view of Sharma and Nii.
This is because one of ordinary skill in the art would recognize that row decoders and column decoders are necessary in the operation of an SRAM device because a row decoder and a column decoder are used to read and write information to the memory array.
Further, this is because Nii teaches that by arranging bit lines complementary to each other side by side, it’s possible to reduce the interference between ports. One of ordinary skill in the art would recognize this as an advantage as the electrical interference between ports can cause errors in the access of a memory cells which is undesirable.
Claims 22-25 are rejected under 35 U.S.C. 103 as being unpatentable over Fujiwara/Mojumder/Nii as applied to claims 3-7 and 11-15 above, and further in view of Sharma.
Regarding Claim 22,
Fujiwara/Mojumder/Nii/Sharma teaches:
“The method of claim 21, wherein the first conductive line is arranged in a first layer over the device layer (Fujiwara: FIG. 6: the M1 layer is above the polysilicon layer. The first conductive line, an M1 line, is in the M1 layer.),”
Fujiwara/Mojumder/Nii/Sharma doesn’t substantially teach:
“and wherein the second conductive line and the third conductive line are arranged in a second layer below the device layer.”
However, Augustine teaches:
“and wherein the second conductive line and the third conductive line are arranged in a second layer below the device layer (Augustine: FIG. 11A: BL and BLB are on the back of the device).”
It would have been obvious to one with ordinary skill in the art before the effective filing
date of the invention to recognize that the device of Fujiwara/Mojumder/Sharma is modifiable in view of Augustine.
This is because one of ordinary skill in the art would want to move the BL and BLB to the back of a singular cell because there is more space in the back of the cell compared to the device layer allowing for compactification of the device and to provide shielding to the BL and BLB in order to reduce capacitive coupling between them by placing them next to the VCC (Augustine: [0043-0047]).
Regarding Claim 23,
Fujiwara/Mojumder/Nii/Sharma/Augustine teaches:
“The method of claim 22, wherein the first cell and configured to receive a second voltage (Fujiwara: power supply VDD, [0024], FIG. 7), wherein (Augustine: VCC (top), [0023] FIG. 11A: VCC provides a second supply voltage and is located on the backside of the device. Two VCCs are shown in FIG. 11A, one on top ,VCC (top), and one on bottom VCC (bottom). FIG. 11A shows VCC extending both horizontally and vertically. VCC is in the second layer along with the second and third conductive lines.)”
It would have been obvious to one with ordinary skill in the art before the effective filing
date of the invention to recognize that the device of Fujiwara/Mojumder/Nii/Sharma is modifiable in view of Augustine.
This is because one of ordinary skill in the art would want to place the VSS in the back of the device to further make room on the device layer allowing for more compactification of the device. One of ordinary skill in the art finds compactification advantageous because the more transistors per unit area, the more computationally powerful a device is.
Regarding Claim 24,
Fujiwara/Mojumder/Nii/Sharma/Augustine teaches:
“The method of claim 21 (Fujiwara: FIG. 7), wherein the data storage element (Fujiwara: S/D contact 472) and a second source/drain region (Fujiwara: S/D contact 476) arranged in the device layer (Fujiwara: annotated FIG. 6B #1) on outer sides of the second gate structure and the third gate structure (Fujiwara: FIG. 7),
wherein the first cell (Fujiwara: annotated FIG. 7 #1) electrically connecting the second gate structure and the second source/drain region (Fujiwara: annotated FIG. 7 #1), and an eighth conductive line (Fujiwara: annotated FIG. 7 #1) electrically connecting the third gate structure and the first source/drain region (Fujiwara: annotated FIG. 7 #1).”
Regarding Claim 25,
Fujiwara/Mojumder/Nii/Sharma/Augustine teaches:
“The method of claim 21, wherein he first cell comprises a ninth conductive line configured to receive the second supply voltage (Fujiwara: S/D contact 404, [0061], FIG. 7. 404 is connected to VSS and therefore receives the first supply voltage. 404 overlies VSS in a vertical direction. One of ordinary skill in the art would know that S/D contacts are conductive.) and arranged between the seventh conductive line and the eighth conductive line along the second direction (Fujiwara: annotated FIG. 7 #3).”
Response to Arguments
Applicant’s amendments to the Claims have overcome the Examiner’s 103 rejections.
Applicant substantively argues:
“Applicant disagrees that length of the fifth conductive line being shorter than length of the sixth conductive line is a matter of choice. The fifth conductive line being shorter is a structural difference that reduces overlap of the fifth conductive line with elements adjacent thereto, which is beneficial at least to reduce parasitic capacitance therebetween.”
The Examiner finds this argument fully persuasive because Applicant has demonstrated a reason for why the length of the fifth conductive line relative to the sixth is not purely a matter of choice
Applicant’s arguments, with respect to the rejection(s) of claims have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Nii and Nii #2.
In the interest of compact prosecution, if the Applicant were to amend an independent claim with the following limitation:
“the first conductive line overlying a first cell boundary of the first cell in a direction perpendicular to the first direction and the second direction, the first cell boundary extending in the second direction”
It would overcome the current rejections for claim 1. The Examiner is available for interview at Applicant’s convenience for discussion of claim amendments.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDRE XAVIER RAMIREZ whose telephone number is (571)272-2715. The examiner can normally be reached Monday - Friday 8:30 AM to 6:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ALEXANDRE X RAMIREZ/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812