DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant's response to the Office Final Action filed on 12/16/2025 is acknowledged.
Applicant amended claims 1, 4, 9, and 16.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/16/2025 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 4, 7, 8, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al. (US 11011626 B2) (hereafter Cheng626), in view of Cheng et al. (US 2017/0338322) (hereafter Cheng322), in further view of Chang et al. (US 2016/0225764) (hereafter Chang764).
Regarding claim 1, Cheng626 discloses a device comprising:
a plurality of first fins (120 on the left hand side of 160 in Fig. 11E, Col. 7, Line 20) protruding from a substrate 101 (Fig. 11E, Col. 7, Line 16);
a plurality of second fins (120 on the right hand side of 160 in Fig. 11E, Col. 7, Line 20) protruding from the substrate 101 (Fig. 11E);
a dummy fin (element number is not shown in Fig. 11E but see 125 in Fig. 11C, Col. 13, Line 17) protruding from the substrate 101 (Fig. 11E) between the plurality of first fins (120 on the left hand side of 160 in Fig. 11E) and the plurality of second fins (120 on the right hand side of 160 in Fig. 11E), wherein the dummy fin (element number is not shown in Fig. 11E but see 125 in Fig. 11C) extends in a first direction (vertical direction in Fig. 11E);
a first gate stack (170 on the left hand side of 160 in Fig. 11E, Col. 11, Line 56) extending over the plurality of first fins (120 on the left hand side of 160 in Fig. 11E);
a second gate stack (170 on the right hand side of 160 in Fig. 11E, Col. 11, Line 56) extending over the plurality of second fins (120 on the right hand side of 160 in Fig. 11E), wherein the first gate stack (170 on the left hand side of 160 in Fig. 11E) is longitudinally aligned with the second gate stack (170 on the right hand side of 160 in Fig. 11E), wherein the first gate stack (170 on the left hand side of 160 in Fig. 11E) and the second gate stack (170 on the right hand side of 160 in Fig. 11E) have a first width (vertical length of 170 in Fig. 11E) in the first direction (vertical direction in Fig. 11E); and
an isolation region 160 (Fig. 11E, Col. 11, Line 49) on the top surface of the dummy fin (element number is not shown in Fig. 11E but see 125 in Fig. 11C) and extending between the first gate stack (140 on the left hand side of 160 in Fig. 11E) and the second gate stack (140 on the right hand side of 160 in Fig. 11E), the isolation region 160 (Figs. 11A and 11E, Col. 13, Lines 32-35, wherein “The segmented gate structure illustrates a non-shared scenario, where respective segments are electrically isolated gates for transistors of respective active regions AR”) electrically isolating the first gate stack (170 on the left hand side of 160 in Fig. 11E) from the second gate stack (170 on the right hand side of 160 in Fig. 11E), wherein the isolation region 160 (Fig. 11E) has a second width (vertical length of 160 in Fig. 11E) in the first direction that is larger than the first width (vertical length of 170 in Fig. 11E).
Cheng626 does not disclose a top surface of a first fin is at least as high above the substrate as a top surface of the dummy fin.
Cheng322 discloses a top surface of a first fin 20 (Fig. 14, paragraph 0048) is at least as high above the substrate 12 (Fig. 14, paragraph 0034) as a top surface of the dummy fin 48 (Fig. 14, paragraph 0046).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Cheng626 to form a top surface of a first fin is at least as high above the substrate as a top surface of the dummy fin, as taught by Cheng322, since the fins 20, 22, 48, 50 (Cheng322, Fig. 14, paragraph 0047) are uniformly disposed across the device 10 (Cheng322, Fig. 14, paragraph 0047), no topography issues will arise in subsequent processing. In addition, since a change in size is generally recognized as being within the level of ordinary skill in the art In re Rose, 105 USPQ 237 (CCPA 1955).
Cheng626 and Cheng322 do not disclose a first distance between the first gate stack and the second gate stack near a top surface of the isolation region is smaller than a second distance between the first gate stack and the second gate stack near a bottom surface of the isolation region.
Chang764 discloses a first distance (W3 in Fig. 1A, paragraph 0026) between the first gate stack (left 40 in Fig. 1A, paragraph 0013) and the second gate stack (right 40 in Fig. 1A, paragraph 0013) near a top surface (top surface of 60 in Fig. 1A) of the isolation region 60 (Fig. 1A, paragraph 0026) is smaller than a second distance (W4 in Fig. 1A, paragraph 0026) between the first gate stack (left 40 in Fig. 1A) and the second gate stack (right 40 in Fig. 1A) near a bottom surface (bottom surface of 60 in Fig. 1A) of the isolation region 60 (Fig. 1A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Cheng626 in view of Cheng322 to form a first distance between the first gate stack and the second gate stack near a top surface of the isolation region is smaller than a second distance between the first gate stack and the second gate stack near a bottom surface of the isolation region, as taught by Chang764, since the width (Chang764, paragraph 0056) of the top portion of the exposed separation plug is reduced, opening area OA (Chang764, Fig. 12B, paragraph 0056) becomes wider such that this wider opening OA (Chang764, Fig. 12B, paragraph 0056) makes it possible for metal materials for the metal gate structure to more conformally fill the space.
Regarding claim 2, Cheng626 further discloses the device of claim 1, further comprising a dielectric fin (element number is not shown in Fig. 11E but see 125 in Fig. 11C, Col. 13, Line 17) extending from the bottom surface of the isolation region 160 (Fig. 11E) toward the substrate 101 (Fig. 11E), wherein a bottom surface of the dielectric fin (element number is not shown in Fig. 11E but see 125 in Fig. 11C) is below a bottom surface of the first gate stack (170 on the left hand side of 160 in Fig. 11E).
Regarding claim 4, Cheng626 further discloses the device of claim 1, wherein the first gate stack (170 on the left hand side of 160 in Fig. 11E) extends underneath the bottom surface (bottom surface of 160 contacting top surface of a dielectric fin (element number is not shown in Fig. 11E but see 125 in Fig. 11C)) of the isolation region 160 (Fig. 11E, Col. 11, Line 49).
Regarding claim 7, Cheng626 in view of Cheng322 and Chang764 discloses the device of claim 1, however Cheng626 and Cheng322 do not disclose the first distance is between 1 nm and 70 nm.
Chang764 discloses the first distance (W3 in Fig. 1A, paragraph 0026, wherein “range of about 5 nm to about 15 nm”) is between 1 nm and 70 nm.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Cheng626 in view of Cheng322 to form the first distance is between 1 nm and 70 nm, as taught by Chang764, since a change in size is generally recognized as being within the level of ordinary skill in the art In re Rose, 105 USPQ 237 (CCPA 1955). In addition, in the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). Note that the specification contains no disclosure of either the critical nature of the claimed ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 f.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Regarding claim 8, Cheng626 in view of Cheng322 and Chang764 discloses the device of claim 1, however Cheng626 and Cheng322 do not disclose the second distance is between 10 nm and 70 nm.
Chang764 discloses the second distance (W4 in Fig. 1A, paragraph 0026, wherein “range of about 10 nm to about 30 nm”) is between 10 nm and 70 nm.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Cheng626 in view of Cheng322 to form the second distance is between 10 nm and 70 nm, as taught by Chang764, since a change in size is generally recognized as being within the level of ordinary skill in the art In re Rose, 105 USPQ 237 (CCPA 1955). In addition, in the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). Note that the specification contains no disclosure of either the critical nature of the claimed ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 f.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Regarding claim 21, Cheng626 further discloses the device of claim 1, wherein a bottom surface (bottom surface of 170 in Fig. 11D) of the first gate stack 170 (Fig. 11D) is higher (see Col. 11, Lines 52-55, wherein “Gate structures 170 are formed in openings left after removal of the dummy gates 140, and are formed on and around the patterned substrate portions 120 and the dummy elements 125”; and see Col. 12, Lines 10-11, wherein “The gate structures 170 further include gate conductor layers formed on the dielectric layer.” Therefore, the dielectric layer is formed between 125 and 170, wherein the bottom surface of 170 is higher than the top surface of 125 in Fig. 11D) above the substrate 101 (Fig. 11D) than the top surface of the dummy fin 125 (Fig. 11D).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Cheng626 in view of Cheng322 and Chang764 as applied to claim 1 above, and further in view of Kim et al. (US 2020/0083222) (hereafter Kim).
Regarding claim 6, Cheng626 further discloses the device of claim 1, wherein a Shallow Trench Isolation (STI) 130 (Fig. 11E, Col. 7, Line 46) surrounding the plurality of first fin (120 on the left hand side of 160 in Fig. 11E) and the plurality of second fins (120 on the right hand side of 160 in Fig. 11E).
Cheng626, Cheng322, and Chang764 do not disclose a bottom surface of the isolation region is below a top surface of the STI.
Kim discloses a bottom surface of the isolation region 151 (Fig. 3, paragraph 0044) is below a top surface of the STI 105 (Fig. 3, paragraph 0028).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Cheng626 in view of Cheng322 and Chang764 to form a bottom surface of the isolation region is below a top surface of the STI, as taught by Kim, since the gate isolation layer 155 (Kim, Fig. 3, paragraph 0053) does not have to be formed deeply so that the gate isolation layer 155 (Kim, Fig. 3, paragraph 0053) touches the device isolation layer 105 (Kim, Fig. 3, paragraph 0053), limitations of a photolithography and an etching process that are caused by a failure to completely remove the dummy gate material may be overcome, and variations of a threshold voltage Vth may be prevented or mitigated.
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Cheng626 in view of Cheng322 and Chang764 as applied to claim 1 above, and further in view of Liou et al. (US 2019/0051731) (hereafter Liou).
Regarding claim 22, Cheng626 in view of Cheng322 and Chang764 discloses the device of claim 1, however Cheng626, Cheng322, and Chang764 do not disclose a top surface of the first fin is higher above the substrate than the top surface of the dummy fin.
Liou discloses a top surface of the first fin 102a (Fig. 14, paragraph 0041) is higher above the substrate 100 (Fig. 14, paragraph 0024) than the top surface of the dummy fin 119 (Fig. 14, paragraph 0043).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Cheng626 in view of Cheng322 and Chang764 to form a top surface of the first fin is higher above the substrate than the top surface of the dummy fin, as taught by Liou, since a change in size is generally recognized as being within the level of ordinary skill in the art In re Rose, 105 USPQ 237 (CCPA 1955). Note that the specification contains no disclosure of either the critical nature of the claimed ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 f.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Allowable Subject Matter
Claims 9-20 are allowed. The following is an examiner’s statement of reasons for allowance: a closest prior art, Cheng et al. (US 11011626 B2), discloses a first gate structure (170 on the left hand side of 160 in Fig. 11E, Col. 11, Line 56) extending over the first fin (120 on the left hand side of 160 in Fig. 11E) and the first isolation region 130 (Fig. 11E); a second gate structure extending (170 on the right hand side of 160 in Fig. 11E, Col. 11, Line 56) over the second fin (120 on the right hand side of 160 in Fig. 11E) and the first isolation region 130 (Fig. 11E); and an isolation structure (element number is not shown in Fig. 11E but see 125 (Fig. 11C, Col. 13, Line 17) and 160 (Fig. 11E, Col. 11, Line 49)) between the first fin (120 on the left hand side of 160 in Fig. 11E) and the second fin (120 on the right hand side of 160 in Fig. 11E), wherein the isolation structure (element number is not shown in Fig. 11E but see 125 (Fig. 11C, Col. 13, Line 17) and 160 (Fig. 11E, Col. 11, Line 49)) separates the first gate structure (170 on the left hand side of 160 in Fig. 11E) and the second gate structure (170 on the right hand side of 160 in Fig. 11E), wherein the isolation structure (element number is not shown in Fig. 11E but see 125 (Fig. 11C, Col. 13, Line 17) and 160 (Fig. 11E, Col. 11, Line 49)) comprises a lower isolation portion (element number is not shown in Fig. 11E but see 125 (Fig. 11C, Col. 13, Line 17)) on the substrate 101 (Fig. 11E) and an upper isolation portion 160 (Fig. 11E, Col. 11, Line 49) on the lower isolation portion (element number is not shown in Fig. 11E but see 125 (Fig. 11C, Col. 13, Line 17)) but fails to disclose a first width of the upper isolation portion is greater than a second width of the lower isolation portion; wherein the first isolation region surrounds the lower isolation portion; a top surface of the upper isolation portion has a third width that is smaller than the first width; and a second isolation region over the first isolation region, wherein the second isolation region extends along sidewalls of the first gate structure, the second gate structure, the lower isolation portion, and the upper isolation portion. Additionally, the prior art does not teach or suggest a device comprising: a second isolation region over the first isolation region, wherein the second isolation region extends along sidewalls of the first gate structure, the second gate structure, the lower isolation portion, and the upper isolation portion in combination with other elements of claim 9.
In addition, a closest prior art, Cheng et al. (US 11011626 B2), discloses a dummy fin (element number is not shown in Fig. 11E but see 125 in Fig. 11C, Col. 13, Line 17) on the substrate 101 (Fig. 11E) adjacent the semiconductor fin 120 (Fig. 11E), wherein the dummy fin (element number is not shown in Fig. 11E but see 125 in Fig. 11C) has a first width; and an isolation region 160 (Fig. 11E, Col. 11, Line 49) on the dummy fin (element number is not shown in Fig. 11E but see 125 in Fig. 11C) but fails to disclose the isolation region tapers upward, wherein a top surface of the isolation region has a second width that is smaller than the first width; and wherein a bottom surface of the isolation region is farther from the substrate than a bottom surface of the first gate dielectric layer. Additionally, the prior art does not teach or suggest a device comprising: the isolation region tapers upward, wherein a top surface of the isolation region has a second width that is smaller than the first width; and wherein a bottom surface of the isolation region is farther from the substrate than a bottom surface of the first gate dielectric layer in combination with other elements of claim 16.
A closest prior art, Cheng et al. (US 11011626 B2), discloses a device comprising: a first fin (120 on the left hand side of 160 in Fig. 11E, Col. 7, Line 20) and a second fin (120 on the right hand side of 160 in Fig. 11E, Col. 7, Line 20) on a semiconductor substrate 101 (Fig. 11E, Col. 7, Line 16); a first isolation region 130 (Fig. 11E, Col. 7, Line 46) surrounding the first fin (120 on the left hand side of 160 in Fig. 11E) and the second fin (120 on the right hand side of 160 in Fig. 11E); a first gate structure (170 on the left hand side of 160 in Fig. 11E, Col. 11, Line 56) extending over the first fin (120 on the left hand side of 160 in Fig. 11E) and the first isolation region 130 (Fig. 11E); a second gate structure extending (170 on the right hand side of 160 in Fig. 11E, Col. 11, Line 56) over the second fin (120 on the right hand side of 160 in Fig. 11E) and the first isolation region 130 (Fig. 11E); and an isolation structure (element number is not shown in Fig. 11E but see 125 (Fig. 11C, Col. 13, Line 17) and 160 (Fig. 11E, Col. 11, Line 49)) between the first fin (120 on the left hand side of 160 in Fig. 11E) and the second fin (120 on the right hand side of 160 in Fig. 11E), wherein the isolation structure (element number is not shown in Fig. 11E but see 125 (Fig. 11C, Col. 13, Line 17) and 160 (Fig. 11E, Col. 11, Line 49)) separates the first gate structure (170 on the left hand side of 160 in Fig. 11E) and the second gate structure (170 on the right hand side of 160 in Fig. 11E), wherein the isolation structure (element number is not shown in Fig. 11E but see 125 (Fig. 11C, Col. 13, Line 17) and 160 (Fig. 11E, Col. 11, Line 49)) comprises a lower isolation portion (element number is not shown in Fig. 11E but see 125 (Fig. 11C, Col. 13, Line 17)) on the substrate 101 (Fig. 11E) and an upper isolation portion 160 (Fig. 11E, Col. 11, Line 49) on the lower isolation portion (element number is not shown in Fig. 11E but see 125 (Fig. 11C, Col. 13, Line 17)) but fails to teach a first width of the upper isolation portion is greater than a second width of the lower isolation portion; wherein the first isolation region surrounds the lower isolation portion; a top surface of the upper isolation portion has a third width that is smaller than the first width; and a second isolation region over the first isolation region, wherein the second isolation region extends along sidewalls of the first gate structure, the second gate structure, the lower isolation portion, and the upper isolation portion as the context of claim 9. The other allowed claims each depend from one of these claims, and each is allowable for the same reasons as the claim from which it depends. Claims 10-15 depend on claim 9.
In addition, a closest prior art, Cheng et al. (US 11011626 B2), discloses a device comprising: a semiconductor fin 120 (Fig. 11E, Col. 7, Line 20) on a substrate 101 (Fig. 11E, Col. 7, Line 16); a dummy fin (element number is not shown in Fig. 11E but see 125 in Fig. 11C, Col. 13, Line 17) on the substrate 101 (Fig. 11E) adjacent the semiconductor fin 120 (Fig. 11E), wherein the dummy fin (element number is not shown in Fig. 11E but see 125 in Fig. 11C) has a first width; an isolation region 160 (Fig. 11E, Col. 11, Line 49) on the dummy fin (element number is not shown in Fig. 11E but see 125 in Fig. 11C); a first gate dielectric layer (“gate dielectric layer” (Col. 11, Line 56) in left 170 in Fig. 11E) physically extending (see bridging paragraph from Col. 11 to Col. 12, wherein “The gate dielectric material can be formed by any suitable process or any suitable combination of multiple processes, including but not limited to, thermal oxidation, chemical oxidation, thermal nitridation, plasma oxidation, plasma nitridation, ALD, CVD, etc.”) on a first sidewall of the dummy fin (element number is not shown in Fig. 11E but see 125 in Fig. 11C) and on a first sidewall (left sidewall of 160 in Fig. 11E) of the isolation region 160 (Fig. 11E); a first gate electrode layer (“gate conductor layers” (Col. 12, Line 11) in left 170 in Fig. 11E) over the first gate dielectric layer (“gate dielectric layer” (Col. 11, Line 56) in left 170 in Fig. 11E); a second gate dielectric layer (“gate dielectric layer” (Col. 11, Line 56) in right 170 in Fig. 11E) physically extending on (see bridging paragraph from Col. 11 to Col. 12, wherein “The gate dielectric material can be formed by any suitable process or any suitable combination of multiple processes, including but not limited to, thermal oxidation, chemical oxidation, thermal nitridation, plasma oxidation, plasma nitridation, ALD, CVD, etc.”) a second sidewall of the dummy fin (element number is not shown in Fig. 11E but see 125 in Fig. 11C) and on a second sidewall (right sidewall of 160 in Fig. 11E) of the isolation region 160 (Fig. 11E); and a second gate electrode layer (“gate conductor layers” (Col. 12, Line 11) in right 170 in Fig. 11E) over the second gate dielectric layer (“gate dielectric layer” (Col. 11, Line 56) in right 170 in Fig. 11E) but fails to teach the isolation region tapers upward, wherein a top surface of the isolation region has a second width that is smaller than the first width; and wherein a bottom surface of the isolation region is farther from the substrate than a bottom surface of the first gate dielectric layer as the context of claim 16. The other allowed claims each depend from one of these claims, and each is allowable for the same reasons as the claim from which it depends. Claims 17-20 depend on claim 16.
Response to Arguments
1. Applicant's arguments filed 12/16/2025 have been fully considered.
2. The applicant argues (REMARKS, Bridging paragraph from page 6 to page 7) that “Claim 1 has been amended herein to recite "a dummy fin protruding from the substrate between the plurality of first fins and the plurality of second fins, wherein a top surface of a first fin is at least as high above the substrate as a top surface of the dummy fin, wherein the dummy fin extends in a first direction," "a first gate stack extending over the plurality of first fins," "a second gate stack extending over the plurality of second fins, wherein the first gate stack is longitudinally aligned with the second gate stack, wherein the first gate stack and the second gate stack have a first width in the first direction," and "an isolation region on the top surface of the dummy fin and extending between the first gate stack and the second gate stack, the isolation region electrically isolating the first gate stack from the second gate stack, wherein a first distance between the first gate stack and the second gate stack near a top surface of the isolation region is smaller than a second distance between the first gate stack and the second gate stack near a bottom surface of the isolation region, wherein the isolation region has a second width in the first direction that is larger than the first width."”. In addition, the applicant argues (REMARKS, first paragraph in page 7) that “The Office Action has not yet illustrated how the cited references teach or suggest the recited features. As such, until the Examiner does illustrate how the cited references teach or suggest the recited features, Applicant respectfully requests that the rejection of claim 1 be withdrawn.” However, Cheng et al. (US 11011626 B2) disclose a dummy fin (element number is not shown in Fig. 11E but see 125 in Fig. 11C, Col. 13, Line 17) protruding from the substrate 101 (Fig. 11E) between the plurality of first fins (120 on the left hand side of 160 in Fig. 11E) and the plurality of second fins (120 on the right hand side of 160 in Fig. 11E), wherein the dummy fin (element number is not shown in Fig. 11E but see 125 in Fig. 11C) extends in a first direction (vertical direction in Fig. 11E); a first gate stack (170 on the left hand side of 160 in Fig. 11E, Col. 11, Line 56) extending over the plurality of first fins (120 on the left hand side of 160 in Fig. 11E); a second gate stack (170 on the right hand side of 160 in Fig. 11E, Col. 11, Line 56) extending over the plurality of second fins (120 on the right hand side of 160 in Fig. 11E), wherein the first gate stack (170 on the left hand side of 160 in Fig. 11E) is longitudinally aligned with the second gate stack (170 on the right hand side of 160 in Fig. 11E), wherein the first gate stack (170 on the left hand side of 160 in Fig. 11E) and the second gate stack (170 on the right hand side of 160 in Fig. 11E) have a first width (vertical length of 170 in Fig. 11E) in the first direction (vertical direction in Fig. 11E); and an isolation region 160 (Fig. 11E, Col. 11, Line 49) on the top surface of the dummy fin (element number is not shown in Fig. 11E but see 125 in Fig. 11C) and extending between the first gate stack (140 on the left hand side of 160 in Fig. 11E) and the second gate stack (140 on the right hand side of 160 in Fig. 11E), the isolation region 160 (Figs. 11A and 11E, Col. 13, Lines 32-35, wherein “The segmented gate structure illustrates a non-shared scenario, where respective segments are electrically isolated gates for transistors of respective active regions AR”) electrically isolating the first gate stack (170 on the left hand side of 160 in Fig. 11E) from the second gate stack (170 on the right hand side of 160 in Fig. 11E), wherein the isolation region 160 (Fig. 11E) has a second width (vertical length of 160 in Fig. 11E) in the first direction that is larger than the first width (vertical length of 170 in Fig. 11E).
Conclusion
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/L.B.K/Examiner, Art Unit 2813
/SHAHED AHMED/Primary Examiner, Art Unit 2813