DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to the amendment filed on 12/30/24. Claims 1-14 and 21-26 are pending.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 21 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kuo et al. (US PGPub 2015/0348872, hereinafter referred to as “Kuo”).
Kuo discloses the semiconductor method as claimed. See figures 1-5 and corresponding text, where Kuo teaches, in claim 21, a method of manufacturing a semiconductor device, the method comprising:
forming metallization layers over a semiconductor substrate (figure 4; [0027]); and
forming a first pad (150), a first dummy pad (180), a second dummy pad (190), and a second pad (152) over the metallization layer, wherein the first pad is separated from a second pad over the metallization layers, wherein the first dummy pad is between the first pad and the second pad, and wherein a second dummy pad is at least partially between the first pad and the second pad, the second dummy pad having a width larger than a shortest distance between the first pad and the second pad (figure 5; [0031-0033], Kuo), wherein the first pad and the second pad are aligned in a first direction, and wherein the first dummy pad and the second dummy pad are aligned in a second direction different from the first direction (figure 5; [0031]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kuo et al. (US PGPub 2015/0348872, hereinafter referred to as “Kuo”) in view of Lee et al. (US PGPub 2022/0013502, hereinafter referred to as “Lee”).
Kuo discloses the semiconductor method substantially as claimed. See figures 1-5 and corresponding text, where Kuo shows, in claim 1, a method of manufacturing a semiconductor device, the method comprising:
forming a first pad (150) (plurality of metal pads) over a semiconductor substrate (110);
forming a second pad (152) (plurality of metal pads) adjacent to the first pad (figure 5; [0031]);
forming a first set of dummy pads (180) at least partially between the first pad (150) and the second pad (152) (figure 5; [0031]);
pad, wherein at least two of the dummy pads within the first set of dummy pads are the same distance from the first pad in a first direction (figure 5; [0031]).
However, Kuo fails to show, in claim 1, depositing a bonding dielectric material over the first pad, the second pad, and the first set of dummy pads.
Lee teaches, in claim 1, a similar method that includes depositing a bonding dielectric material (10UI) over the first pad (MP1), the second pad (MP2), and the first set of dummy pads (DPR1) (figure 8; [0070]). In addition, Lee provides the advantages of minimizing local erosion of an insulating layer during a bonding operation ([0004]).
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was filed, to incorporate depositing a bonding dielectric material over the first pad, the second pad, and the first set of dummy pads, in the method of Kuo, according to the teachings of Lee, with the motivation of minimizing local erosion of an insulating layer during a bonding operation.
Kuo in view of Lee shows, in claim 2, wherein the forming the first set of dummy pads comprises forming first dummy pads and second dummy pads between the first pad and the second pad, the second dummy pads having a larger width than the first dummy pads (figure 5; [0031-0033], Kuo).
Kuo in view of Lee shows, in claim 3, wherein the second dummy pads have a larger width than a distance between the first pad and the second pad (figure 5; [0031-0033], Kuo).
Kuo in view of Lee shows, in claim 4, wherein the forming the first dummy pads and the second dummy pads forms the second dummy pads having chamfered corners.
Kuo in view of Lee shows, in claim 5, wherein the forming the first set of dummy pads forms a third dummy pad adjacent to one of the second dummy pads, the third dummy pad being a continuous line (figure 5; [0031-0033], Kuo).
Kuo in view of Lee shows, in claim 6, wherein the forming the first set of dummy pads forms a third dummy pad adjacent to one of the second dummy pads, the third dummy pad being a discontinuous line (figure 5; [0031-0033], Kuo).
Kuo shows, in claim 7, a method of manufacturing a semiconductor device, the method comprising: (figure 5; [0031-0033])
forming a first pad (150) and a second pad (152) over a metallization layer;
forming a first set of dummy pads (180) around the first pad and the second pad, the first set of dummy pads comprising:
a first dummy pad between the first pad and the second pad, the first dummy pad being rectangular in shape;
shape, wherein a dielectric material (120) extends in a first direction all of the way from the first dummy pad to the first pad (figures 4 and 5; [0012] [0027-0029]);
a second dummy pad (190) between the first pad and the second pad, the second dummy pad being wider than the first dummy pad (figure 5; [0031-0033]);
pad, wherein the dielectric material (120) extends in the first direction all of the way from the second dummy pad to the first pad:
a third dummy pad on an opposite side of the second dummy pad from the first dummy pad, the third dummy pad having a different width than the second dummy pad (figure 5; [0031-0033], the examiner views that Kuo discloses a plurality of dummy pads within the region having different width sizes, thus meets the limitation)); and
However, Kuo fails to show, in claim 7, forming a bonding layer over the first pad and the second pad, the bonding layer comprising a conductive bond pad in electrical connection with the first pad.
Lee teaches, in claim 7, a similar method that includes depositing a bonding dielectric material (10UI) over the first pad (MP1), the second pad (MP2), and the first set of dummy pads (DPR1) (figure 8; [0070]). In addition, Lee provides the advantages of minimizing local erosion of an insulating layer during a bonding operation ([0004]).
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was filed, to incorporate forming a bonding layer over the first pad and the second pad, the bonding layer comprising a conductive bond pad in electrical connection with the first pad, in the method of Kuo, according to the teachings of Lee, with the motivation of minimizing local erosion of an insulating layer during a bonding operation.
Kuo in view of Lee shows, in claim 8, further comprising bonding the bonding layer to a second bonding layer (figure 8; [0070], Lee).
Kuo in view of Lee shows, in claim 9, wherein the bonding the bonding layer forms a hybrid bond ([0043], Lee).
Kuo in view of Lee shows, in claim 10, wherein the bonding the bonding layer forms a fusion bond ([0055], Lee).
Kuo in view of Lee shows, in claim 11, wherein the third dummy pad is discontinuous (figure 5; [0031-0033], Kuo).
Kuo in view of Lee shows, in claim 12, wherein different portions of the third dummy pad have centerlines that are off-center from each other (figure 5; [0031-0033], Kuo).
Kuo in view of Lee shows, in claim 13, wherein the second dummy pad has a first chamfered corner ([0044], Lee).
Kuo in view of Lee shows, in claim 14, wherein the first pad has a second chamfered corner ([0044], Lee).
Claim(s) 22-26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kuo et al. (US PGPub 2015/0348872, hereinafter referred to as “Kuoas applied to claim 21 above, and further in view of Lee et al. (US PGPub 2022/0013502, hereinafter referred to as “Lee”).
Kuo discloses the semiconductor method of claim 21 above.
However, Kuo fails to show, in claim 22, wherein the second dummy pad is in an "S"- shape.
Lee teaches, in claim 22, that the dummy pads can be made in various shapes [0044], and provides the advantages of preventing local erosion of insulating layers surrounding connection pads, thus improving bonding operations ([0003-0004]).
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was filed, to incorporate, wherein the second dummy pad is in an "S"- shape, in the method of Kuo, according to the teachings of Lee, with the motivation of preventing local erosion of insulating layers surrounding connection pads, thus improving bonding operations
Kuo fails to explicitly show, in claim 23, wherein the first pad and the second pad have a pitch of about 35 µm.
Lee teaches, in claim 23, that the main connection pad structures having different pitches ([0041], [0068]). In addition, Lee provides the advantages of preventing local erosion of insulating layers surrounding connection pads, thus improving bonding operations ([0003-0004]).
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was filed, to incorporate wherein the first pad and the second pad have a pitch of about 35 µm, in the method of Kuo, according to the teachings of Lee, with the motivation of preventing local erosion of insulating layers surrounding connection pads, thus improving bonding operations
Kuo in view of Lee shows, in claim 24, wherein the second dummy pad has at least one chamfered corner ([0044], Lee).
Kuo in view of Lee shows, in claim 25, further comprising forming a third dummy pad, wherein after the forming the third dummy pad the third dummy pad is on an opposite side of the second dummy pad from the first dummy pad, the third dummy pad being discontinuous (figure 5; [0031-0033], Kuo).
Kuo in view of Lee shows, in claim 26, wherein the first pad is circular ([0044], Lee).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-14 and 21-26 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Applicant’s amendment has necessitated new grounds of rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STANETTA D ISAAC whose telephone number is (571)272-1671. The examiner can normally be reached M-F 11-8.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at 571-272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/STANETTA D ISAAC/Examiner, Art Unit 2898 April 30, 2025
/JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898