Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant elected without traverse group I and species A (Fig. 13), claims 1-8 and 21-32 in the reply filed on December 13, 2024. Claim 33 was cancelled and claim 34 was added in the amendment filed on March 31, 2025. Claims 1, 3-8, 21-32 and 34 are pending in this application.
Response to Amendment
This Office Action is in response to Applicant’s Amendment filed December 5, 2025. Claims 1, 21, and 29 are amended. The Examiner notes that claims 1, 3-8, 21-32 and 34 are examined.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 4, and 21-28 are rejected under 35 U.S.C. 103 as being unpatentable over Woo (US 2018/0126718 A1) in view of Maki (US 2008/0318346 A1), Pei (US 2016/0126226 A1), Sreenivasan (US 2021/0134640 A1), Choi (US 2023/0163094 A1), Tsuno (US 2011/0011536 A1), and Araki (JP 2002184847 A).
With respect to claim 1, Woo teaches:
A method for forming a semiconductor device, comprising:
providing a wafer (para 27 “holding element”) with multiple semiconductor dies (para. 27, “electrical component”, para. 52 “predetermined number of electrical components”);
picking the semiconductor die up with a collector element (para. 27, Fig. 3, flip head collet 308);
flip-chipping the semiconductor die with the collector element (Fig. 3);
picking up the semiconductor die (para. 27, “electrical component”) from the collector element (308) using a bond-head element (bond head collet 304) (para. 41, When the bond head 302 is at the alignment position, the electrical component is transferred from the flip head collet 310 to the bond head collet 304”);
and bonding the semiconductor die (“electrical component”) to a carrier (bonding pad 606) using the bond-head element (bond head collet 304) (para. 51)
Woo fails to teach:
an adhesive film held by a frame element;
lifting a semiconductor die up from the wafer using an ejector element;
performing a measurement of a warpage of the semiconductor die on the bond-head element using a sensor;
measuring a tilt of the carrier relative to a horizontal plane using a tilt sensor on the bond-head element before the semiconductor die is bonded to the carrier
and operating a tilt mechanism disposed on corners of a stage holding the carrier to adjust the tilt to level the carrier relative to the horizontal plane while the carrier is on the stage.
Maki teaches:
an adhesive film (Fig. 5-7, dicing tape 4) held by a frame element (wafer ring 5);
lifting a semiconductor die (Fig. 30, chip 1) up from the wafer using an ejector element (block 110c of chucking piece 102);
Pei teaches:
performing a measurement of a warpage of the semiconductor die (para. 48 “the corresponding warpage of the package may be determined by measuring and analyzing the moiré pattern using a defect inspector.”)
Sreenivasan teaches:
performing a measurement of the semiconductor die on the bond-head element using a sensor (para. 50-56 give the order of steps “3. Element pickup 4. Alignment of elements to product substrate and temporary attachment 5. Bonding” para. 47 specifies that the process of alignment uses moire based metrology as used in Pei.)
Choi teaches in Fig. 4:
measuring a tilt of the carrier (substrate 104) relative to a horizontal plane (para. 45 “parallelism between the chip 102 and the substrate 104) using a tilt sensor (claim 13, “air gyro.” It is known in the art that a gyroscope/gyrometer may be used to measure orientation ) on the bond-head element (bonding head 150) (Fig. 4 shows the tilt adjusting driver 156 is on bonding head 150, claim 13 “wherein the tilt adjusting driver comprises an air gyro”), before the semiconductor die (chip 102) is bonded to the carrier (substrate 104) (para. 45 “the controller adjusts the parallelism between the chip 102 and the substrate 104 through the tilt adjusting driver”)
Tsuno teaches:
operating a tilt mechanism to adjust the tilt to level the carrier relative to the horizontal plane. (para. 15 “the room temperature bonding apparatus can use the angle adjustment mechanism to change a direction of the first substrate such that a first surface of the first substrate, which faces to the second substrate, and a second surface of the second substrate, which faces to the first substrate, come into parallel contact with each other”)
Araki teaches in Figs. 4-5:
and operating a tilt mechanism (mechanism 124 including height adjustment posts 126) disposed on corners of a stage (heating and laminating stage 122) holding the carrier (wafer 12) while the carrier (12) is on the stage (para. 13 “The tilting mechanism 124 is configured such that the heating and laminating stage 122 is supported by four height adjustment posts 126 that can be moved up and down and are arranged at the four corners of a fixed stage 125 below it, and by changing the height of these four height adjustment posts 126,” “The tilt direction and tilt angle are determined by the control unit 123 so that the lateral shear stress on the wafer 12 caused by the airflow and the sliding stress on the wafer 12 caused by the tilt of the thermal bonding stage 122 are balanced.”)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Maki, Pei, Sreenivasan, Choi, and Tsuno into the method of Woo to attach a semiconductor die to an adhesive film, lift the die using an ejector element, performing a warpage measurement, perform a tilt measurement while the die is attached to the bond head, and level the carrier before bonding. The ordinary artisan would have been motivated to modify Woo in the manner set forth above for the purpose of reduce defects and increase speed in the manufacturing process (para. 29 of Maki), “achiev[ing] sub-100 nm and in some embodiments sub-25 nm or even sub-10 nm alignment in assembly” (Sreenivasan paragraph 47), finding “desired parameters for the composition” (Pei paragraph 48), “adjusting the parallelism between the chip and the substrate” (para. 45 of Choi), and causing the substrates to come into parallel contact with each other and uniformly impose the larger load on a bonding surface (para. 15 of Tsuno).
It would have been obvious to one of ordinary skill in the art at the time of the invention to further modify the method of Woo/Maki/Pei/Sreenivasan/Choi/Tsuno with the tilt adjustment mechanism of Araki to have the tilt adjustment mechanism attached to the corners of the stage. The claim would have been obvious because the technique of adjusting tilt using an adjustment mechanism attached to the corners of the stage was part of the ordinary capabilities of a person of ordinary skill in the art, in view of the teaching of the technique for improvement as taught by Araki. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
With respect to claim 3, Woo further teaches:
The method as claimed in claim 1, further comprising: performing an alignment check (step 420, para. 40) to determine a position of the semiconductor die between a center of the bond-head element (bond head collet 304) and a center of the semiconductor die (electrical component). (para. 55 The bond head 302 is then moved to a position at which the center of the bond head collet 304 is aligned with the center of the electrical component)
With respect to claim 4, Woo/Maki/Pei/Sreenivasan/Choi/Tsuno/Araki do not explicitly teach:
method as claimed in claim 3, wherein the measurement to the warpage of the semiconductor die is performed prior to the alignment check.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to measure the warpage prior to alignment check. The ordinary artisan would have been motivated to order the measurements this way for the purpose of using information about the warpage to adjust the ideal alignment positions based on warpage parameters.
With respect to claim 21, Woo teaches:
picking the semiconductor die (“electrical component”) up using a collector element (para. 27, Fig. 3, the flip head collet 310 is facing the holding element (downwards away from the rail 318) so as to retrieve the electrical component);
transferring the semiconductor die (“electrical component) from the collector element (308) to a bond-head element (304) (para. 41, When the bond head 302 is at the alignment position, the electrical component is transferred from the flip head collet 310 to the bond head collet 304”);
and bonding the semiconductor die (“electrical component”) to a carrier (bonding pad 606) using the bond-head element (bond head collet 304)
Woo fails to teach:
aligning a semiconductor die with an ejector element;
lifting the semiconductor die up using the ejector element;
performing a measurement of a warpage of the semiconductor die on the bond-head element using a sensor
measuring a tilt of the carrier relative to a horizontal plane using a tilt sensor on the bond-head element before the semiconductor die is bonded to the carrier
and operating a tilt mechanism disposed on corners of a stage holding the carrier to adjust the tilt to level the carrier relative to the horizontal plane while the carrier is on the stage.
Maki teaches:
aligning a semiconductor die (chip 1) with an ejector element (chucking piece 102) (para. 583 “Alignment is made so that the chip 1 concerned is positioned centrally of both chucking piece 102 and chucking collet 105);
lifting a semiconductor die (Fig. 30, chip 1) up from the wafer using an ejector element (block 110c of chucking piece 102);
Pei teaches:
performing a measurement of a warpage of the semiconductor die (para. 48 “the corresponding warpage of the package may be determined by measuring and analyzing the moiré pattern using a defect inspector.”)
Sreenivasan teaches:
performing a measurement of the semiconductor die on the bond-head element using a sensor (para. 50-56 give the order of steps “3. Element pickup 4. Alignment of elements to product substrate and temporary attachment 5. Bonding” para. 47 specifies that the process of alignment uses moire based metrology as used in Pei.)
Choi teaches in Fig. 4:
measuring a tilt of the carrier (substrate 104) relative to a horizontal plane (para. 45 “parallelism between the chip 102 and the substrate 104) using a tilt sensor (claim 13, “air gyro.” It is known in the art that a gyroscope/gyrometer may be used to measure orientation ) on the bond-head element (bonding head 150) (Fig. 4 shows the tilt adjusting driver 156 is on bonding head 150, claim 13 “wherein the tilt adjusting driver comprises an air gyro”), before the semiconductor die (chip 102) is bonded to the carrier (substrate 104) (para. 45 “the controller adjusts the parallelism between the chip 102 and the substrate 104 through the tilt adjusting driver”)
Tsuno teaches:
operating a tilt mechanism to adjust the tilt to level the carrier relative to the horizontal plane. (para. 15 “the room temperature bonding apparatus can use the angle adjustment mechanism to change a direction of the first substrate such that a first surface of the first substrate, which faces to the second substrate, and a second surface of the second substrate, which faces to the first substrate, come into parallel contact with each other”)
Araki teaches in Figs. 4-5:
and operating a tilt mechanism (mechanism 124 including height adjustment posts 126) disposed on corners of a stage (heating and laminating stage 122) holding the carrier while the carrier is on the stage (para. 13 “The tilting mechanism 124 is configured such that the heating and laminating stage 122 is supported by four height adjustment posts 126 that can be moved up and down and are arranged at the four corners of a fixed stage 125 below it, and by changing the height of these four height adjustment posts 126,” “The tilt direction and tilt angle are determined by the control unit 123 so that the lateral shear stress on the wafer 12 caused by the airflow and the sliding stress on the wafer 12 caused by the tilt of the thermal bonding stage 122 are balanced.”)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Maki, Pei, Sreenivasan, Choi, and Tsuno into the method of Woo to lift the die using an ejector element, perform a warpage measurement while the die is attached to the bond head, detecting the tilt of the carrier, and leveling the carrier before bonding. The ordinary artisan would have been motivated to modify Woo in the manner set forth above for the purpose of reducing defects and increase speed in the manufacturing process (para. 29 of Maki), “achiev[ing] sub-100 nm and in some embodiments sub-25 nm or even sub-10 nm alignment in assembly” (Sreenivasan paragraph 47), finding “desired parameters for the composition” (Pei paragraph 48), and “adjusting the parallelism between the chip and the substrate” (para. 45 of Choi) and causing the substrates to come into parallel contact with each other and uniformly impose the larger load on a bonding surface (para. 15 of Tsuno).
It would have been obvious to one of ordinary skill in the art at the time of the invention to further modify the method of Woo/Maki/Pei/Sreenivasan/Choi/Tsuno with the tilt adjustment mechanism of Araki to have the tilt adjustment mechanism attached to the corners of the stage. The claim would have been obvious because the technique of adjusting tilt using an adjustment mechanism attached to the corners of the stage was part of the ordinary capabilities of a person of ordinary skill in the art, in view of the teaching of the technique for improvement as taught by Araki. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
With respect to claim 22, Woo further teaches:
checking a position of the semiconductor die (“electrical component”) before transferring the semiconductor die from the collector element (flip head collet 308) to the bond-head element (bond head collet 304). (para. 29 “the flip head alignment optic 314 is directed downwards towards the flip head collet 310”)
With respect to claim 23, Sreenivasan further teaches in Fig. 10:
wherein picking the semiconductor die (layered silicon 203) up using the collector element (superstrate 1004) further comprises providing a vacuum force (para. 96 “vacuum is pulled through the superstrate 1004) to a channel (vacuum channels 1002) of the collector element to pick up the semiconductor die.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to further incorporate the teachings of Sreenivasan into the method of Woo/Maki/Pei/Sreenivasan/Choi/Tsuno/Araki to use vacuum force in the collector element. The ordinary artisan would have been motivated to modify Woo in the manner set forth above for the purpose of enabling “highly accurate, parallel assembly” (abstract of Sreenivasan.)
With respect to claim 24, Sreenivasan further teaches:
wherein the channel is located at a center of the collector element (Fig. 10 of Sreenivasan, the middle vacuum hole is in the center of the superstrate)
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Woo in view of Sreenivasan as explained above.
With respect to claim 25, Woo further teaches:
wherein the center of the collector element (flip head 308) is misaligned with a center of the semiconductor die (“electrical component). (para. 55 “after the flip head 308 retrieves the electrical component and is inverted back to the second orientation, an image of the electrical component may be captured by the flip head alignment optic 314 and a position of the electrical component relative to the flip head alignment optic 314 may be determined using the captured image. More specifically, an offset of the center of the electrical component from the center of the flip head alignment optic 314 may be determined using the captured image.)
With respect to claim 26,
Woo/Maki/Pei/Sreenivasan/Choi/Tsuno/Araki as applied above fail to teach:
wherein transferring the semiconductor die from the collector element to the bond-head element further comprises providing a vacuum force to a channel of the bond-head element to pick up the semiconductor die.
Sreenivasan further teaches in the embodiment of Fig. 11:
A method in which a semiconductor die is picked up by a superstrate 1004 through vacuum holes 1101. Using this embodiment as the bond-head and the embodiment of Fig. 10 for the collector element as described in claim 21 upon which claim 21 depends meets the limitation:
wherein transferring the semiconductor die (203) from the collector element (1004 in Fig. 10) to the bond-head element (1004 in Fig. 11) further comprises providing a vacuum force to a channel (vacuum hole 1101) of the bond-head element to pick up the semiconductor die (203).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Sreenivasan into the method of Woo to use vacuum force in the bond-head element. The ordinary artisan would have been motivated to modify Woo in the manner set forth above for the purpose of enabling “highly accurate, parallel assembly” (abstract of Sreenivasan.)
With respect to claim 27, Sreenivasan further teaches:
wherein the channel (vacuum hole 1101 of Sreenivasan) is offset from a center of the bond-head element (1104)(Fig. 11 of Sreenivasan).
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Woo in view of Sreenivasan as explained above.
With respect to claim 28, Woo further teaches:
wherein transferring the semiconductor die (“electrical component”) from the collector element (flip head collet 308) to the bond-head element (bond head collet 304) further comprises aligning a center of the bond-head element with a center of the semiconductor die. (para. 41 “The bond head 302 is then moved to the alignment position at which the center of the bond head collet 304 is aligned with the center of the flip head collet 310. When the bond head 302 is at the alignment position, the electrical component is transferred from the flip head collet 310 to the bond head collet 304.”)
Claims 5-8 are rejected under 35 U.S.C. 103 as being unpatentable over Woo (US 2018/0126718 A1) in view of Maki (US 2008/0318346 A1), Pei (US 2016/0126226 A1), Sreenivasan (US 2021/0134640 A1), Choi (US 2023/0163094 A1), Tsuno (US 2011/0011536 A1) and Araki (JP 2002184847 A) as applied to claim 1 above and further in view of Pan (Review of Scientific Instruments 77(4)).
With respect to claim 5, Woo/Maki/Pei/Sreenivasan/Choi fails to teach:
wherein performing the measurement to the warpage of the semiconductor die further comprises moving the sensor relative to the semiconductor die.
However, Pei teaches the use of the moiré interferometry method to measure warpage (para. 47-48).
Pan teaches:
wherein performing the measurement to the warpage (col. 3, para. 2, line 2 “LSCM with moiré method for deformation measurement”) of the semiconductor die further comprises moving (“rotating mirrors mounted on motor”) the sensor (col 3, para. 3, mirrors attached to a motor, pinhole, and CCD target) relative to the semiconductor die (“specimen”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Pan into the method of Woo/Maki/Pei/Sreenivasan/Choi to use a LSCM to measure the moire interference pattern in order to measure warpage and this process involves moving the sensor. The ordinary artisan would have been motivated to modify Woo/Maki/Pei/Sreenivasan/Choi in the manner set forth above for the purpose of using a “high accuracy technique for measuring and observing in-plane microdeformation” (abstract of Pan).
With respect to claim 6, Woo/Maki/Pei/Sreenivasan/Choi/Tsuno/Araki fails to teach:
wherein performing the measurement to the warpage of the semiconductor die further comprises measuring heights of a plurality of points on the semiconductor die, and the number of the points is between about 9 to about 900.
Pan teaches:
wherein performing the measurement to the warpage (scanning of moire patterns with LSCM) of the semiconductor die (specimen) further comprises measuring heights of a plurality of points (scanning lines) on the semiconductor die, and the number of the points is between about 9 to about 900 (the number of scanning lines N can be chosen to be 128, 256, 512).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Pan into the method of Woo/Maki/Pei/Sreenivasan/Choi/Tsuno/Araki to measure 128, 256, or 512 points. The ordinary artisan would have been motivated to modify Woo/Maki/Pei/Sreenivasan/Choi in the manner set forth above for the purpose of effectively and accurately “measuring and observing in-plane microdeformation at micrometer scale.” (abstract of Pan)
With respect to claim 7, Pan further teaches:
wherein the points each have an elongated shape. (Fig. 3 of Pan)
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Woo in view of Pan as explained above.
With respect to claim 8, Pan further teaches:
wherein a length (the shorter length of a scanning line, the pitch = (scan size)/(number of lines)) of each of the points is between about 0.1 µm to about 600 µm (Fig. 4 of Pan includes a scan size of 398.52 µm with 512 scanning lines, for a length of each point of 0.8 µm, within the range)
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Woo in view of Pan as explained above.
Claims 29, 31, and 34 are rejected under 35 U.S.C. 103 as being unpatentable over Woo (US 2018/0126718 A1) in view Pei (US 2016/0126226 A1), Sreenivasan (US 2021/0134640 A1), Choi (US 2023/0163094 A1), Tsuno (US 2011/0011536 A1) and Araki (JP 2002184847 A).
With respect to claim 29, Woo teaches:
A method for forming a semiconductor device, comprising:
picking up a semiconductor die using a bond-head element (para. 41, “the electrical component is transferred from the flip head collet 310 to the bond head collet 304”);
and bonding the semiconductor die (“electrical component”) to a carrier (bonding pad 606) using the bond-head element (bond head collet 304) (para. 51)
Woo fails to teach:
measuring a warpage of the semiconductor die on the bond-head element using a sensor;
measuring a tilt of the carrier relative to a horizontal plane using a tilt sensor on the bond-head element before the semiconductor die is bonded to the carrier
and operating a tilt mechanism disposed on corners of a stage holding the carrier to adjust the tilt to level the carrier relative to the horizontal plane while the carrier is on the stage.
Pei teaches:
performing a measurement of a warpage of the semiconductor die (para. 48 “the corresponding warpage of the package may be determined by measuring and analyzing the moiré pattern using a defect inspector.”)
Sreenivasan teaches:
performing a measurement of the semiconductor die on the bond-head element using a sensor (para. 50-56 give the order of steps “3. Element pickup 4. Alignment of elements to product substrate and temporary attachment 5. Bonding” para. 47 specifies that the process of alignment uses moire based metrology as used in Pei.)
Choi teaches in Fig. 4:
measuring the tilt of the carrier (substrate 104) relative to a horizontal plane (para. 45 “parallelism between the chip 102 and the substrate 104) using a tilt sensor (claim 13, “air gyro.” It is known in the art that a gyroscope/gyrometer may be used to measure orientation ) on the bond-head element (bonding head 150) (Fig. 4 shows the tilt adjusting driver 156 is on bonding head 150, claim 13 “wherein the tilt adjusting driver comprises an air gyro”), before the semiconductor die (chip 102) is bonded to the carrier (substrate 104) (para. 45 “the controller adjusts the parallelism between the chip 102 and the substrate 104 through the tilt adjusting driver”)
Tsuno teaches:
operating a tilt mechanism to adjust the tilt to level the carrier relative to the horizontal plane. (para. 15 “the room temperature bonding apparatus can use the angle adjustment mechanism to change a direction of the first substrate such that a first surface of the first substrate, which faces to the second substrate, and a second surface of the second substrate, which faces to the first substrate, come into parallel contact with each other”)
Araki teaches in Figs. 4-5:
and operating a tilt mechanism (mechanism 124 including height adjustment posts 126) disposed on corners of a stage (heating and laminating stage 122) holding the carrier (wafer 12) while the carrier (12) is on the stage (para. 13 “The tilting mechanism 124 is configured such that the heating and laminating stage 122 is supported by four height adjustment posts 126 that can be moved up and down and are arranged at the four corners of a fixed stage 125 below it, and by changing the height of these four height adjustment posts 126,” “The tilt direction and tilt angle are determined by the control unit 123 so that the lateral shear stress on the wafer 12 caused by the airflow and the sliding stress on the wafer 12 caused by the tilt of the thermal bonding stage 122 are balanced.”)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Pei, Sreenivasan, Choi, and Tsuno into the method of Woo to perform a warpage measurement while the die is attached to the bond head. The ordinary artisan would have been motivated to modify Woo in the manner set forth above for the purpose of “achiev[ing] sub-100 nm and in some embodiments sub-25 nm or even sub-10 nm alignment in assembly” (Sreenivasan paragraph 47), and finding “desired parameters for the composition” (Pei paragraph 48), “adjusting the parallelism between the chip and the substrate” (para. 45 of Choi), and causing the substrates to come into parallel contact with each other and uniformly impose the larger load on a bonding surface (para. 15 of Tsuno).
It would have been obvious to one of ordinary skill in the art at the time of the invention to further modify the method of Woo/Pei/Sreenivasan/Choi/Tsuno with the tilt adjustment mechanism of Araki to have the tilt adjustment mechanism attached to the corners of the stage. The claim would have been obvious because the technique of adjusting tilt using an adjustment mechanism attached to the corners of the stage was part of the ordinary capabilities of a person of ordinary skill in the art, in view of the teaching of the technique for improvement as taught by Araki. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
With respect to claim 31, Pei further teaches that the method of measuring warpage is by emitting a moire pattern (para. 48 “the corresponding warpage of the package may be determined by measuring and analyzing the moiré pattern using a defect inspector.”)
Therefore, modifying Woo by Pei, Sreenivasan, and Choi as described with respect to claim 29 upon which claim 31 depends above meets the limitation:
wherein measuring the warpage of the semiconductor die on the bond-head element comprises emitting a moir6 pattern from the sensor to measure a profile of the semiconductor die.
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Woo in view of Pei as explained above.
With respect to claim 34, Choi further teaches:
wherein the tilt sensor and the tilt mechanism operate before and after the semiconductor die is bonded to the carrier (para. 45 “As the chip 102 reaches a bonding position with the substrate, the bonding head 150 corrects for any position error by adjusting a theta axis through the theta axis driver 152 (refer to FIG. 4 ) “, “Thereafter (or at the same time, or just before), the controller adjusts the parallelism between the chip 102 and the substrate 104 through the tilt adjusting driver”).
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Woo in view of Choi as explained above.
Claims 30 is rejected under 35 U.S.C. 103 as being unpatentable over Woo (US 2018/0126718 A1) in view of Pei (US 2016/0126226 A1), Sreenivasan (US 2021/0134640 A1), Choi (US 2023/0163094 A1), Tsuno (US 2011/0011536 A1) and Araki (JP 2002184847 A) as applied to claim 29 above and further in view of Pan (Review of Scientific Instruments 77(4)).
With respect to claim 30, Woo/Pei/Sreenivasan/Choi/Tsuno/Araki are silent to:
wherein the sensor is movable, and measuring the warpage of the semiconductor die on the bond-head element comprises measuring heights of different points on a bottom surface of the semiconductor die using the movable sensor
Pan teaches
wherein the sensor (col 3, para. 3, mirrors attached to a motor, pinhole, and CCD target) is movable (“rotating mirrors mounted on motor”), and measuring the warpage (scanning of moire patterns with LSCM) of the semiconductor die (specimen) on the bond-head element comprises measuring heights of different points (scanning lines) on a bottom surface of the semiconductor die using the movable sensor (mirrors scan the laser across the specimen located in the front focus of microscope.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Pan into the method of Woo/Pei/Sreenivasan/Choi/Tsuno/Araki to use a movable sensor to measure different points on the surface of a semiconductor die. The ordinary artisan would have been motivated to modify Woo/Pei/Sreenivasan in the manner set forth above for the purpose of effectively and accurately “measuring and observing in-plane microdeformation at micrometer scale.” (abstract of Pan)
Claims 32 is rejected under 35 U.S.C. 103 as being unpatentable over Woo (US 2018/0126718 A1) in view of Pei (US 2016/0126226 A1), Sreenivasan (US 2021/0134640 A1) , Choi (US 2023/0163094 A1) Tsuno (US 2011/0011536 A1) and Araki (JP 2002184847 A) as applied to claim 29 above and further in view of Bai (Sensors 19(16), page 3592)
With respect to claim 32, Woo/Pei/Sreenivasan/Choi/Tsuno/Araki fail to teach:
wherein the sensor comprises a chromatic focal lens configured to measure light reflected from a plurality of portions of the semiconductor die to determine the warpage of the semiconductor die
Bai teaches:
wherein the sensor comprises a chromatic focal lens (chromatic confocal technology) configured to measure light reflected from a plurality of portions of the semiconductor die to determine the warpage of the semiconductor die (“Chromatic confocal technology (CCT) is one of the most promising methods for the contactless and accurate measurement of structure profiles. Based on the principles of chromatic dispersion and confocal theory, a dispersion probe is proposed and optimized with several commercial and cheap refractive index lenses”)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Bai into the method of Woo/Pei/Sreenivasan/Choi/Tsuno/Araki to use a chromatic focal lens in the sensor. The ordinary artisan would have been motivated to modify Woo in the manner set forth above for the purpose of making “contactless and accurate measurement of structure profiles.” (abstract of Bai).
Response to Arguments
Applicant’s arguments filed December 5, 2025 with respect to claim objections are persuasive. Claim objections are withdrawn in view of amendments.
Applicant's arguments filed December 5, 2025 have been fully considered but they are not persuasive.
In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Applicant argues that the prior art of record does not teach the limitation:
“operating a tilt mechanism disposed on corners of a stage holding the carrier to adjust the tilt to level the carrier relative to the horizontal plane while the carrier is on the stage.”
A combination of Tsuno and Araki are relied upon to teach the above limitation in the rejections of the independent claims.
Tsuno is used to teach “operating a tilt mechanism (angle adjustment mechanism) to adjust the tilt to level the carrier relative to the horizontal plane (parallel plane at which substrates make contact).” Para. 15 of Tsuno recites “the room temperature bonding apparatus can use the angle adjustment mechanism to change a direction of the first substrate such that a first surface of the first substrate, which faces to the second substrate, and a second surface of the second substrate, which faces to the first substrate, come into parallel contact with each other.” Tsuno uses a different mechanism for the tilt and does not teach the limitation that the tilt mechanism is disposed on corners of a stage.
Araki is used to teach that the tilt mechanism is disposed on corners of a stage although the purpose of using the tilt mechanism is different and therefore the stage is not level relative to a horizontal plane.
Combining the teachings of Tsuno in which a tilt mechanism levels a stage relative to a horizontal stage in order to align substrates for bonding with the teachings of Araki in which the tilt mechanism is one in which the mechanism is disposed on corners of the stage as described above in the rejections to the independent claims renders obvious the limitation:
“operating a tilt mechanism disposed on corners of a stage holding the carrier to adjust the tilt to level the carrier relative to the horizontal plane while the carrier is on the stage.”
Therefore, elements of the limitation are known in the prior art and the rejection is maintained.
Conclusion
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/A.M.W./Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897