DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1, 7, 21, 27-30, 32-33, 35-40 and 42-48 are pending in this application. Claims 2-6, 8-20, 22-26, 31, 34 and 41 were cancelled as set forth in the applicant’s response filed on 3/27/2026.
Prior rejection of Claims 30, 35 and 40 under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, are withdrawn in view of amendments to those claims.
Prior rejection of Claims 21, 27-30, 32 and 43-44 under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, are withdrawn in view of amendments to claim 21.
Prior rejection of Claim 28, 30, 38, 40, 43 and 45 under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, are withdrawn in view of amendments to claims 28 and 38.
Prior rejection of Claim 32 under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, is withdrawn in view of amendments to claim 32.
Information Disclosure Statement
Acknowledgement is made of Applicant's Information Disclosure Statement (IDS) from PTO-1449. The IDS has been considered.
Drawings
Prior objection to drawing is withdrawn in view of corrected drawing of Fig. 11.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 29 and 39 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 29 recites the limitation “the first semiconductor material” and “the second semiconductor material” in lines 2-3. There is insufficient antecedent basis for this limitation in the claim. Claim 29 depends from claim 21 and “a first semiconductor material” or “a second semiconductor material” is not defined in claim 21.
Claim 39 recites the limitation “the first semiconductor material” and “the second semiconductor material” in lines 2-3. There is insufficient antecedent basis for this limitation in the claim. Claim 39 depends from claim 7 and “a first semiconductor material” or “a second semiconductor material” is not defined in claim 7.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1 and 36-37 are rejected under 35 U.S.C. 103 as being unpatentable over Zeng et al. (US 2018/0366569 A1, of record), and further in view of Eriksen et al. (US 2003/0036247 A1, of record) and Miura et al. (US 2006/0169987 A1, of record).
Re Claim 1, Zeng teaches a method of making a semiconductor device , comprising:
forming a first semiconductor layer (102, Fig. 27A, para [0084]) comprising silicon carbide (layer 102 is SiC, Fig. 27A);
disposing a first surface of a second semiconductor layer comprising silicon (layer 144’, which is silicon, Fig. 27A, para [0084]) in contact with a first surface of the first semiconductor layer (top surface of 102, Fig. 27A).
Zeng teaches that the first semiconductor layer 102 is formed from an epitaxial process. Hence, it does not teach that the layer is formed separately on a different substrate.
However, related art Eriksen teaches a method of making an improved SiC layer with low defect density, which can then be bonded to fabricate integrated electronics, temperature sensors and other electronics (para [0017]). Eriksen teaches:
providing a first substrate comprising silicon (202, which is made of silicon, Figs. 2A-2E, para [0030]) and including a surface (top surface of 202);
forming a first semiconductor layer comprising silicon carbide (105, SiC layer, Fig. 2B, para [0030]) over the surface of the first substrate (top surface of 202) by,
(a) forming a sacrificial layer (103, Fig. 2B, para [0030]) comprising silicon carbide (103 is part of 104 layer which is a SiC layer, para [0030]) in contact with the surface of the first substrate (top surface of 202), and
(b) forming the first semiconductor layer (105, Fig. 2B) in contact with the sacrificial layer (103, Fig. 2B) with defects being formed in the sacrificial layer (defects are formed within the layer 103, similar to layer 3 in Fig. 1B, para [0023]) leaving the first semiconductor layer as substantially defect free (para [0023]);
removing the sacrificial layer (103) and first substrate (202) leaving the first semiconductor layer (110; note that 110 is the portion of 105 that is separated from the substrate and sacrificial layers, para [0032], Figs. 2D-2G) as substantially defect free (para [0023]);
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to replace the epitaxially grown SiC layer of Zeng with the SiC layer of Eriksen, as they are art recognized well-known alternative processes of making SiC layer for a transistor device. The substitution of a known process for its known purpose to yield predictable results is prima facie obvious. Also see KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007). Additionally, the selection of a known process based on its suitability for its intended use supports a prima facie obviousness determination as established in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945), see MPEP 2144.07.
Eriksen does not disclose that the substrate (202) has a patterned surface and that defects are being formed in the patterned surface of the first substrate.
However, in a related semiconductor field of art, Miura discloses a silicon substrate with patterned surface (1, Fig. 1, para [0051]) and a buffer layer (4, Fig. 1, para [0051]) on top of the substrate, which in combination decreases the density of defects in the SiC layer (5, Fig. 1, para [0051]) that would be grown on top of the Si substrate (paras [0051] – [0052]). The patterned grooves comprise of mirror-symmetrical facets which lead to the defects themselves being mirror-symmetrical to each other, and the paired defects meeting together and disappearing, thus realizing a high-quality SiC layer with extremely low defects (paras [0047] - [0049], Fig. 1).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to modify the first substrate of Eriksen by patterning the top surface of the Si substrate as disclosed by Miura, for realizing a high-quality SiC layer with extremely low defects (paras [0047] - [0049], Miura). The patterned grooves on the top surface of the silicon substrate of Eriksen modified by Miura, would comprise of mirror-symmetrical facets resulting in generated defects themselves being mirror-symmetrical to each other, and the paired defects meeting together and disappearing within the sacrificial layer of Eriksen (similar to the buffer layer of Miura), thus realizing a high-quality SiC layer with extremely low defects (paras [0047] - [0049], Fig. 1, Miura).
Re Claim 36, Zeng modified by Eriksen and Miura teaches the method of claim 1, further including:
providing a second substrate (100, Fig. 27A, para [0040], Zeng) with a buffer layer (101, Fig. 27A, para [0040], Zeng) in contact with a first surface of the second substrate (top surface of 100);
disposing the first semiconductor layer (102, Fig. 27A, Zeng) and second semiconductor layer (144’, Fig. 27A, Zeng) over the buffer layer (101); and
forming an electrical component (transistor device, Fig. 27A, para [0084], Zeng) at least partially within the second semiconductor layer (144’, Zeng).
Re Claim 37, Zeng modified by Eriksen and Miura teaches the method of claim 1, further including forming a compliant layer (204, Fig. 2B, para [0030], Eriksen) over a second surface of the first substrate (bottom surface of 202, Fig. 2B, Eriksen) opposite the patterned surface of the first substrate (top surface of 202, Fig. 2B, Eriksen modified by Miura).
Claims 33 and 35 are rejected under 35 U.S.C. 103 as being unpatentable over Zeng et al. (US 2018/0366569 A1, of record), Eriksen et al. (US 2003/0036247 A1, of record) and Miura et al. (US 2006/0169987 A1, of record), as applied to claim 36 above, and further in view of Lipkin et al. (US 2002/0153594 A1, of record).
Re Claim 33, Zeng modified by Eriksen and Miura teaches the method of claim 36, but does not explicitly disclose that the buffer layer (101, Fig. 27A, Zeng) provides characteristics of radiation hardening.
However, in a related semiconductor field, Lipkin discloses that silicon carbide provides significant advantages due to its excellent electronic properties, such as radiation hardness (para [0003]).
It would be obvious to one of ordinary skill in the art that the buffer layer as disclosed by Zeng which is also made of silicon carbide (101 is SiC, para [0040], Zeng), will have the characteristics of radiation hardening as disclosed by Lipkin. Where applicant claims a composition in terms of a function, property or characteristic and the composition of the prior art is the same as that of the claim but the function is not explicitly disclosed by the reference, the examiner may make a rejection under both 35 U.S.C. 102 and 103. “There is nothing inconsistent in concurrent rejections for obviousness under 35 U.S.C. 103 and for anticipation under 35 U.S.C. 102.” In re Best, 562 F.2d 1252, 1255 n.4, 195 USPQ 430, 433 n.4 (CCPA 1977). This same rationale should also apply to product, apparatus, and process claims claimed in terms of function, property or characteristic (see MPEP 2112-III).
Re Claim 35, Zeng modified by Eriksen, Miura and Lipkin teaches the method of claim 33, but does not disclose that the buffer layer provides at least a portion of radiation hardening of at least 87 Mev cm2/mg.
However, Zeng modified by Eriksen, Miura and Lipkin teaches the same structure as recited in the claim including the buffer layer, which is also made of the same material (silicon carbide) as disclosed in the applicant’s specification. Additionally, Lipkin discloses that silicon carbide provides significant advantages due to its excellent electronic properties, such as radiation hardness (para [0003]).
It would be obvious to one of ordinary skill in the art that the semiconductor structure as disclosed by Zeng modified by Eriksen, Miura and Lipkin which comprises silicon carbide buffer layer, will have the characteristics of radiation hardening as disclosed by Lipkin, and will have the same strength of radiation hardening as disclosed in the claimed limitation because of the same structure as disclosed by prior art Zeng. Where applicant claims a composition in terms of a function, property or characteristic and the composition of the prior art is the same as that of the claim but the property or characteristic is not explicitly disclosed by the reference, the examiner may make a rejection under both 35 U.S.C. 102 and 103. “There is nothing inconsistent in concurrent rejections for obviousness under 35 U.S.C. 103 and for anticipation under 35 U.S.C. 102.” In re Best, 562 F.2d 1252, 1255 n.4, 195 USPQ 430, 433 n.4 (CCPA 1977). This same rationale should also apply to product, apparatus, and process claims claimed in terms of function, property or characteristic (see MPEP 2112-III).
Claim 48 is rejected under 35 U.S.C. 103 as being unpatentable over Zeng et al. (US 2018/0366569 A1, of record), Eriksen et al. (US 2003/0036247 A1, of record) and Miura et al. (US 2006/0169987 A1, of record), as applied to claim 36 above, and further in view of Nagasawa et al. (US 2011/0006310 A1, of record).
Re Claim 48, Zeng modified by Eriksen and Miura teaches the method of claim 36, but Zeng does not explicitly disclose forming the buffer layer (101 SiC layer, Fig. 27A, para [0040], Zeng) includes forming alternating layers of silicon and carbon.
Related art, Nagasawa teaches that a SiC layer is formed by alternating layers of silicon and carbon (Fig. 5, para [0267]).
It would be obvious to one of ordinary skill in the art that the buffer layer as disclosed by Zeng which is also made of silicon carbide (101 is SiC, para [0040], Zeng), will be formed by alternating layers of silicon and carbon as disclosed by Nagasawa. Where applicant claims a composition in terms of a function, property or characteristic and the composition of the prior art is the same as that of the claim but the function is not explicitly disclosed by the reference, the examiner may make a rejection under both 35 U.S.C. 102 and 103. “There is nothing inconsistent in concurrent rejections for obviousness under 35 U.S.C. 103 and for anticipation under 35 U.S.C. 102.” In re Best, 562 F.2d 1252, 1255 n.4, 195 USPQ 430, 433 n.4 (CCPA 1977). This same rationale should also apply to product, apparatus, and process claims claimed in terms of function, property or characteristic (see MPEP 2112-III).
Claims 7, 38 and 42 are rejected under 35 U.S.C. 103 as being unpatentable over Zeng et al. (US 2018/0366569 A1, of record), and further in view of Eriksen et al. (US 2003/0036247 A1, of record) and Miura et al. (US 2006/0169987 A1, of record).
Re Claim 7, Zeng teaches a method of making a semiconductor device, comprising:
forming a first semiconductor layer (102, Fig. 27A, para [0084]) comprising silicon carbide (layer 102 is SiC, Fig. 27A);
disposing a first surface of a second semiconductor layer comprising silicon (layer 144’, which is silicon, Fig. 27A, para [0084]) over a first surface of the first semiconductor layer (top surface of 102, Fig. 27A);
providing a second substrate (100+101, Fig. 27A, para [0040]);
disposing the first semiconductor layer (102, Fig. 27A) and second semiconductor layer (144’, Fig. 27A) over the second substrate (100+101, Fig. 27A) with a second surface of the first semiconductor layer (bottom surface of 102, Fig. 27A) in contact with a surface of the second substrate (top surface of 100+101, Fig. 27A); and
forming an electrical component (transistor device, Fig. 27A, para [0084]) at least partially within the second semiconductor layer (144’).
Zeng teaches that the first semiconductor layer 102 is formed from an epitaxial process. Hence, it does not teach that the layer is formed separately on a different substrate.
However, related art Eriksen teaches a method of making an improved SiC layer with low defect density, which can then be bonded to fabricate integrated electronics, temperature sensors and other electronics (para [0017]). Eriksen teaches:
providing a first substrate comprising silicon (202, which is made of silicon, Figs. 2A-2E, para [0030]) including a surface (top surface of 202);
forming a first semiconductor layer comprising silicon carbide (105, SiC layer, Fig. 2B, para [0030]) over the surface of the first substrate (top surface of 202) by,
(a) forming a sacrificial layer (103, Fig. 2B, para [0030]) comprising silicon carbide (103 is part of 104 layer which is a SiC layer, para [0030]) in contact with the surface of the first substrate (top surface of 202), and
(b) forming the first semiconductor layer (105, Fig. 2B) in contact with the sacrificial layer (103, Fig. 2B) with defects being formed in the sacrificial layer (defects are formed within the layer 103, similar to layer 3 in Fig. 1B, para [0023]) leaving the first semiconductor layer as substantially defect free (para [0023]);
removing the sacrificial layer (103) and first substrate (202) leaving the first semiconductor layer (110; note that 110 is the portion of 105 that is separated from the substrate and sacrificial layers, para [0032], Figs. 2D-2G) as substantially defect free (para [0023]);
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to replace the epitaxially grown SiC layer of Zeng with the SiC layer of Eriksen, as they are art recognized well-known alternative processes of making SiC layer for a transistor device. The substitution of a known process for its known purpose to yield predictable results is prima facie obvious. Also see KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007). Additionally, the selection of a known process based on its suitability for its intended use supports a prima facie obviousness determination as established in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945), see MPEP 2144.07.
Eriksen does not disclose that the substrate (202) has a patterned surface and that defects are being formed in the patterned surface of the first substrate.
However, in a related semiconductor field of art, Miura discloses a silicon substrate with patterned surface (1, Fig. 1, para [0051]) and a buffer layer (4, Fig. 1, para [0051]) on top of the substrate, which in combination decreases the density of defects in the SiC layer (5, Fig. 1, para [0051]) that would be grown on top of the Si substrate (paras [0051] – [0052]). The patterned grooves comprise of mirror-symmetrical facets which lead to the defects themselves being mirror-symmetrical to each other, and the paired defects meeting together and disappearing, thus realizing a high-quality SiC layer with extremely low defects (paras [0047] - [0049], Fig. 1).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to modify the first substrate of Eriksen by patterning the top surface of the Si substrate as disclosed by Miura, for realizing a high-quality SiC layer with extremely low defects (paras [0047] - [0049], Miura). The patterned grooves on the top surface of the silicon substrate of Eriksen modified by Miura, would comprise of mirror-symmetrical facets resulting in generated defects themselves being mirror-symmetrical to each other, and the paired defects meeting together and disappearing within the sacrificial layer of Eriksen (similar to the buffer layer of Miura), thus realizing a high-quality SiC layer with extremely low defects (paras [0047] - [0049], Fig. 1, Miura).
Re Claim 38, Zeng modified by Eriksen and Miura teaches the method of claim 7, wherein the second substrate (100+101, Fig. 27A, Zeng) includes a buffer layer (101, Fig. 27A, Zeng) in contact with the second surface of the first semiconductor layer (bottom surface of 102, Fig. 27A, Zeng).
Re Claim 42, Zeng modified by Eriksen and Miura teaches the method of claim 7, further including forming a compliant layer (204, Fig. 2B, para [0030], Eriksen) over a second surface of the first substrate (bottom surface of 202, Fig. 2B, Eriksen) opposite the patterned surface of the first substrate (top surface of 202, Fig. 2B, Eriksen modified by Miura).
Claim 40 is rejected under 35 U.S.C. 103 as being unpatentable over Zeng et al. (US 2018/0366569 A1, of record), Eriksen et al. (US 2003/0036247 A1, of record) and Miura et al. (US 2006/0169987 A1, of record), as applied to claim 38 above, and further in view of Lipkin et al. (US 2002/0153594 A1, of record).
Re Claim 40, Zeng modified by Eriksen and Miura teaches the method of claim 38, but does not disclose that the buffer layer provides at least a portion of radiation hardening of at least 87 Mev cm2/mg.
However, Zeng modified by Eriksen and Miura teaches the same structure as recited in the claim including the buffer layer (101, Fig. 27A, Zeng), which is also made of the same material (silicon carbide) as disclosed in the applicant’s specification. Additionally, Lipkin discloses that silicon carbide provides significant advantages due to its excellent electronic properties, such as radiation hardness (para [0003]).
It would be obvious to one of ordinary skill in the art that the semiconductor structure as disclosed by Zeng modified by Eriksen and Miura which comprises silicon carbide buffer layer, will have the characteristics of radiation hardening as disclosed by Lipkin, and will have the same strength of radiation hardening as disclosed in the claimed limitation because of the same structure as disclosed by prior art Zeng. Where applicant claims a composition in terms of a function, property or characteristic and the composition of the prior art is the same as that of the claim but the property or characteristic is not explicitly disclosed by the reference, the examiner may make a rejection under both 35 U.S.C. 102 and 103. “There is nothing inconsistent in concurrent rejections for obviousness under 35 U.S.C. 103 and for anticipation under 35 U.S.C. 102.” In re Best, 562 F.2d 1252, 1255 n.4, 195 USPQ 430, 433 n.4 (CCPA 1977). This same rationale should also apply to product, apparatus, and process claims claimed in terms of function, property or characteristic (see MPEP 2112-III).
Claim 45 is rejected under 35 U.S.C. 103 as being unpatentable over Zeng et al. (US 2018/0366569 A1, of record), Eriksen et al. (US 2003/0036247 A1, of record) and Miura et al. (US 2006/0169987 A1, of record), as applied to claim 38 above, and further in view of Nagasawa et al. (US 2011/0006310 A1, of record).
Re Claim 45, Zeng modified by Eriksen and Miura teaches the method of claim 38, but Zeng does not explicitly disclose forming the buffer layer (101 SiC layer, Fig. 27A, para [0040], Zeng) includes forming alternating layers of silicon and carbon.
Related art, Nagasawa teaches that a SiC layer is formed by alternating layers of silicon and carbon (Fig. 5, para [0267]).
It would be obvious to one of ordinary skill in the art that the buffer layer as disclosed by Zeng which is also made of silicon carbide (101 is SiC, para [0040], Zeng), will be formed by alternating layers of silicon and carbon as disclosed by Nagasawa. Where applicant claims a composition in terms of a function, property or characteristic and the composition of the prior art is the same as that of the claim but the function is not explicitly disclosed by the reference, the examiner may make a rejection under both 35 U.S.C. 102 and 103. “There is nothing inconsistent in concurrent rejections for obviousness under 35 U.S.C. 103 and for anticipation under 35 U.S.C. 102.” In re Best, 562 F.2d 1252, 1255 n.4, 195 USPQ 430, 433 n.4 (CCPA 1977). This same rationale should also apply to product, apparatus, and process claims claimed in terms of function, property or characteristic (see MPEP 2112-III).
Claims 21, 27-28 and 32 are rejected under 35 U.S.C. 103 as being unpatentable over Zeng et al. (US 2018/0366569 A1, of record), and further in view of Eriksen et al. (US 2003/0036247 A1, of record).
Re Claim 21, Zeng teaches a method of making a semiconductor device, comprising:
forming a first semiconductor layer (102, Fig. 27A, para [0084]) comprising silicon carbide (layer 102, which is SiC, Fig. 27A);
disposing a first surface of a second semiconductor layer (layer 144’, which is silicon, Fig. 27A, para [0084]) over a first surface of the first semiconductor layer (top surface of 102, Fig. 27A);
providing a second substrate (100+101, Fig. 27A, para [0040]);
disposing the first semiconductor layer (102, Fig. 27A, Zeng) and second semiconductor layer (144’, Fig. 27A, Zeng) over the second substrate (top surface of 100+101, Fig. 27A) with a second surface of the first semiconductor layer (bottom surface of 102, Fig. 27A) in contact with a surface of the second substrate (top surface of 100+101, Fig. 27A); and
forming an electrical component (transistor device, Fig. 27A, para [0084]) at least partially within the second semiconductor layer (144’).
Zeng teaches that the first semiconductor layer 102 is formed from an epitaxial process. Hence, it does not teach that the layer is formed separately on a different substrate.
However, related art Eriksen teaches a method of making an improved SiC layer with low defect density, which can then be bonded to fabricate integrated electronics, temperature sensors and other electronics (para [0017]). Eriksen teaches:
providing a first substrate comprising silicon (202, which is made of silicon, Figs. 2A-2E, para [0030]);
forming a first semiconductor layer comprising silicon carbide (105, SiC layer, Fig. 2B, para [0030]) over a first surface of the first substrate by (top surface of 202),
(a) forming a sacrificial layer (103, Fig. 2B, para [0030]) comprising silicon carbide (103 is part of 104 layer which is a SiC layer, para [0030]) in contact with the first surface of the first substrate (top surface of 202, see Fig. 2B), and
(b) forming the first semiconductor layer (105, Fig. 2B) in contact with the sacrificial layer (103, Fig. 2B) with defects being formed in the sacrificial layer (defects are formed within the layer 103, similar to layer 3 in Fig. 1B, para [0023]) leaving the first semiconductor layer as substantially defect free (para [0023]);
removing the sacrificial layer (103) and first substrate (202) leaving the first semiconductor layer (110; note that 110 is the portion of 105 that is separated from the substrate and sacrificial layers, para [0032], Figs. 2D-2G) as substantially defect free (para [0023]);
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to replace the epitaxially grown SiC layer of Zeng with the SiC layer of Eriksen, as they are art recognized well-known alternative processes of making SiC layer for a transistor device. The substitution of a known process for its known purpose to yield predictable results is prima facie obvious. Also see KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007). Additionally, the selection of a known process based on its suitability for its intended use supports a prima facie obviousness determination as established in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945), see MPEP 2144.07.
Re Claim 27, Zeng modified by Eriksen teaches the method of claim 21, further wherein forming the electrical component includes forming a MOSFET device (MOSFET device, Fig. 27A, para [0084], Zeng).
Re Claim 28, Zeng modified by Eriksen teaches the method of claim 21, wherein the second substrate (100+101, Fig. 27A, Zeng) includes a buffer layer (101, Fig. 27A, Zeng) in contact with the second surface of the first semiconductor layer (bottom surface of 102, Fig. 27A, Zeng).
Re Claim 32, Zeng modified by Eriksen teaches the method of claim 21, further including forming a compliant layer (204, Fig. 2B, para [0030], Eriksen) over a second surface of the first substrate (bottom surface of 202, Fig. 2B, Eriksen) opposite the first surface of the first substrate (top surface of 202, Fig. 2B, Eriksen).
Claim 30 is rejected under 35 U.S.C. 103 as being unpatentable over Zeng et al. (US 2018/0366569 A1, of record) and Eriksen et al. (US 2003/0036247 A1, of record), as applied to claim 28 above, and further in view of Lipkin et al. (US 2002/0153594 A1, of record).
Re Claim 30, Zeng modified by Eriksen teaches the method of claim 28, but does not disclose that the buffer layer contributes to radiation hardening of at least 87 Mev cm2/mg.
However, Zeng modified by Eriksen teaches the same structure as recited in the claim including the buffer layer (101, Fig. 27A, Zeng), which is also made of the same material (silicon carbide) as disclosed in the applicant’s specification. Additionally, Lipkin discloses that silicon carbide provides significant advantages due to its excellent electronic properties, such as radiation hardness (para [0003]).
It would be obvious to one of ordinary skill in the art that the semiconductor structure as disclosed by Zeng modified by Eriksen which comprises silicon carbide buffer layer, will have the characteristics of radiation hardening as disclosed by Lipkin, and will have the same strength of radiation hardening as disclosed in the claimed limitation because of the same structure as disclosed by prior art Zeng. Where applicant claims a composition in terms of a function, property or characteristic and the composition of the prior art is the same as that of the claim but the property or characteristic is not explicitly disclosed by the reference, the examiner may make a rejection under both 35 U.S.C. 102 and 103. “There is nothing inconsistent in concurrent rejections for obviousness under 35 U.S.C. 103 and for anticipation under 35 U.S.C. 102.” In re Best, 562 F.2d 1252, 1255 n.4, 195 USPQ 430, 433 n.4 (CCPA 1977). This same rationale should also apply to product, apparatus, and process claims claimed in terms of function, property or characteristic (see MPEP 2112-III).
Claim 43 is rejected under 35 U.S.C. 103 as being unpatentable over Zeng et al. (US 2018/0366569 A1, of record) and Eriksen et al. (US 2003/0036247 A1, of record) as applied to claim 28 above, and further in view of Nagasawa et al. (US 2011/0006310 A1, of record).
Re Claim 43, Zeng modified by Eriksen teaches the method of claim 28, but Zeng does not explicitly disclose forming the buffer layer (101 SiC layer, Fig. 27A, para [0040], Zeng) includes forming alternating layers of silicon and carbon.
Related art, Nagasawa teaches that a SiC layer is formed by alternating layers of silicon and carbon (Fig. 5, para [0267]).
It would be obvious to one of ordinary skill in the art that the buffer layer as disclosed by Zeng which is also made of silicon carbide (101 is SiC, para [0040], Zeng), will be formed by alternating layers of silicon and carbon as disclosed by Nagasawa. Where applicant claims a composition in terms of a function, property or characteristic and the composition of the prior art is the same as that of the claim but the function is not explicitly disclosed by the reference, the examiner may make a rejection under both 35 U.S.C. 102 and 103. “There is nothing inconsistent in concurrent rejections for obviousness under 35 U.S.C. 103 and for anticipation under 35 U.S.C. 102.” In re Best, 562 F.2d 1252, 1255 n.4, 195 USPQ 430, 433 n.4 (CCPA 1977). This same rationale should also apply to product, apparatus, and process claims claimed in terms of function, property or characteristic (see MPEP 2112-III).
Allowable Subject Matter
Claims 44, 46 and 47 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 44 would be allowable for the for the following reasons. Most of the limitations are taught by Zeng et al. (US 2018/0366569 A1, of record), which includes:
forming a trench (gate trench 110, Fig. 27A, also see Fig. 4, para [0045], Zeng) through the second semiconductor layer (144’, Fig. 27A, Zeng) and extending into the first semiconductor layer (102, Fig. 27A, Zeng);
forming a first column of semiconductor material having a first conductivity type (“P region” in layer 144’, Fig. 27A, Zeng) and extending through the second semiconductor layer (144’, Fig. 27A);
forming a source region (142, Fig. 27A, para [0034], Zeng) over the first column of semiconductor material (“P region” in layer 144’, Fig. 27A, Zeng).
However, Zeng does not disclose the limitation wherein, “forming a second column of semiconductor material having a second conductivity type opposite the first conductivity type (P-type) and in contact with a side surface of the first column of semiconductor material within the second semiconductor layer opposite the trench”. Zeng discloses the second semiconductor layer (144’, Fig. 27A, Zeng) and the first column of semiconductor material with first conductivity type (“P region” in layer 144’, Fig. 27A, Zeng) within the second semiconductor layer (144’, Fig. 27A). The only N-type region (second conductivity) within the second semiconductor layer 144’, is the source region 142, and there is no additional second column of N-type within 144’ which is in contact with a side surface of the first column of semiconductor material (“P region” in layer 144’) and also within the second semiconductor layer opposite the trench. Therefore, in the Examiner’s opinion, the above limitation is neither anticipated nor made obvious by the prior art of record, when viewed in the context of the independent claim 21, as a whole.
Claim 46 would be allowable for the for the following reasons. Most of the limitations are taught by Zeng et al. (US 2018/0366569 A1, of record), which includes:
forming a trench (gate trench 110, Fig. 27A, also see Fig. 4, para [0045], Zeng) through the second semiconductor layer (144’, Fig. 27A, Zeng) and extending into the first semiconductor layer (102, Fig. 27A, Zeng);
forming a first column of semiconductor material having a first conductivity type (“P region” in layer 144’, Fig. 27A, Zeng) and extending through the second semiconductor layer (144’, Fig. 27A);
forming a source region (142, Fig. 27A, para [0034], Zeng) over the first column of semiconductor material (“P region” in layer 144’, Fig. 27A, Zeng).
However, Zeng does not disclose the limitation wherein, “forming a second column of semiconductor material having a second conductivity type opposite the first conductivity type (P-type) and in contact with a side surface of the first column of semiconductor material within the second semiconductor layer opposite the trench”. Zeng discloses the second semiconductor layer (144’, Fig. 27A, Zeng) and the first column of semiconductor material with first conductivity type (“P region” in layer 144’, Fig. 27A, Zeng) within the second semiconductor layer (144’, Fig. 27A). The only N-type region (second conductivity) within the second semiconductor layer 144’, is the source region 142, and there is no additional second column of N-type within 144’ which is in contact with a side surface of the first column of semiconductor material (“P region” in layer 144’) and also within the second semiconductor layer opposite the trench. Therefore, in the Examiner’s opinion, the above limitation is neither anticipated nor made obvious by the prior art of record, when viewed in the context of the independent claim 7, as a whole.
Claim 47 would be allowable for the for the following reasons. Most of the limitations are taught by Zeng et al. (US 2018/0366569 A1, of record), which includes:
forming a trench (gate trench 110, Fig. 27A, also see Fig. 4, para [0045], Zeng) through the second semiconductor layer (144’, Fig. 27A, Zeng) and extending into the first semiconductor layer (102, Fig. 27A, Zeng);
forming a first column of semiconductor material having a first conductivity type (“P region” in layer 144’, Fig. 27A, Zeng) and extending through the second semiconductor layer (144’, Fig. 27A);
forming a source region (142, Fig. 27A, para [0034], Zeng) over the first column of semiconductor material (“P region” in layer 144’, Fig. 27A, Zeng).
However, Zeng does not disclose the limitation wherein, “forming a second column of semiconductor material having a second conductivity type opposite the first conductivity type (P-type) and in contact with a side surface of the first column of semiconductor material within the second semiconductor layer opposite the trench”. Zeng discloses the second semiconductor layer (144’, Fig. 27A, Zeng) and the first column of semiconductor material with first conductivity type (“P region” in layer 144’, Fig. 27A, Zeng) within the second semiconductor layer (144’, Fig. 27A). The only N-type region (second conductivity) within the second semiconductor layer 144’, is the source region 142, and there is no additional second column of N-type within 144’ which is in contact with a side surface of the first column of semiconductor material (“P region” in layer 144’) and also within the second semiconductor layer opposite the trench. Therefore, in the Examiner’s opinion, the above limitation is neither anticipated nor made obvious by the prior art of record, when viewed in the context of the independent claim 1 and dependent claim 36 (claim 47 depends from claim 36), as a whole.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Response to Arguments
Applicant’s arguments with respect to claims 1, 7 and 21 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
With regards to independent claims 1, 7 and 21, applicant argues that the combination of Zeng et al. (US 2018/0366569 A1, of record) and Eriksen et al. (US 2003/0036247 A1, of record) is not obvious to one of ordinary skill in the art. Examiner respectfully disagrees with the applicant as detailed in the rejection of the above claims. Eriksen teaches how to make a defect-free silicon carbide layer which can then be bonded to fabricate integrated electronics, temperature sensors and other electronics (para [0017], Eriksen). Zeng shows the final device structure which includes a silicon carbide (SiC) layer. Though the SiC layer of Zeng is formed epitaxially, it would have been prima facie obvious to one of ordinary skill in the art, to replace the epitaxially grown SiC layer of Zeng with the defect-free and improved SiC layer of Eriksen, as they are art recognized well-known alternative processes of making SiC layer for a transistor device. Additionally, Miura et al. (US 2006/0169987 A1, of record) teaches a silicon substrate with patterned surface to further reduce any defects within the SiC layer that would be grown on top of the patterned silicon substrate. Thus, one of ordinary skill in the art would realize that patterning a two-dimensional array of inverted-pyramid-structure on the surface of the Si substrate of Eriksen as disclosed by Miura, would further reduce any defects within the SiC layer that will be formed above, thus realizing a high-quality SiC layer with extremely low defects.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/P.D./Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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