DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 10/15/2025 has been entered.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-8, 10-18, 21-23 have been considered but are moot in view of the new grounds of rejection.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xie et al. (US 10,388,747; hereinafter “Xie”) in view of Van Cleemput et al. (US PGPub 2018/0233398; hereinafter “Van Cleemput”).
Re claim 1: Xie teaches (e.g. figs. 5-8) a method for forming a semiconductor structure, comprising: receiving a structure comprising a metal gate structure (replacement gate structure 119; e.g. column 6, line 53), source/drain regions (raised source drain regions 116; e.g. column 7, line 16), and a dielectric structure laterally (insulating material 113) surrounding the metal gate structure (119), wherein a sacrificial spacer (112Y,112X) is interposed between the metal gate structure (119) and the dielectric structure (113); and a sidewall of the source/drain regions (116) is coupled to the sacrificial spacer (112Y,112X); removing at least a portion (112X) of the sacrificial spacer (112Y,112X) to form a recess (spaces 123; e.g. column 7, line 51) between the metal gate structure (119) and the dielectric structure (113), wherein a bottommost surface of the recess (123) is higher than upper surfaces of the source/drain regions (116); and forming a spacer (gate spacer 127; e.g. column 7, line 65) in the recess (123) along a sidewall of the metal gate structure (119).
Xie is silent as to explicitly teaching increasing a temperature of the sacrificial spacer.
Van Cleemput teaches (e.g. figs. 3E, 3F) increasing a temperature (etching 128 at a temperature of above 100°C; e.g. paragraph 44) of the sacrificial spacer (307).
It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to increase the temperature of the sacrificial spacer as taught by Van Cleemput in the method of forming the semiconductor device of Xie in order to have the predictable result of increasing the processing speed and increasing cost saving of the multistep process.
Re claim 2: Xie in view of Van Cleemput teaches the method of Claim 1, wherein the sacrificial spacer (112 made from SiN; e.g. column 6, line 25) comprises a first atom (Si) and a second atom (N) different from the first atom (Si), and the temperature of the sacrificial spacer (112) is increased by heating (increasing the temperature of 22 would heat the atoms and bonds) a bonding between the first atom (Si) and the second atom (O).
Re claim 10: Xie teaches the method of Claim 1, wherein the metal gate structure (119) comprises a gate dielectric layer (119 includes a gate insulation layer; e.g. column 6, line 55; hereinafter “GDL”), and the gate dielectric layer (GDL) is exposed through the recess (123).
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xie in view of Van Cleemput, as applied to claim 2, and further in view of Frohberg et al. (US PGPub 2009/0108336; hereinafter “Frohberg”).
Re claim 3: Xie in view of Van Cleemput teaches substantially the entire method as recited in Claim 2 except explicitly teaching the dielectric structure (113 of Xie) comprises a contact etch stop layer adjacent to the sacrificial spacer (112Y,112X of Xie).
Frohberg teaches (e.g. fig. 2h) the dielectric structure (209, 204) comprises a contact etch stop layer (etch stop layer 204 can be SiN, SiC, SiCN; e.g. paragraph 39) adjacent to the sacrificial spacer (18, 22 of Xie).
It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the etch stop layer as taught by Frohberg in the method of Xie in view of Van Cleemput in order to have the predictable result of using an etch stop to more reliably and uniformly make contact holes for device electrodes.
Claim(s) 4-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xie in view of Van Cleemput and Frohberg, as applied to claim 3, and further in view of Cheng (US PGPub 2019/0312123).
Re claim 4: Xie in view of Van Cleemput and Frohberg teaches substantially the entire method as recited in claim 3 except explicitly teaching wherein the contact etch stop layer comprises the first atom and a third atom different from the second atom and the first atom.
Cheng teaches the material of the sacrificial spacer 16 being made from SiOC (e.g. paragraph 48) and further teaches the contact etch stop layer (204 of Frohberg made from SiON; e.g. paragraph 48) comprises the first atom (Si) and a third atom (N) different from the second atom (C of sacrificial spacer 16 of Xie2) and the first atom (Si).
It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the SiOC material of the sacrificial spacer as taught by Cheng in the method of Xie in view of Van Cleemput and Frohberg in order to have the predictable result of using a sacrificial spacer having etch selectivity from the etch stop layer.
Re claim 5: Xie in view of Van Cleemput, Frohberg, and Cheng teaches the method of Claim 4, wherein the first atom (Si of Cheng’s SiOC of 16) comprises silicon (Si), the second atom (C of Cheng’s SiOC of 16) comprises carbon (C), and the third atom comprises nitrogen (N) (N of Frohberg’s SiON of 204).
Re claim 6: Xie in view of Van Cleemput, Frohberg, and Cheng teaches the method of Claim 5, wherein a concentration of the second atom (C of Cheng’s SiOC of 16) in the sacrificial spacer is substantially in a range of from 5% to 20% (the atomic percent of C in SiOC is approximately 20%).
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xie in view of Van Cleemput, as applied to claim 1, and further in view of Tsai et al. (US PGPub 2018/0175170; hereinafter “Tsai”).
Re claim 7: Xie in view of Van Cleemput teaches substantially the entire method as recited in Claim 1 except explicitly teaching the temperature of the sacrificial spacer (128/307) is increased by a millimeter wave generated by a millimeter-wave beamforming antenna system.
Tsai teaches the use of heating using plasma excited by a microwave in the frequency range of 2-10 GHz (e.g. paragraph 25).
It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the method of heating using microwave as taught by Tsai in the method of Xie in view of Van Cleemput in order to have the predictable result of simplifying manufacture by using a known method of heating devices during manufacture.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xie in view of Van Cleemput and Tsai, as applied to claim 7, and further in view of Tsukamoto et al. (US PGPub 2009/0179160; hereinafter “Tsukamoto”).
Re claim 8: Xie in view of Van Cleemput and Tsai teaches substantially the entire method as recited in Claim 7 except explicitly teaching wherein a frequency of the millimeter wave is substantially in a range of from 30 GHz to 450 GHz.
Tsukamoto teaches a frequency of the millimeter wave is substantially in a range of from 30 GHz to 450 GHz (heating can be by millimeter wave heating having a frequency of 300MHz to 300GHz; e.g. paragraph 85).
It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the method of heating using microwave as taught by Tsukamoto in the method of Xie in view of Van Cleemput and Tsai in order to have the predictable result of simplifying manufacture by using an known to be capable of heating in a wider range of frequencies and therefore having a more robust apparatus applicable to many applications.
Claim(s) 11-18, 21, 22, and 23, is/are rejected under 35 U.S.C. 103 as being unpatentable over Xie (US PGPub 10,388,747) in view of Van Cleemput and Cheng (US PGPub 2009/0001480; hereinafter “Cheng2”).
Re claim 11: Xie teaches (e.g. figs. 5-8) a method for forming a semiconductor structure, comprising: receiving a structure comprising a gate structure (replacement gate structure 119; e.g. column 6, line 53), source/drain regions (raised source drain regions 116; e.g. column 7, line 16), and a sacrificial spacer (112Y,112X) along a sidewall of the gate structure (119), wherein the gate structure (119) comprises a gate electrode (119 includes a gate conductor; e.g. column 6, line 55; hereinafter “GCL”) and a gate dielectric layer (119 includes a gate insulation layer; e.g. column 6, line 55; hereinafter “GDL”), and the sacrificial spacer (112Y,112X) is adjacent to the gate dielectric layer (GDL); selectively etching (112X etched in fig. 7) the sacrificial spacer (112Y,112X) to reduce a thickness of the sacrificial spacer (112Y,112X), wherein an upper surface (upper surface of 112Y) of remaining sacrificial spacer (112Y) is higher than upper surfaces of the source/drain regions (116); and a bottom surface of the remaining sacrificial spacer (112Y) is lower than the upper surfaces of the source/drain regions (116).
Xie is silent as to explicitly teaching performing a treatment to selectively heat a bonding between a first atom and a second atom of the sacrificial spacer (18, 22) and removing a surface portion of the gate dielectric layer (upper portion of 28 removed as shown in fig. 3E).
Van Cleemput teaches (e.g. figs. 3E, 3F) teaching performing a treatment (etching 128 at a temperature of above 100°C; e.g. paragraph 44) to selectively heat a bonding between a first atom and a second atom of the sacrificial spacer (307).
Cheng2 teaches removing a surface portion of the gate dielectric layer (upper portion of 28 removed as shown in fig. 3E).
It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to increase the temperature of the sacrificial spacer as taught by Van Cleemput and to remove the upper portions of the gate dielectric sidewalls as taught by Cheng2 in the method of forming the semiconductor device of Xie in order to have the predictable result of increasing the processing speed and increasing cost saving of the multistep process, and in order to have the predictable result of improving electrical isolation between the gate and s/d contacts, respectively.
Re claim 12: Xie in view of Van Cleemput and Cheng2 teaches the method of Claim 11, further comprising: forming a spacer (SiOC spacer 36; e.g. paragraphs 78 of Cheng2) along a sidewall of the gate electrode (30).
Re claim 13: Xie in view of Van Cleemput and Cheng2 teaches the method of Claim 12, further comprising: repeating the steps (fig. 3D and 3E of Cheng2) of performing the treatment and selectively etching until at least a first portion (top portion of 28 is etched as shown in fig. 3E of Cheng2) of a sidewall of the gate dielectric layer (28 of Cheng2) is exposed, wherein a portion of the sacrificial spacer (18 of Cheng2) remains adjacent to a second portion (bottom portion of 28 of Cheng2) of the sidewall of the gate dielectric layer (28).
Re claim 14 Xie in view of Van Cleemput and Cheng2 teaches the method of Claim 13, wherein the spacer (36 of Cheng2) is formed over the portion of the sacrificial spacer (18 of Cheng2).
Re claim 15: Xie in view of Van Cleemput and Cheng2 teaches the method of Claim 11, wherein the structure further comprises a dielectric structure (24 of Cheng2) adjacent to the sacrificial spacer (22, 18 of Cheng2), and the sacrificial spacer (22, 18 of Cheng2) is between the gate dielectric layer (28 of Cheng2) and the dielectric structure (24 of Cheng2).
Re claim 16: Xie in view of Van Cleemput and Cheng2 teaches the method of Claim 15, further comprising: removing (fig. 3A of Cheng2 shows a planarized top surface) a surface portion (top portion of 24 of Cheng2) of the dielectric structure (24 of Cheng2) prior to removing the surface portion of the gate dielectric layer (top part of 28 as shown in fig. 3E of Cheng2).
Re claim 17: Xie in view of Van Cleemput and Cheng2 teaches the method of Claim 11, wherein the sacrificial spacer (22, 18 of Cheng2) comprises a low-k dielectric material (sacrificial spacer 22, 18 made from SiON low-k material; e.g. paragraph 61 of Cheng2), and the gate dielectric layer (high-k gate dielectric 28; e.g. paragraph 67 of Cheng2) comprises a high-k dielectric material.
Re claim 18: Xie in view of Van Cleemput and Cheng2 teaches the method of Claim 17, wherein the low-k dielectric material comprises SiCON or SiCN (low-k dielectric spacer made from Si, C, O, H; e.g. paragraph 78 of Cheng2).
Re claim 21: Xie teaches (e.g. figs. 5-8) a method for forming a semiconductor structure, comprising: receiving a gate structure (replacement gate structure 119; e.g. column 6, line 53), source/drain regions (raised source drain regions 116; e.g. column 7, line 16), a dielectric structure (insulating material 113) laterally surrounding the gate structure (119), and a sacrificial spacer (112Y,112X) along a sidewall of the gate structure (119) and the dielectric structure (113), wherein the gate structure (119) comprises a gate electrode (119 includes a gate conductor; e.g. column 6, line 55; hereinafter “GCL”) and a gate dielectric layer (119 includes a gate insulation layer; e.g. column 6, line 55; hereinafter “GDL”); a sidewall of the source/drain regions (116) is coupled to the sacrificial spacer (112Y,112X); removing at least a portion (112X) of the sacrificial spacer (112Y,112X) to form a first recess (spaces 123; e.g. column 7, line 51) between the gate structure (119) and the dielectric structure (113); removing a surface portion () of the dielectric structure (24) to widen the first recess (R) to form a second recess (recess 123 as shown in fig. 7 at an initial point in time becomes wider as recess 123 is etched; hereinafter “2R”).
Xie is silent as to explicitly teaching increasing a temperature of the sacrificial spacer; and removing a surface portion of the gate dielectric layer to widen the second recess (2R) to form a third recess (recess as shown in fig. 3E at the final point in time; hereinafter “3R”), wherein a bottommost surface of the third recess (3R) is higher than upper surfaces of the source/drain regions (14).
Van Cleemput teaches (e.g. figs. 3E, 3F) increasing a temperature (etching 128 at a temperature of above 100°C; e.g. paragraph 44) of the sacrificial spacer (307).
Cheng2 teaches removing a surface portion of the gate dielectric layer to widen the second recess (2R) to form a third recess (recess as shown in fig. 3E at the final point in time; hereinafter “3R”), wherein a bottommost surface of the third recess (3R) is higher than upper surfaces of the source/drain regions (14).
It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to increase the temperature of the sacrificial spacer as taught by Van Cleemput and to remove the upper portions of the gate dielectric sidewalls as taught by Cheng2 in the method of forming the semiconductor device of Xie in order to have the predictable result of increasing the processing speed and increasing cost saving of the multistep process, and in order to have the predictable result of improving electrical isolation between the gate and s/d contacts, respectively.
Re claim 22: Xie in view of Van Cleemput and Cheng2 teaches the method of Claim 21, further comprising forming a spacer (SiOC spacer 36; e.g. paragraphs 78) in the third recess (3R).
Re claim 23: Xie in view of Van Cleemput and Cheng2 teaches the method of Claim 21, wherein the sacrificial spacer (18) is exposed through a bottom of the third recess (3R).
Conclusion
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/JESSE Y MIYOSHI/
Primary Examiner, Art Unit 2898
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