Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 10/29/2025 has been entered.
Prior Art of Record
The applicant's attention is directed to additional pertinent prior art cited in the accompanying PTO-892 Notice of References Cited, which, however, may not be currently applied as a basis for the following rejections. While these references were considered during the examination of this application and are deemed relevant to the claimed subject matter, they are not presently being applied as a basis for rejection in this Office action. The pertinence of these documents, however, may be revisited, and they may be applied in subsequent Office actions, particularly in light of any amendments or further clarification of the claimed invention.
Response to Arguments
Applicant's arguments filed 10/20/2025 have been fully considered but they are not persuasive.
As addressed in the previous Response to After Final Amendments, mailed 10/24/2025, the scope of the argued claim is broader than the applicant’s arguments suggest.
The applicant incorrectly argues for an overly narrow interpretation that limits layers 235a and 235 to being entirely electrically coupled to the n-type and p-type layers.
The claim language does not require the entire layer to be isolated or entirely coupled; rather, it allows for both scenarios within the same layer, as depicted in the applicant’s own figures. The claim specifically states:
"a second reflective layer that is electrically conductive, and a plurality of reflective layer interconnects that extend through the first reflective layer to electrically couple first portions of the second reflective layer to the p- type layer, wherein second portions of the second reflective layer are electrically isolated from the active LED structure,".
This quoted text explicitly refers to a single “second reflective layer” that features both “coupled” first portions 38 and “isolated” second portions 34.
The argument that element 34’ depicts this feature appears incorrect, as the figure’s limited cross-sectional view shows element 34’ as entirely isolated. Instead, reflective layer 34/38 accurately reflects the plain meaning of the terminology as recited in the claim language. The broader reflective layer structure (34/38) has isolated portions (34) and coupled portions (38).
Therefore, the rejection stands because the requirement is met if some parts of the layer have isolation material, even if other parts are electrically connected to the LED. This interpretation is consistent with the plain meaning of the claim language and the Applicant’s own patent figures and description, which supports that an overall layer can be connected to the LED despite containing some isolated portions. The term "portion" does not specify exact boundaries, making the assumption that the entire layer must be isolated incorrect and unpersuasive.
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Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-7, 10-22, 24-28 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Won (US 20170288088 A1).
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CLAIM 1. Won discloses a light-emitting diode (LED) chip, comprising: an active LED structure comprising an n-type layer, a p-type layer, and an active layer arranged between the n-type ¶192 layer 225 and the p-type layer 229; an n-contact 235a electrically coupled with the n-type layer; a p-contact 239b electrically coupled with the p-type layer; and a plurality of n-contact interconnects electrically coupled between the n-type layer and the n-contact, wherein one or more n-contact interconnects of the plurality of n-contact interconnects are vertically arranged between the p-contact and the n-type layer (Won FIG. 38B – i.e. plurality of contact interfaces/surfaces of layer 235a);
further comprising a reflective structure on the active LED structure, wherein the reflective structure comprises a first reflective layer that is electrically insulating 233, a second reflective¶224 layer that 235a/b is electrically conductive ¶224, and a plurality of reflective layer interconnects that extend through the first reflective layer to electrically couple first portions of the second reflective layer to the p-type layer (Won figs. 9A-B).
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wherein second portions of the second reflective layer are electrically isolated from the active LED structure 227 (Won FIG. 38B).
CLAIM 2. Won discloses a chip of claim 1, wherein the one or more n-contact interconnects of the plurality of n-contact interconnects are electrically coupled to an n-contact structure that is electrically coupled to the n-contact (Won FIG. 38B – i.e. 235a).
CLAIM 3. Won discloses a chip of claim 2, wherein the n-contact structure is arranged to laterally extend from a position that is vertically registered with the n-contact to a position that is vertically registered with the p-contact such that the n-contact structure is electrically coupled with the one or more n-contact interconnects of the plurality of n-contact interconnects that are vertically arranged between the p-contact and the n-type layer (Won FIG. 38B – i.e. 235a).
CLAIM 4. Won discloses a chip of claim 2, further comprising: a peripheral n-contact interconnect that is electrically coupled to a portion of the n-type layer that is outside a mesa sidewall of the active LED structure, the mesa side wall comprising a sidewall of the p-type layer, the active layer, and a portion of the n-type layer; wherein the n-contact structure is arranged to laterally extend from a position that is vertically registered with the n-contact to the mesa sidewall such that the n-contact structure is electrically coupled to the peripheral n-contact interconnect (Won FIG. 38B – i.e. 235a).
CLAIM 5. Won discloses a chip of claim 4, wherein the peripheral n-contact interconnect is electrically coupled with the one or more n-contact interconnects of the plurality of n-contact interconnects that are vertically arranged between the p-contact and the n-type layer (Won FIG. 38B – i.e. 235a).
CLAIM 6. Won discloses a chip of claim 4, wherein the peripheral n-contact interconnect is electrically coupled to the portion of the n-type layer that is outside the mesa sidewall in a continuous manner proximate two or more peripheral edges of the active LED structure (Won FIG. 38B – i.e. 235a).
CLAIM 7. Won discloses a chip of claim 4, wherein the peripheral n-contact interconnect is electrically coupled to the portion of the n-type layer that is outside the mesa sidewall in a discontinuous manner such that portions of the peripheral n-contact interconnect contact the n-type layer and other portions of the peripheral n-contact interconnect are separated from the n-type layer by a passivation layer 233 (Won FIG. 38B).
CLAIM 10. Won discloses a chip of claim 9, wherein the second portions of the second reflective layer are vertically arranged between the n-contact structure and the active LED structure (Won FIG. 38B).
CLAIM 11. Won discloses a chip of claim 8, wherein a second portion of the second reflective layer is entirely separated from the p-type layer by a passivation layer 233, and the second portion of the second reflective layer is electrically coupled with the n-contact (Won FIG. 38B).
CLAIM 12. Won discloses a chip of claim 1, further comprising: a passivation layer on the active LED structure, wherein the plurality of n-contact interconnects 311b extend through portions of the passivation layer 233/237; and a first metal-containing interlayer 311A, a second metal-containing interlayer 313/250/239a, and a third-metal containing interlayer 235A arranged within the passivation layer, wherein each of the first metal-containing interlayer, the second metal-containing interlayer, and the third-metal containing interlayer are electrically isolated from the n-contact and the p-contact (Fig. 29).
CLAIM 13. Won discloses a chip of claim 1, wherein the n-contact and the p-contact are contact pads arranged to receive external electrical connections when the LED chip is flip-chip mounted (Won FIG. 30A-B).
CLAIM 14. A light-emitting diode (LED) chip, comprising: an active LED structure comprising an n-type layer, a p-type layer, and an active layer arranged between the n-type layer and the p-type layer; a passivation layer on the active LED structure; and a first metal-containing interlayer, a second metal-containing interlayer, and a third-metal containing interlayer at least partially within the passivation layer, wherein each of the first metal-containing interlayer, the second metal-containing interlayer, and the third-metal containing interlayer are electrically isolated from the active LED structure (Won FIGS. 29 & 38B).
CLAIM 15. Won discloses a chip of claim 14, further comprising: a reflective structure on the active LED structure, wherein the reflective structure comprises a first reflective layer that is electrically insulating, a second reflective layer that is electrically conductive, and a plurality of reflective layer interconnects that extend through the first reflective layer to electrically couple first portions of the second reflective layer to the p-type layer; wherein the second metal-containing interlayer comprises second portions of the second reflective layer that are electrically isolated from the active LED structure (Won FIGS. 29 & 38B).
CLAIM 16. Won discloses a chip of claim 14, further comprising: an n-contact electrically coupled with the n-type layer; a p-contact electrically coupled with the p-type layer; a plurality of n-contact interconnects electrically coupled between the n-type layer and the n-contact; and an n-contact structure that is electrically coupled with one or more n-contact interconnects of the plurality of n-contact interconnects, wherein the n-contact structure is arranged to laterally extend within the passivation layer (Won FIGS. 29 & 38B).
CLAIM 17. Won discloses a chip of claim 16, wherein the third metal-containing interlayer comprises a same material as the n-contact structure (Won FIGS. 29 & 38B).
CLAIM 18. Won discloses a chip of claim 16, wherein the second metal-containing interlayer is vertically arranged between the n-contact structure and the active LED structure (Won FIGS. 29 & 38B).
CLAIM 19. Won discloses a chip of claim 16, further comprising: a reflective structure on the active LED structure, wherein the reflective structure comprises a first reflective layer that is electrically insulating, a second reflective layer that is electrically conductive, and wherein the first reflective layer is between the second reflective layer and the p-type layer; wherein the second metal-containing interlayer comprises portions of the second reflective layer that are electrically isolated from the active LED structure (Won FIGS. 29 & 38B).
CLAIM 20. Won discloses a chip of claim 19, wherein the portions of the second reflective layer that are electrically isolated from the active LED structure are vertically arranged between the n-contact structure and the active LED structure (Won FIGS. 29 & 38B).
CLAIM 21. Won discloses a chip of claim 14, wherein the first metal-containing interlayer, the second metal-containing interlayer, and the third metal-containing interlayer are vertically arranged within the passivation layer (Won FIGS. 29 & 38B).
CLAIM 22. A light-emitting diode (LED) chip, comprising: an active LED structure comprising an n-type layer, a p-type layer, and an active layer arranged between the n-type layer and the p-type layer; a plurality of n-contact interconnects electrically coupled to the n-type layer; and an n-contact structure electrically coupled to the plurality of n-contact interconnects, the n-contact structure comprising a first segment that is connected to a first group of n-contact interconnects of the plurality of n-contact interconnects, and a second segment that is connected to a second group of n-contact interconnects of the plurality of n-contact interconnects (Won FIGS. 29 & 38B).
CLAIM 24. Won discloses a chip of claim 22, wherein the first segment of the n-contact structure is arranged to continuously extend from one edge of the active LED structure to an opposing edge of the active LED structure (Won FIGS. 29 & 38B).
CLAIM 25. Won discloses a chip of claim 22, wherein the second segment of the n-contact structure is arranged to continuously extend without extending to at least one edge of the active LED structure (Won FIGS. 29 & 38B).
CLAIM 26. Won discloses a chip of claim 22, further comprising: an n-contact electrically coupled with the n-contact structure; and a p-contact electrically coupled with the p-type layer; wherein the plurality of n-contact interconnects are vertically arranged outside peripheral edges of the p-contact (Won FIGS. 29 & 38B).
CLAIM 27. Won discloses a chip of claim 26, wherein the p-contact comprises: a first portion that is vertically arranged between a boundary of the first segment of the n-contact structure and a perimeter of the active LED structure; and a second portion that is vertically arranged between another boundary of the first segment of the n-contact structure and a boundary of the second segment of the n-contact structure; wherein the first portion of the p-contact is discontinuous with the second portion of the p-contact (Won FIGS. 29 & 38B).
CLAIM 28. Won discloses a LED chip of claim 14, wherein the first metal-containing interlayer 311A, the second metal-containing interlayer 313/250/239a, and the third-metal containing interlayer 235A are electrically isolated from the active LED structure by the passivation layer (Fig. 29- at least partially within passivation material. Figs. 30A-B – Upon completion of the device, it is recognized the structure may be completely encapsulated within a insulating/passivation material for protection and/or other recognized benefits.).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JARRETT J STARK whose telephone number is (571)272-6005. The examiner can normally be reached 8-4 M-F.
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JARRETT J. STARK
Primary Examiner
Art Unit 2822
12/5/2025
/JARRETT J STARK/Primary Examiner, Art Unit 2898