Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 1/8/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference characters “706” and “708” in Fig. 7 have both been used to designate the “read bit line conductive structure 708” described in [0114]. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 9, 10, and 11 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 9, “wherein the read word line conductive structure is coupled with a first source/drain region of the first transistor; wherein the read bit line conductive structure is coupled with a gate structure of the first transistor” in lines 5-8 is indefinite because it is inconsistent with the specification. More specifically, lines 1-4 require the above/below configuration of the RWL and RBL of Fig. 3. However, to also satisfy the “coupled” requirements in lines 5-8, the term “coupled” must also include capacitive coupling which is inconsistent with [0053] of the written description. For the sake of compact prosecution, the meaning of “coupled” in the claim is interpreted as including one of direct and capacitive coupling. MPEP 2173.03: “A claim, although clear on its face, may also be indefinite when a conflict or inconsistency between the claimed subject matter and the specification disclosure renders the scope of the claim uncertain as inconsistency with the specification disclosure or prior art teachings may make an otherwise definite claim take on an unreasonable degree of uncertainty.”. The examiner notes the issue appears to be an inadvertent swapping of the terms “a first source/drain region” and “a gate structure” in lines 5-8 of the claim.
Regarding claim 10, “a source/drain transistor of the first transistor” in line 6 is unclear how a component of a transistor (i.e., a source, drain, gate, channel) can also be an entire transistor. For the sake of compact prosecution, claim 10 is interpreted in the instant Office action as follows: “a source/drain transistor of the first transistor” in line 6 is equivalent to “a source/drain region of the first transistor”. This interpretation is to be confirmed by applicant in next office action.
Regarding claim 11, “wherein a second source/drain region, of the first plurality of source/drain regions of the second transistor, is coupled with the first gate structure of the second transistor” in lines 6-7 is indefinite because it is inconsistent with the specification. More specifically, lines 1-4 require the above/below configuration of the RWL and RBL of Fig. 3. However, to also satisfy the “coupled” requirements in lines 6-7, the term “coupled” must also include capacitive coupling which is inconsistent with [0053] of the written description. For the sake of compact prosecution, the meaning of “coupled” in the claim is interpreted as including one of direct and capacitive coupling. MPEP 2173.03: “A claim, although clear on its face, may also be indefinite when a conflict or inconsistency between the claimed subject matter and the specification disclosure renders the scope of the claim uncertain as inconsistency with the specification disclosure or prior art teachings may make an otherwise definite claim take on an unreasonable degree of uncertainty.”. The examiner notes the issue appears to be an inadvertent inclusion of term “a second source/drain region, of the first plurality of source/drain regions of the second transistor” instead of “a second source/drain region, of the second plurality of source/drain regions of the third transistor” in lines 5-8 of the claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 6-12 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Zhu (CN 115274669 A).
Regarding claim 1, Zhu discloses a memory cell structure (Fig. 16), comprising:
a first transistor (encircled as TS, See annotated figure) coupled with a word line conductive structure (1005; pg. 7 of translation: “connecting line layer 1005 may define RWL”) and a bit line conductive structure (1011. Note: this mapping is based on selecting RBL for 1011, which is an option of two possible configurations disclosed in pg. 5: “the second connecting line layer (the conductive line in the line) can be a read bit line (RBL)”. This interpretation is also supported by the schematic of Fig. 17(b));
a second transistor (encircled as TR, See annotated figure) above (vertically above, See annotated figure for direction designation) the first transistor and coupled (electrical coupling is shown in the schematic of Fig. 17(b)) with the first transistor (TR is coupled to TS at a portion of 1027) and to a ground conductive structure (1015. Note: this mapping is based on selecting ground for 1015, which is an option of two possible configurations disclosed in pg. 5: “the third connecting line layer (conductive line in the line) can be a read bit line (RBL) and the ground plane in the other one”. This interpretation is also supported by the schematic of Fig. 17(b));
and a third transistor (encircled as TW, See annotated figure) above (vertically above) the second transistor and coupled (electrical coupling is shown in the schematic of Fig. 17(b)) with the second transistor (TW is coupled to TR at SN), a write word line conductive structure (1045/WWL), and a write bit line conductive structure (1021/WBL),
wherein at least one of the second transistor or the third transistor comprises a channel layer (TW includes channel layer 1041; pg. 12: “a channel region”) that comprises:
an inverted (inverted U-shaped when facing towards 1001) approximately U-shaped portion (See annotated figure);
and a plurality of extension portions (See annotated figure), each coupled (integrally coupled) with a respective end of the inverted approximately U-shaped portion.
Illustrated below are marked and annotated figures of Figs. 16 and 17(b) of Zhu.
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Regarding claim 2, Zhu discloses the memory cell structure of claim 1 (Fig. 16), wherein the inverted approximately U-shaped portion comprises: a first elongated portion (Left portion of the portion 1041, See annotated figure for direction designation); a second elongated portion (Right portion of the portion 1041, See annotated figure for direction designation); and a third elongated portion (Middle portion of the portion 1041, See annotated figure for direction designation) coupled (integrally coupled) with the first elongated portion and the second elongated portion at opposing ends (opposing horizontally) of the third elongated portion.
Regarding claim 3, Zhu discloses the memory cell structure of claim 2 (Fig. 16), wherein the first elongated portion is approximately parallel (vertically parallel) with the second elongated portion; and wherein the third elongated portion is approximately perpendicular (perpendicular along the horizontal direction) with the first elongated portion and the second elongated portion.
Regarding claim 6, Zhu discloses the memory cell structure of claim 1 (Fig. 16), wherein the first transistor comprises: a first source/drain region (TS-SD1); a second source/drain region (TS-SD2); and a gate structure (1031) between (vertically between along a meandering path) the first source/drain region and the second source/drain region.
Regarding claim 7, Zhu discloses the memory cell structure of claim 6 (Fig. 16), wherein the first transistor comprises: another channel layer (TS-CH 1027) that wraps around at least three sides of the gate structure (channel 1027 wraps around all four sides of gate 1031 in the horizontal/out-of-page plane. Note: this surrounding shape is the resultant shape of the 1027 formation technique; pg. 9: “the first active layer 1027 can be left on the side wall of the opening”), wherein the other channel layer is between the gate structure and the first source/drain region (TS-CH 1027 is vertically between 1031 and TS-SD1 along a meandering path), and is between the gate structure and the second source/drain region (TS-CH 1027 is vertically between 1031 and TS-SD2 along a meandering path).
Regarding independent claim 8, Zhu discloses a dynamic random access memory (DRAM) cell structure (Fig. 16; pg. 5: “dynamic random access memory”), comprising:
a first transistor (encircled as TS, See annotated figure) coupled with a word line conductive structure (1005; pg. 7 of translation: “connecting line layer 1005 may define RWL”) and a bit line conductive structure (1011. Note: this mapping is based on selecting RBL for 1011, which is an option of two possible configurations disclosed in pg. 5: “the second connecting line layer (the conductive line in the line) can be a read bit line (RBL)”. This interpretation is also supported by the schematic of Fig. 17(b));
a second transistor (encircled as TR, See annotated figure) above (vertically above, See annotated figure for direction designation) above (vertically above, See annotated figure for direction designation) the first transistor and coupled (electrical coupling is shown in the schematic of Fig. 17(b)) with the first transistor (TR is coupled to TS at a portion of 1027) and to a ground conductive structure (1015. Note: this mapping is based on selecting ground for 1015, which is an option of two possible configurations disclosed in pg. 5: “the third connecting line layer (conductive line in the line) can be a read bit line (RBL) and the ground plane in the other one”. This interpretation is also supported by the schematic of Fig. 17(b)),
wherein the second transistor comprises:
a first plurality of source/drain regions (TR-SD1, TR-SD2);
a first channel layer (TR-CH 1027) above the first plurality of source/drain regions (vertically above at least some of the plurality because it is vertically above TR-SD1);
and a first gate structure (1035) above the first plurality of source/drain regions (vertically above at least some of the plurality because it is vertically above TR-SD1) and at least partially wrapping around the first channel layer (gate 1035 is fully wrapping around the inside of TS-CH 1027);
and a third transistor (encircled as TW, See annotated figure) above (vertically above) the second transistor and coupled (electrical coupling is shown in the schematic of Fig. 17(b)) with the second transistor (TW is coupled to TR at SN), a write word line conductive structure (1045/WWL), and a write bit line conductive structure (1021/WBL),
wherein the third transistor comprises:
a second plurality of source/drain regions (TW-SD1, TW-SD2, See annotated figure below); a second channel layer (TW-CH 1041) above the second plurality of source/drain regions (vertically above at least some of the plurality because it is vertically above TW-SD1);
and a second gate structure (1045) above the second plurality of source/drain regions (vertically above at least some of the plurality because it is vertically above TW-SD1) and at least partially wrapping around the second channel layer (gate 1045 is fully wrapping around the inside of TW-CH 1041).
Illustrated below is a marked and annotated figure of Fig. 16 of Zhu.
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Regarding claim 9 as noted in the 112(b) rejection, Zhu discloses the DRAM cell structure of claim 8 (Fig. 16), wherein the word line conductive structure is a read word line conductive structure (1005; pg. 7 of translation: “connecting line layer 1005 may define RWL”) that is below the first transistor (vertically below);
wherein the read bit line conductive structure is a read bit line conductive structure that is above the first transistor (1011 is vertically above at least a portion of TS) and below the second transistor (vertically below);
wherein the read word line conductive structure is coupled (1005 is capacitively coupled with 1027) with a first source/drain region of the first transistor (TS-SD1);
wherein the read bit line conductive structure is coupled (1011 is capacitively coupled with 1031) with a gate structure of the first transistor (1031);
and wherein a second source/drain region of the first transistor (TS-SD2) is coupled (integrally coupled, directly electrically coupled) with a source/drain region (coupled with region TR-SD1) of the first plurality of source/drain regions of the second transistor.
Regarding claim 10 as noted in the 112(b) rejection, Zhu discloses the DRAM cell structure of claim 8 (Fig. 16), wherein the ground conductive structure is below the second transistor (a portion of 1015 is vertically below a portion of 1035, which is a portion of transistor TR) and above the first transistor (vertically above);
wherein a first source/drain region (TR-SD2), of the first plurality of source/drain regions of the second transistor, is coupled (directly electrically coupled) with the ground conductive structure;
wherein a second source/drain region (TR-SD1), of the first plurality of source/drain regions of the second transistor, is coupled (integrally coupled, directly electrically coupled) with a source/drain region of the first transistor;
and wherein the first gate structure of the second transistor is coupled (directly electrically coupled) with a source/drain region of the second plurality of source/drain regions of the third transistor (TW-SD1).
Regarding claim 11 as noted in the 112(b) rejection, Zhu discloses the DRAM cell structure of claim 8 (Fig. 16), wherein the write bit line conductive structure is above (1021 is vertically above TR) the second transistor and below the third transistor (1021 is vertically below a portion of TW);
wherein the write word line conductive structure is above the third transistor (vertically above); wherein a first source/drain region (TW-SD2), of the second plurality of source/drain regions of the third transistor, is coupled (directly electrically coupled) with the write bit line conductive structure;
wherein a second source/drain region (TR-SD1), of the first plurality of source/drain regions of the second transistor, is coupled (TR-SD1 is capacitively coupled with 1035) with the first gate structure of the second transistor;
and wherein the second gate structure of the third transistor is coupled (directly electrically coupled) with the write word line conductive structure.
Regarding claim 12, Zhu discloses the DRAM cell structure of claim 8 (Fig. 16), wherein at least one of the first channel layer or the second channel layer corresponds to an approximately ohm (Ω) symbol (second channel layer 1041 is U-shaped which is “approximately” ohm (Ω) symbol shaped).
Claims 15 and 17-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Song (CN 114334980 A).
Regarding independent claim 15, Song discloses a method of forming a transistor (transistor components are cited further below) of a memory cell (pg. 2 of translation: “a non-capacitor DRAM cell”), comprising:
forming, in a dielectric layer (Fig. 17: defining “layer” as the collection of structures 102/104/109a/109; pg. 5: “isolation layer material”. Note: this interpretation of “in” and “layer” is consistent with Applicant’s disclosure, Fig. 6A: the collective layer using 402/404), a first source/drain region (103; pg. 4: “source electrode”) and a second source/drain region (105; pg. 4: “drain electrode”) of the transistor;
forming a dielectric support structure (104) above the first source/drain region (Position B of 104 is above Position A of 103, when using the designated direction. See annotated figure for direction designation) and above the second source/drain region (Position B of 104 is above Position A of 105, when using the designated direction. See annotated figure for direction designation);
forming a channel layer (106; pg. 4: “channel layer”) of the transistor such that the channel layer is on the dielectric support structure (directly on) and above the first source/drain region and the second source/drain region (106 is above 103/105, when using the designated direction), wherein the channel layer wraps (106 directly and indirectly wraps 104) around three sides of the dielectric support structure (three sides are shown wrapped) and extends over (directly over) top surfaces (See annotated figure) of the first source/drain region and the second source/drain region;
forming a gate dielectric layer (107; pg. 4: “gate dielectric layer”) of the transistor over (directly over) the channel layer;
and forming a gate structure (108; pg. 4: “gate layer”) of the transistor over the gate dielectric layer (directly over based on no disclosed intervening deposition steps).
Illustrated below is a marked and annotated figure of Fig. 17 of Song.
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Regarding claim 17, Song discloses the method of claim 15 (Fig. 17), wherein forming the gate dielectric layer comprises: depositing the gate dielectric layer by conformal deposition (pg. 4: “The first channel layer 106, the first gate dielectric layer 107 and the first gate layer 108 are conformal”) such that a shape of the gate dielectric layer conforms to a shape of channel layer (the figure shows 107 is conformal to the channel layer 106).
Regarding claim 18, Song discloses the method of claim 15 (Fig. 17), wherein the dielectric layer comprises a first dielectric layer (104, formed in the method step of Fig. 9); wherein the method further comprises: forming a second dielectric layer (109a, formed in the method step of Figs. 13-15) over the first dielectric layer after forming the gate dielectric layer (109a is initially formed in Fig. 13, which is “after” forming gate dielectric layer 107 in Fig. 11); and wherein forming the gate structure comprises: forming the gate structure in the second dielectric layer (the resultant configuration of gate structure 108 is “in” dielectric 109a).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Song as applied to claim 15 above, and further in view of Rios (US 20200066326 A1).
Regarding claim 16, Song discloses the method of claim 15 (Fig. 17), wherein forming the first source/drain region comprises: forming the first source/drain region such that the first source/drain region is connected to an interconnect structure (Fig. 1: the schematic wirings shown that ultimately connect to RWL or RBL. Note: these wirings correspond to regions 103 and 105 based on the teachings in pg. 5, which teaches the function and spatial configuration of the transistor terminals) […]. that is connected to a ground conductive structure.
Song fails to teach “the first source/drain region is connected to an interconnect structure. that is connected to a ground conductive structure”.
Rios teaches the first source/drain region (Fig. 2: See annotated figure) comprises: forming the first source/drain region (See annotated figure) such that the first source/drain region is connected to an interconnect structure (See annotated figure) that is connected to a ground conductive structure (See annotated figure). Modifying the interconnect structure of the first source/drain region (of Song) by connecting it to a ground conductive structure (taught by Rios) would arrive at the claimed connection configuration. Rios provides a teaching to motivate one of ordinary skill in the art before the effective filing date to include the connection configuration in the method in that it would enable forming a memory cell capable of operating at high speed ([0008]: “a high speed memory device”). A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success because in each case the first source/drain region is connected with a read bit line (Song: Fig. 1: RBL; Rios: Fig. 2: RBL). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed connection configuration in the method because it would enable forming a high speed memory cell. MPEP 2143 (I)(G).
Illustrated below is a marked and annotated figure of Fig. 2 of Rios.
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Allowable Subject Matter
Claims 4-5, 13-14, and 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The primary reason for the allowable subject matter of claims 4-5 is the inclusion of the limitation “wherein the plurality of extension portions comprise: a first extension portion; and a second extension portion that is approximately parallel with the first extension portion, wherein the first extension portion and the second extension portion are approximately parallel with the third elongated portion and approximately perpendicular with the first elongated portion and the second elongated portion” in combination with the other limitations in the claim. For example, prior art of record fails to teach or be reasonably combined to render obvious the claimed limitations “extension portions”, and the spatial arrangement with the other claimed structures in combination with all other limitations in claims 4, 2, and 1.
The primary reason for the allowable subject matter of claims 13-14 is the inclusion of the limitation “a first extension portion; and a second extension portion that is approximately parallel with the first extension portion, wherein the first extension portion and the second extension portion are approximately parallel with the third elongated portion and approximately perpendicular with the first elongated portion and the second elongated portion” in combination with the other limitations in the claim. For example, prior art of record fails to teach or be reasonably combined to render obvious the claimed limitations “extension portion”, and the spatial arrangement with the other claimed structures in combination with all other limitations in claims 13 and 8.
The primary reason for the allowable subject matter of claim 19 is the inclusion of the limitation “forming a spacer layer (606) on the gate dielectric layer prior to forming the gate structure, wherein forming the gate structure comprises: forming the gate structure on the spacer layer” in combination with the other limitations in the claim. For example, prior art of record fails to teach or be reasonably combined to render obvious the claimed limitations “spacer layer”, the spatial and sequential limitation “on the gate dielectric layer”, and the sequence “prior” in combination with all other limitations in claims 19 and 15.
The primary reason for the allowable subject matter of claim 20 is the inclusion of the limitation “performing an etch back operation to remove first portions of the layer of channel material such that second portions of the layer of channel material remain over the dielectric support structure, the first source/drain region, and the second source/drain region, wherein the second portions of the layer of channel material correspond to the channel layer” in combination with the other limitations in the claim. For example, prior art of record fails to teach or be reasonably combined to render obvious the claimed limitations “etch back operation”, and “remove” in combination with all other limitations in claims 20 and 15.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM H ANDERSON whose telephone number is (571)272-2534. The examiner can normally be reached Monday-Friday, 8:00-5:00.
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/WILLIAM H ANDERSON/ Examiner, Art Unit 2817