DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 3/24/2026 has been entered.
Information Disclosure Statement
Acknowledgement is made of Applicant's Information Disclosure Statement (IDS) from PTO-1449. The IDS has been considered.
Claim Status
Claims 1-2, 5-13, 16-21 and 33-42 are pending in this application.
Prior rejection of Claims 1-2, 5-11 and 33 under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, is withdrawn in view of applicant’s amendments to claims 1 and 12.
Prior rejection of Claims 1-2, 5-11 and 33 under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, is withdrawn in view of applicant’s amendments to claims 1 and 12.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-2, 5-11, 13 and 34-42 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 recites the limitation wherein, “(e) a first insulating layer formed over the trench; and (f) a second insulating layer formed over the first insulating layer”. In the elected embodiment in Fig. 11(k), there are two insulating layers, layer 254 and layer 270, and 270 is above 254. Hence the first insulating layer has to be 254 and the second insulating layer has to be 270. Now the claim recites that the first insulating layer is formed over the trench. The trench is 236 and is defined by the sidewalls 250 and the bottom surface 246 (see Fig. 11(e)). Therefore, it appears that the layer 254 is formed within the trench and not over the trench, thus introducing new matter and hence rejected. Claims 2 and 5-11 depend from claim 1 and are rejected at least for the reasons above.
Claim 13 recites the limitation wherein “the insulating layer includes an oxide layer and a nitride layer for protection against radiation”. Claim 13 depends from claim 12 wherein the insulator layer is defined. Claim 12 recites that “an insulating layer is formed over the trench”. The only insulating layer that is formed over the trench 236 in the elected embodiment of Fig. 11k, is the insulating layer 270. Layer 270 can have only one material, either an oxide or a nitride (para [0063] of original specification). Thus, the limitation, wherein “the insulating layer includes an oxide layer and a nitride layer” introduces new matter and hence rejected.
Claim 35 recites the limitation wherein “the insulating layer includes an oxide layer and a nitride layer for protection against radiation”. Claim 35 depends from claim 34 wherein the insulator layer is defined. Claim 34 recites that “an insulating layer is formed over the trench”. The only insulating layer that is formed over the trench 236 in the elected embodiment of Fig. 11k, is the insulating layer 270. Layer 270 can have only one material, either an oxide or a nitride (para [0063] of original specification). Thus, the limitation, wherein “the insulating layer includes an oxide layer and a nitride layer” introduces new matter and hence rejected.
Claim 34 recites the limitation, “a substrate including a sacrificial surface” in line 2 of the claim. It appears that the “substrate” is referring to an intermediate process step, while the claim is directed to a final device. In the elected embodiment of Fig. 11k, the substrate 172 does not have a sacrificial surface, thus introducing new matter and hence rejected. Claims 35-42 depend from claim 34 and are rejected at least for the reasons above.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-2, 5-11, 13 and 34-42 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation wherein, “(e) a first insulating layer formed over the trench; and (f) a second insulating layer formed over the first insulating layer”. In the elected embodiment in Fig. 11(k), there are two insulating layers, layer 254 and layer 270, and 270 is above 254. Hence the first insulating layer has to be 254 and the second insulating layer has to be 270. Now the claim recites that the first insulating layer is formed over the trench. The trench is 236 and is defined by the sidewalls 250 and the bottom surface 246 as shown in Fig. 11(e). Therefore, it appears that the layer 254 is formed within the trench. Thus, it is unclear what applicant means by the “first insulating layer formed over the trench”, and hence rejected. Claims 2 and 5-11 depend from claim 1 and are rejected at least for the reasons above. For examining purposes, “first insulating layer formed over the trench” will be treated as an insulating layer that is formed within the trench.
Claim 13 recites the limitation wherein “the insulating layer includes an oxide layer and a nitride layer for protection against radiation”. Claim 13 depends from claim 12 wherein the insulator layer is defined. Claim 12 recites that “an insulating layer is formed over the trench”. The only insulating layer that is formed over the trench 236 in the elected embodiment of Fig. 11k is the insulating layer 270. Layer 270 can have only one material, either an oxide or a nitride (para [0063] of original specification). Thus, it is not clear how the layer can include both an oxide and a nitride layer, and hence rejected. For examination purposes, the limitation, wherein “the insulating layer includes an oxide layer and a nitride layer” will be treated as “the insulating layer includes -- either an oxide layer or a nitride layer --”.
Claim 35 recites the limitation wherein “the insulating layer includes an oxide layer and a nitride layer for protection against radiation”. Claim 35 depends from claim 34 wherein the insulator layer is defined. Claim 34 recites that “an insulating layer is formed over the trench”. The only insulating layer that is formed over the trench 236 in the elected embodiment of Fig. 11k is the insulating layer 270. Layer 270 can have only one material, either an oxide or a nitride (para [0063] of original specification). Thus, it is not clear how the layer can include both an oxide and a nitride layer, and hence rejected. For examination purposes, the limitation, wherein “the insulating layer includes an oxide layer and a nitride layer” will be treated as “the insulating layer includes -- either an oxide layer or a nitride layer --”.
Claim 34 recites the limitation, “a substrate including a sacrificial surface” in line 2 of the claim. It appears that the “substrate” is referring to an intermediate process step, while the claim is directed to a final device. In the elected embodiment of Fig. 11k, the substrate 172 does not have a sacrificial surface, and it is unclear what the applicant is referring to. Where applicant acts as his or her own lexicographer to specifically define a term of a claim contrary to its ordinary meaning, the written description must clearly redefine the claim term and set forth the uncommon definition so as to put one reasonably skilled in the art on notice that the applicant intended to so redefine that claim term. Process Control Corp. v. HydReclaim Corp., 190 F.3d 1350, 1357, 52 USPQ2d 1029, 1033 (Fed. Cir. 1999). The term “sacrificial” in claim 34 is used by the claim to mean “a removal of a surface” but the claim does not recite a removal step. Thus, the claim is indefinite and hence rejected. Claims 35-42 depend from claim 34 and are rejected at least for the reasons above. For examination purposes, “a sacrificial surface” will be treated as “a surface” with no patentable weight on the term “sacrificial”.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1 and 5-10 are rejected under 35 U.S.C. 103 as being unpatentable over Zeng et al. (US 2018/0366569 A1, newly cited), and further in view of Lipkin et al. (US 2002/0153594 A1, newly cited).
Re Claim 1, Zeng teaches a semiconductor device, comprising:
a substrate (100’+101, Fig. 28A, para [0087]);
a first semiconductor layer (102, Fig. 28A, para [0087]) comprising a first semiconductor material (102 is made of SiC, para [0087]) and disposed over the substrate (100’+101);
a second semiconductor layer (144’, Fig. 28A, para [0087]) comprising a second semiconductor material (144’ is silicon, para [0087]) dissimilar from the first semiconductor material (102 is SiC) and disposed over the first semiconductor layer (102); and
an electrical component formed at least partially within the second semiconductor layer (transistor device is formed in the device of Fig. 28A, para [0087]), wherein the electrical component includes,
(a) a trench (gate trench 110, Fig. 28A, also see Fig. 4, para [0045]) formed through the second semiconductor layer (144’, see Fig. 28A) and extending into the first semiconductor layer (102, see Fig. 28A),
(b) a first column of semiconductor material having a first conductivity type (P-type region in layer 144’, marked “1st column” in annotated Fig. 28A below) and extending through the second semiconductor layer (144’),
(c) a second column of semiconductor material having a second conductivity type (marked “2nd column” in annotated Fig. 28A below, n- type conductivity) opposite the first conductivity type and in contact with the first column of semiconductor material (“1st column”, see annotated Fig. 28A below),
(d) a source region (142, Fig. 28A, para [0034]) formed over the first column of semiconductor material (“1st column”),
(e) a first insulating layer (“gate oxide layer”, marked in annotated Fig. 28A below, also see Fig. 10 which shows the formation of gate oxide layer, para [0052]) formed over the trench (trench 110, also see 112(b) rejection above on how this limitation is treated); and
(f) a second insulating layer (interlevel dielectric 118, annotated in Fig. 28A below, para [0034], also see Fig. 1, where the layer is marked) formed over the first insulating layer (gate oxide layer).
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Zeng does not explicitly state that the first semiconductor material (102) is substantially defect-free.
However, it would be obvious to one of ordinary skill in the art, that the first semiconductor layer (102) has to be substantially defect-free, otherwise, it will cause current-leakage, lower breakdown voltage, and therefore will not be a functional device. Examiner notes that “substantially defect-free” means that there will be some defects in the semiconductor device and there is no definition of “substantially defect-free” in the original specification so that it can be quantified. The claim language does not preclude this treatment.
Zeng also does not explicitly disclose that the electrical component is formed “for protection against radiation”.
However, related art Lipkin discloses that silicon carbide provides significant advantages due to its excellent electronic properties, such as radiation hardness (para [0003]).
It would be obvious to one of ordinary skill in the art that the device disclosed by Zeng which is also made of silicon carbide (102 is SiC, para [0040], Zeng), will have the characteristics of radiation hardening as disclosed by Lipkin. Where applicant claims a composition in terms of a function, property or characteristic and the composition of the prior art is the same as that of the claim but the function is not explicitly disclosed by the reference, the examiner may make a rejection under both 35 U.S.C. 102 and 103. “There is nothing inconsistent in concurrent rejections for obviousness under 35 U.S.C. 103 and for anticipation under 35 U.S.C. 102.” In re Best, 562 F.2d 1252, 1255 n.4, 195 USPQ 430, 433 n.4 (CCPA 1977). This same rationale should also apply to product, apparatus, and process claims claimed in terms of function, property or characteristic (see MPEP 2112-III).
Re Claim 5, Zeng modified by Lipkin teaches the semiconductor device of claim 1, wherein the first semiconductor material includes silicon carbide or cubic silicon carbide (102 is made of SiC, Zeng, see claim 1 above).
Re Claim 6, Zeng modified by Lipkin teaches the semiconductor device of claim 1, wherein the second semiconductor material includes silicon (144’ is silicon, Zeng, see claim 1 above).
Re Claim 7, Zeng modified by Lipkin teaches the semiconductor device of claim 1, wherein the substrate includes a material selected from the group consisting of silicon, silicon carbide, cubic silicon carbide, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, diamond, and all families of III-V and II-VI semiconductor materials (substrate 100’ is silicon, Fig. 28A, Zeng).
Re Claim 8, Zeng modified by Lipkin teaches the semiconductor device of claim 1, wherein the substrate includes multiple layers (substrate is 100’+101, Fig. 28A, Zeng, see claim 1 above).
Re Claim 9, Zeng modified by Lipkin teaches the semiconductor device of claim 1, wherein the electrical component is selected from the group consisting of a transistor, diode, insulated gate bipolar transistor, cluster trench insulated gate bipolar transistor, and thyristor (transistor device is formed in the device of Fig. 28A, para [0087], Zeng).
Re Claim 10, Zeng modified by Lipkin teaches the semiconductor device of claim 1, but does not explicitly state that the second semiconductor layer (144’, Fig. 28A, Zeng) with the electrical component provides a first portion of a breakdown voltage for the semiconductor device and the first semiconductor layer (102, Fig. 28A, Zeng) and substrate (100’+101, Fig. 28A, Zeng) provides provide a second portion of the breakdown voltage for the semiconductor device.
However, it would be obvious to one of ordinary skill in the art, that each semiconductor layer will have its own breakdown voltage depending on the operating conditions, exceeding which the functionality of the layer will cease to operate. This is because the semiconductor device in Fig. 28A is vertical trench-gate MOSFET and the current flows through the layers 144’+102+101+100’ and each layer experiences a voltage distribution and will contribute to the breakdown. Therefore, it would be obvious to one of ordinary skill in the semiconductor art, that the second semiconductor layer (144’) with the electrical component will provide a first portion of a breakdown voltage for the semiconductor device (vertical trench-gate MOSFET of Fig. 28A) and the first semiconductor layer (102) and substrate (100’+101) will provide a second portion of the breakdown voltage for the semiconductor device (vertical trench-gate MOSFET of Fig. 28A).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Zeng et al. (US 2018/0366569 A1, newly cited) and Lipkin et al. (US 2002/0153594 A1, newly cited), and further in view of Ishiguro et al. (US 2008/0258239 A1, newly cited).
Re Claim 2, Zeng modified by Lipkin teaches the semiconductor device of claim 1, wherein the first insulating layer includes an oxide layer (first insulating layer is “gate oxide layer”, see claim 1 above).
Zeng does not explicitly disclose the material for the second insulating layer 118, and hence does not teach that the second insulating layer includes a nitride layer.
Related art, Ishiguro teaches that the dielectric passivation layer can be made of any appropriate passivation material like nitride, polyimide or oxide (para [0054]). It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to make the second insulating layer of Zeng from nitride as taught by Ishiguro. The use of a known material for its known purpose to yield predictable results is prima facie obvious. Also see KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Zeng et al. (US 2018/0366569 A1, newly cited) and Lipkin et al. (US 2002/0153594 A1, newly cited), and further in view of Kumar et al. (US 6573534 B1, of record).
Re Claim 11, Zeng modified by Lipkin teaches the semiconductor device of claim 1, but does not disclose that the semiconductor device operates within an electrical power supply to provide electrical operating potential for aerospace, data processing centers, LED lighting, charging stations for electric vehicles, and variable speed drives for electric motors.
In a related semiconductor art, Kumar teaches that a vertical MOSFET device (similar to Zeng’s device) can be applied as an inverter or an alternator for a vehicle (Col. 7, lines 20-23). It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, that the vertical MOSFET device of Zeng can be used as an inverter or an alternator for a vehicle as disclosed by Kumar.
Claims 12, 16-20, 33-40 and 42 are rejected under 35 U.S.C. 103 as being unpatentable over Zeng et al. (US 2018/0366569 A1, newly cited).
Re Claim 12, Zeng teaches a semiconductor device, comprising:
a substrate (100’+101, Fig. 28A, para [0087]);
a first semiconductor layer (102, Fig. 28A, para [0087]) comprising a first semiconductor material (102 is made of SiC, para [0087]) and disposed over the substrate (100’+101);
a second semiconductor layer (144’, Fig. 28A, para [0087]) comprising a second semiconductor material (144’ is silicon, para [0087]) and disposed over the first semiconductor layer (102);
an electrical component formed at least partially within the second semiconductor layer (transistor device is formed in the device of Fig. 28A, para [0087]), wherein the electrical component includes,
(a) a trench (gate trench 110, Fig. 28A, also see Fig. 4, para [0045]) formed through the second semiconductor layer (144’, see Fig. 28A) and extending into the first semiconductor layer (102, see Fig. 28A),
(b) a first column of semiconductor material having a first conductivity type (P-type region in layer 144’, marked “1st column” in annotated Fig. 28A above) and extending through the second semiconductor layer (144’),
(c) a second column of semiconductor material having a second conductivity type (marked “2nd column” in annotated Fig. 28A above, n- type conductivity) opposite the first conductivity type and in contact with the first column of semiconductor material (“1st column”, see annotated Fig. 28A above), and
(d) an insulating layer (interlevel dielectric 118, annotated in Fig. 28A above, para [0034], also see Fig. 1, where the layer is marked) formed over the trench (110).
Zeng does not explicitly state that the first semiconductor material (102) is substantially defect-free.
However, it would be obvious to one of ordinary skill in the art, that the first semiconductor layer (102) has to be substantially defect-free, otherwise, it will cause current-leakage, lower breakdown voltage, and therefore will not be a functional device. Examiner notes that “substantially defect-free” means that there will be some defects in the semiconductor device and there is no definition of “substantially defect-free” in the original specification so that it can be quantified. The claim language does not preclude this treatment.
Re Claim 16, Zeng teaches the semiconductor device of claim 12, wherein the first semiconductor material includes silicon carbide or cubic silicon carbide (102 is made of SiC, see claim 12 above).
Re Claim 17, Zeng teaches the semiconductor device of claim 12, wherein the second semiconductor material includes silicon (144’ is silicon, see claim 12 above).
Re Claim 18, Zeng teaches the semiconductor device of claim 12, wherein the substrate includes a material selected from the group consisting of silicon, silicon carbide, cubic silicon carbide, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, diamond, and all families of III-V and II-VI semiconductor materials (substrate 100’ is silicon, Fig. 28A).
Re Claim 19, Zeng teaches the semiconductor device of claim 12, wherein the substrate includes multiple layers (substrate is 100’+101, Fig. 28A, see claim 12 above).
Re Claim 20, Zeng teaches the semiconductor device of claim 12, but does not explicitly state that the second semiconductor layer (144’, Fig. 28A) with the electrical component provides a first portion of a breakdown voltage for the semiconductor device and the first semiconductor layer (102) and substrate (100’+101) provides provide a second portion of the breakdown voltage for the semiconductor device.
However, it would be obvious to one of ordinary skill in the art, that each semiconductor layer will have its own breakdown voltage depending on the operating conditions, exceeding which the functionality of the layer will cease to operate. This is because the semiconductor device in Fig. 28A is vertical trench-gate MOSFET and the current flows through the layers 144’+102+101+100’ and each layer experiences a voltage distribution and will contribute to the breakdown. Therefore, it would be obvious to one of ordinary skill in the semiconductor art, that the second semiconductor layer (144’) with the electrical component will provide a first portion of a breakdown voltage for the semiconductor device (vertical trench-gate MOSFET of Fig. 28A) and the first semiconductor layer (102) and substrate (100’+101) will provide a second portion of the breakdown voltage for the semiconductor device (vertical trench-gate MOSFET of Fig. 28A).
Re Claim 33, Zeng teaches the semiconductor device of claim 12, wherein the electrical component further includes a source region (142, Fig. 28A, para [0034]) formed over the first column of semiconductor material (“1st column”, see annotated Fig. 28A above).
Re Claim 34, Zeng teaches a semiconductor device, comprising:
a substrate (100’+101, Fig. 28A, para [0087]) including a sacrificial surface (top surface of 100’+101, see 112(b) rejection above on how the limitation is treated);
a first semiconductor layer (102, Fig. 28A, para [0087]) comprising a first semiconductor material (102 is made of SiC, para [0087]) disposed over the sacrificial surface of the substrate (top surface of 100’+101); and
disposing a second semiconductor layer (144’, Fig. 28A, para [0087]) comprising a second semiconductor material (144’ is silicon, para [0087]) over the first semiconductor layer (102);
forming an electrical component at least partially within the second semiconductor layer (transistor device is formed in the device of Fig. 28A, para [0087]), wherein the electrical component includes,
(a) a trench (gate trench 110, Fig. 28A, also see Fig. 4, para [0045]) formed through the second semiconductor layer (144’, see Fig. 28A) and extending into the first semiconductor layer (102, see Fig. 28A),
(b) a first column of semiconductor material having a first conductivity type (P-type region in layer 144’, marked “1st column” in annotated Fig. 28A above) and extending through the second semiconductor layer (144’),
(c) a second column of semiconductor material having a second conductivity type (marked “2nd column” in annotated Fig. 28A above, n- type conductivity) opposite the first conductivity type and in contact with the first column of semiconductor material (“1st column”, see annotated Fig. 28A above), and
(d) an insulating layer (interlevel dielectric 118, annotated in Fig. 28A above, para [0034], also see Fig. 1, where the layer is marked) formed over the trench (110).
Zeng does not explicitly state that the first semiconductor material (102) is substantially defect-free.
However, it would be obvious to one of ordinary skill in the art, that the first semiconductor layer (102) has to be substantially defect-free, otherwise, it will cause current-leakage, lower breakdown voltage, and therefore will not be a functional device. Examiner notes that “substantially defect-free” means that there will be some defects in the semiconductor device and there is no definition of “substantially defect-free” in the original specification so that it can be quantified. The claim language does not preclude this treatment.
Re Claim 36, Zeng teaches the semiconductor device of claim 34, wherein the first semiconductor material includes silicon carbide or cubic silicon carbide (102 is made of SiC, see claim 34 above).
Re Claim 37, Zeng teaches the semiconductor device of claim 34, wherein the second semiconductor material includes silicon (144’ is silicon, see claim 34 above).
Re Claim 38, Zeng teaches the semiconductor device of claim 34, wherein the substrate includes a material selected from the group consisting of silicon, silicon carbide, cubic silicon carbide, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, diamond, and all families of III-V and II-VI semiconductor materials (substrate 100’ is silicon, Fig. 28A).
Re Claim 39, Zeng teaches the semiconductor device of claim 34, wherein the substrate includes multiple layers (substrate is 100’+101, Fig. 28A, see claim 34 above).
Re Claim 40, Zeng teaches the semiconductor device of claim 34, but does not explicitly state that the second semiconductor layer (144’, Fig. 28A) with the electrical component provides a first portion of a breakdown voltage for the semiconductor device and the first semiconductor layer (102) and substrate (100’+101) provides provide a second portion of the breakdown voltage for the semiconductor device.
However, it would be obvious to one of ordinary skill in the art, that each semiconductor layer will have its own breakdown voltage depending on the operating conditions, exceeding which the functionality of the layer will cease to operate. This is because the semiconductor device in Fig. 28A is vertical trench-gate MOSFET and the current flows through the layers 144’+102+101+100’ and each layer experiences a voltage distribution and will contribute to the breakdown. Therefore, it would be obvious to one of ordinary skill in the semiconductor art, that the second semiconductor layer (144’) with the electrical component will provide a first portion of a breakdown voltage for the semiconductor device (vertical trench-gate MOSFET of Fig. 28A) and the first semiconductor layer (102) and substrate (100’+101) will provide a second portion of the breakdown voltage for the semiconductor device (vertical trench-gate MOSFET of Fig. 28A).
Re Claim 42, Zeng teaches the semiconductor device of claim 34, wherein the electrical component is selected from the group consisting of a transistor, diode, insulated gate bipolar transistor, cluster trench insulated gate bipolar transistor, and thyristor (transistor device is formed in the device of Fig. 28A, para [0087]).
Claims 13 and 35 are rejected under 35 U.S.C. 103 as being unpatentable over Zeng et al. (US 2018/0366569 A1, newly cited), and further in view of Ishiguro et al. (US 2008/0258239 A1, newly cited).
Re Claim 13, Zeng teaches the semiconductor device of claim 12, but does not disclose that the insulating layer includes either an oxide layer or a nitride layer for protection against radiation.
Related art, Ishiguro teaches that the dielectric passivation layer can be made of any appropriate passivation material like nitride, polyimide or oxide (para [0054]). It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to make the insulating layer of Zeng from either oxide or nitride as taught by Ishiguro. The use of a known material for its known purpose to yield predictable results is prima facie obvious. Also see KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
Additionally, since, Zeng modified by Ishiguro teaches the same material for the insulating layer as recited in the claim, it would be obvious to one of ordinary skill in the art, that the material will provide protection against radiation as recited in the claim. Where applicant claims a composition in terms of a function, property or characteristic and the composition of the prior art is the same as that of the claim but the function is not explicitly disclosed by the reference, the examiner may make a rejection under both 35 U.S.C. 102 and 103. “There is nothing inconsistent in concurrent rejections for obviousness under 35 U.S.C. 103 and for anticipation under 35 U.S.C. 102.” In re Best, 562 F.2d 1252, 1255 n.4, 195 USPQ 430, 433 n.4 (CCPA 1977).
Re Claim 35, Zeng teaches the semiconductor device of claim 34, but does not disclose that the insulating layer includes either an oxide layer or a nitride layer for protection against radiation.
Related art, Ishiguro teaches that the dielectric passivation layer can be made of any appropriate passivation material like nitride, polyimide or oxide (para [0054]). It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to make the insulating layer of Zeng from either oxide or nitride as taught by Ishiguro. The use of a known material for its known purpose to yield predictable results is prima facie obvious. Also see KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
Additionally, since, Zeng modified by Ishiguro teaches the same material for the insulating layer as recited in the claim, it would be obvious to one of ordinary skill in the art, that the material will provide protection against radiation as recited in the claim. Where applicant claims a composition in terms of a function, property or characteristic and the composition of the prior art is the same as that of the claim but the function is not explicitly disclosed by the reference, the examiner may make a rejection under both 35 U.S.C. 102 and 103. “There is nothing inconsistent in concurrent rejections for obviousness under 35 U.S.C. 103 and for anticipation under 35 U.S.C. 102.” In re Best, 562 F.2d 1252, 1255 n.4, 195 USPQ 430, 433 n.4 (CCPA 1977).
Claims 21 and 41 are rejected under 35 U.S.C. 103 as being unpatentable over Zeng et al. (US 2018/0366569 A1, newly cited), and further in view of Kumar et al. (US 6573534 B1, of record).
Re Claim 21, Zeng teaches the semiconductor device of claim 12, but does not disclose that the semiconductor device operates within an electrical power supply to provide electrical operating potential for aerospace, data processing centers, LED lighting, charging stations for electric vehicles, and variable speed drives for electric motors.
In a related semiconductor art, Kumar teaches that a vertical MOSFET device (similar to Zeng’s device) can be applied as an inverter or an alternator for a vehicle (Col. 7, lines 20-23). It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, that the vertical MOSFET device of Zeng can be used as an inverter or an alternator for a vehicle as disclosed by Kumar.
Re Claim 41, Zeng teaches the semiconductor device of claim 34, but does not disclose that the semiconductor device operates within an electrical power supply to provide electrical operating potential for aerospace, data processing centers, LED lighting, charging stations for electric vehicles, and variable speed drives for electric motors.
In a related semiconductor art, Kumar teaches that a vertical MOSFET device (similar to Zeng’s device) can be applied as an inverter or an alternator for a vehicle (Col. 7, lines 20-23). It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, that the vertical MOSFET device of Zeng can be used as an inverter or an alternator for a vehicle as disclosed by Kumar.
Rejection 2
Claim Rejections - 35 USC § 103
Claims 12-13, 17-18, 20, 33-35, 37-38, 40 and 42 are rejected under 35 U.S.C. 103 as being unpatentable over Anderson et al. (US 2014/0264582 A1, newly cited).
Re Claim 12, Anderson teaches a semiconductor device, comprising:
a substrate (12, Fig. 3, para [0027]);
a first semiconductor layer (14, Fig. 3, para [0027]) comprising a first semiconductor material (14 is 1st semiconductor material) and disposed over the substrate (12);
a second semiconductor layer (16, Fig. 3, para [0027]) comprising a second semiconductor material (16 is 2nd semiconductor material) and disposed over the first semiconductor layer (14);
an electrical component formed at least partially within the second semiconductor layer (transistor device is formed in Fig. 3, para [0004]), wherein the electrical component includes,
(a) a trench (18, Fig. 3, para [0028]) formed through the second semiconductor layer (16) and extending into the first semiconductor layer (14, see Fig. 3),
(b) a first column of semiconductor material having a first conductivity type (22, p-type, Fig. 3, para [0029]) and extending through the second semiconductor layer (16),
(c) a second column of semiconductor material having a second conductivity type (20, n-type, Fig. 3, para [0029]) opposite the first conductivity type and in contact with the first column of semiconductor material (22, see Fig. 3), and
(d) an insulating layer (30, Fig. 3, para [0029]) formed over the trench (18).
Anderson does not explicitly state that the first semiconductor material (14) is substantially defect-free.
However, it would be obvious to one of ordinary skill in the art, that the first semiconductor layer (14) has to be substantially defect-free, otherwise, it will cause current-leakage, lower breakdown voltage, and therefore will not be a functional device. Examiner notes that “substantially defect-free” means that there will be some defects in the semiconductor device and there is no definition of “substantially defect-free” in the original specification so that it can be quantified. The claim language does not preclude this treatment.
Re Claim 13, Anderson teaches the semiconductor device of claim 12, wherein the insulating layer (30) includes either an oxide layer or a nitride layer (30 can be an oxide layer, para [0045]).
Anderson does not explicitly state that the insulator layer provides protection against radiation.
However, Anderson teaches the same material for the insulating layer as recited in the claim, and hence, it would be obvious to one of ordinary skill in the art that the same material will provide protection against radiation as recited in the claim. Where applicant claims a composition in terms of a function, property or characteristic and the composition of the prior art is the same as that of the claim but the function is not explicitly disclosed by the reference, the examiner may make a rejection under both 35 U.S.C. 102 and 103. “There is nothing inconsistent in concurrent rejections for obviousness under 35 U.S.C. 103 and for anticipation under 35 U.S.C. 102.” In re Best, 562 F.2d 1252, 1255 n.4, 195 USPQ 430, 433 n.4 (CCPA 1977).
Re Claim 17, Anderson teaches the semiconductor device of claim 12, wherein the second semiconductor material includes silicon (16 is 2nd semiconductor material which is silicon, para [0033]).
Re Claim 18, Anderson teaches the semiconductor device of claim 12, wherein the substrate includes a material selected from the group consisting of silicon, silicon carbide, cubic silicon carbide, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, diamond, and all families of III-V and II-VI semiconductor materials (substrate 12 is silicon, para [0031]).
Re Claim 20, Anderson teaches the semiconductor device of claim 12, but does not explicitly state that the second semiconductor layer (16) with the electrical component provides a first portion of a breakdown voltage for the semiconductor device and the first semiconductor layer (14) and substrate (12) provides provide a second portion of the breakdown voltage for the semiconductor device.
However, it would be obvious to one of ordinary skill in the art, that each semiconductor layer will have its own breakdown voltage depending on the operating conditions, exceeding which the functionality of the layer will cease to operate. In the transistor device of Fig. 3, the current flows through all the layers, each layer having their own carrier concentrations and each experiencing a voltage distribution and will contribute to the breakdown. Therefore, it would be obvious to one of ordinary skill in the semiconductor art, that the second semiconductor layer (16) with the electrical component will provide a first portion of a breakdown voltage for the semiconductor device (device in Fig. 3) and the first semiconductor layer (14) and substrate (12) will provide a second portion of the breakdown voltage for the semiconductor device.
Re Claim 33, Anderson teaches the semiconductor device of claim 12, wherein the electrical component further includes a source region (24, Fig. 3, para [0029]) formed over the first column of semiconductor material (22).
Re Claim 34, Anderson teaches a semiconductor device, comprising:
a substrate (12, Fig. 3, para [0027]) including a sacrificial surface (top surface of 12, see 112(b) rejection above on how the limitation is treated);
a first semiconductor layer (14, Fig. 3, para [0027]) comprising a first semiconductor material (14 is 1st semiconductor material) disposed over the sacrificial surface of the substrate (top surface of 12); and
disposing a second semiconductor layer (16, Fig. 3, para [0027]) comprising a second semiconductor material (16 is 2nd semiconductor material) over the first semiconductor layer (14);
forming an electrical component at least partially within the second semiconductor layer (transistor device is formed in Fig. 3, para [0004]), wherein the electrical component includes,
(a) a trench (18, Fig. 3, para [0028]) formed through the second semiconductor layer (16) and extending into the first semiconductor layer (14, see Fig. 3),
(b) a first column of semiconductor material having a first conductivity type (22, p-type, Fig. 3, para [0029]) and extending through the second semiconductor layer (16),
(c) a second column of semiconductor material having a second conductivity type (20, n-type, Fig. 3, para [0029]) opposite the first conductivity type and in contact with the first column of semiconductor material (22, see Fig. 3), and
(d) an insulating layer (30, Fig. 3, para [0029]) formed over the trench (18).
Anderson does not explicitly state that the first semiconductor material (14) is substantially defect-free.
However, it would be obvious to one of ordinary skill in the art, that the first semiconductor layer (14) has to be substantially defect-free, otherwise, it will cause current-leakage, lower breakdown voltage, and therefore will not be a functional device. Examiner notes that “substantially defect-free” means that there will be some defects in the semiconductor device and there is no definition of “substantially defect-free” in the original specification so that it can be quantified. The claim language does not preclude this treatment.
Re Claim 35, Anderson teaches the semiconductor device of claim 34, wherein the insulating layer (30) includes either an oxide layer or a nitride layer (30 can be an oxide layer, para [0045]).
Anderson does not explicitly state that the insulator layer provides protection against radiation.
However, Anderson teaches the same material for the insulating layer as recited in the claim, and hence, it would be obvious to one of ordinary skill in the art that the same material will provide protection against radiation as recited in the claim. Where applicant claims a composition in terms of a function, property or characteristic and the composition of the prior art is the same as that of the claim but the function is not explicitly disclosed by the reference, the examiner may make a rejection under both 35 U.S.C. 102 and 103. “There is nothing inconsistent in concurrent rejections for obviousness under 35 U.S.C. 103 and for anticipation under 35 U.S.C. 102.” In re Best, 562 F.2d 1252, 1255 n.4, 195 USPQ 430, 433 n.4 (CCPA 1977).
Re Claim 37, Anderson teaches the semiconductor device of claim 34, wherein the second semiconductor material includes silicon (16 is 2nd semiconductor material which is silicon, para [0033]).
Re Claim 38, Anderson teaches the semiconductor device of claim 34, wherein the substrate includes a material selected from the group consisting of silicon, silicon carbide, cubic silicon carbide, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, diamond, and all families of III-V and II-VI semiconductor materials (substrate 12 is silicon, para [0031]).
Re Claim 40, Anderson teaches the semiconductor device of claim 34, but does not explicitly state that the second semiconductor layer (16) with the electrical component provides a first portion of a breakdown voltage for the semiconductor device and the first semiconductor layer (14) and substrate (12) provides provide a second portion of the breakdown voltage for the semiconductor device.
However, it would be obvious to one of ordinary skill in the art, that each semiconductor layer will have its own breakdown voltage depending on the operating conditions, exceeding which the functionality of the layer will cease to operate. In the transistor device of Fig. 3, the current flows through all the layers, each layer having their own carrier concentrations and each experiencing a voltage distribution and will contribute to the breakdown. Therefore, it would be obvious to one of ordinary skill in the semiconductor art, that the second semiconductor layer (16) with the electrical component will provide a first portion of a breakdown voltage for the semiconductor device (device in Fig. 3) and the first semiconductor layer (14) and substrate (12) will provide a second portion of the breakdown voltage for the semiconductor device.
Re Claim 42, Anderson teaches The semiconductor device of claim 34, wherein the electrical component is selected from the group consisting of a transistor, diode, insulated gate bipolar transistor, cluster trench insulated gate bipolar transistor, and thyristor (transistor device is formed in Fig. 3, para [0004]).
Response to Arguments
Applicant’s arguments with respect to claims 1 and 12 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/P.D./Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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