Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on July 21, 2026 has been entered.
Response to Arguments
Applicant’s arguments with respect to claim(s) 7-9, 11-18, 20-25, 27-33 have been considered but are moot in view of the newly cited prior art.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-6, 33 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zluc et al (USPGPUB 20200365573, hereinafter “Zluc”) in view of Andry et al (USPGPUB 20080284037, hereinafter “Andry”) in further view of Takachi (USPGPUB 20190019831).
Regarding Claim 1, Zluc teaches (Fig. 26) a package comprising: an interposer substrate (102) including at least one via (118) including a hole extending from a top surface of the interposer substrate (102) to a bottom surface of the interposer substrate (102); an optical sensor die (106) disposed on the interposer substrate (102);
Zluc is silent with regards to a silicon substrate that would make for the vias being silicon vias.
Andry teaches a silicon interposer substrate ([0027], “a thinned silicon substrate (12b) and a plurality of conductive through-vias (12c)”)
It would have been obvious to a person of ordinary skill in the art, absent unexpected results, before the date of effective filing, to incorporate the silicon material of Andry into the package of Zluc in order to arrive at the expected result of creating a device with the known benefits of a silicon substrate, such as cost-effectiveness and thermal/mechanical stability with reasonable expectation of success.
Zluc in view of Andry is silent with regards to an optical sensor die disposed on the topside surface of the semiconductor die having a top side, a bottom side, and a sidewall, the semiconductor die being disposed on the interposer substrate with the bottom side electrically coupled to the top surface of the interposer substrate; and a molding material disposed on at least on a portion of the sidewall of the semiconductor die.
Takachi teaches (Fig. 16) the optical sensor die (10) disposed on the topside surface of a semiconductor die (20) having a top side, a bottom side, and a sidewall, the semiconductor die being disposed on the interposer substrate with the bottom side electrically coupled to the top surface of the interposer substrate (the package being incorporated onto the interposer substrate would be obvious to one of ordinary skill in the art); and a molding material (261) disposed on at least on a portion of the sidewall of the semiconductor die (20).
It would have been obvious to a person of ordinary skill in the art, absent unexpected results, before the date of effective filing, to incorporate the packaging scheme and logic die of Takachi into the device of Zluc in view of Andry in order to arrive at the expected result of creating a device with increased utility given the logic die as well as increased stability given the encapsulant structure with reasonable expectation of success.
Regarding Claim 2, Zluc in view of Andry and Takachi teaches the package of claim 1, wherein the semiconductor die (106 ) has a width, and the interposer substrate (102) has a width that is greater than the width of the semiconductor die (the interposer substrate 102 is seen having a greater width than that of die 106).
Regarding Claim 3, Zluc in view of Andry and Takachi teaches the package of claim 1, further comprising a glass cover (114) disposed above the optical sensor die (the sensor die and semiconductor die would be understood to be in the same location as understood by one of ordinary skill in the art).
Regarding Claim 4, Zluc in view of Andry and Takachi teaches (Zluc Fig. 26) the package of claim 3 further comprising: a non-transparent black coating (Zluc 164) disposed on an edge portion of the glass cover (Zluc 114) disposed above the optical sensor die (one of ordinary skill in the art would understand the optical sensor die as being situated at element 106 of Zluc).
Regarding Claim 5, Zluc in view of Andry and Takachi teaches the package of claim 1, further comprising an array of conductive material (Takashi 42) disposed on the bottom surface of the interposer substrate (Takashi 20), wherein the array of conductive material (42) is a ball grid array of solder (element 42 of Takashi is a ball grid array of solder).
Regarding Claim 6, Zluc in view of Andry and Takachi teaches a package of claim 1, wherein semiconductor die is an application- specific integrated circuit (ASIC) die, the ASIC die including at least one backside through- semiconductor via (BTSV) for electrical connections to the optical sensor die. (the semiconductor die being application-specific is understood as obvious to one of ordinary skill in the art)
Regarding Claim 33, Zluc in view of Andry and Takachi teaches the package of claim 1, wherein the interposer substrate is a silicon interposer (Zluc 102); and wherein the at least one through-silicon via (Zluc 118) includes a vertical hole extending between the top surface of the silicon interposer (Zluc 102) and the bottom surface of the silicon interposer with conductive material being disposed in the hole (Silicon vias 118 of Zluc are seen as conductive material placed within vertical holes).
Claim(s) 7-10, 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tan et al (USPGPUB 20180182801, hereinafter “Tan”) in view of Andry and Yen et al (USPGPUB 20220336332, hereinafter “Yen”).
Regarding Claim 7, Tan teaches (Fig. 3i) a package (100) comprising: an interposer substrate (105) including at least one through-substrate via (122) electrically connecting a top surface of the interposer substrate (105) to a bottom surface of the interposer substrate (105); at least one semiconductor die (180) disposed on the interposer substrate (105) with a bottom side of the at least one semiconductor die (180) being electrically coupled to the top surface of the interposer substrate (105); an array of conductive material (130) disposed on the bottom surface of the interposer substrate (105), to form external contacts of the package (100); and an image signal processing (ISP) (170) die disposed on a back surface of the interposer substrate (105) opposite the at least one semiconductor die (180)
Tan is silent with regards to through-substrate via being through-silicon vias.
Andry teaches the use of through-silicon vias in an interposer substrate ([0027], “a thinned silicon substrate (12b) and a plurality of conductive through-vias (12c)”)
It would have been obvious to a person of ordinary skill in the art, absent unexpected results, before the date of effective filing, to incorporate the silicon material of Andry into the package of Tan in order to arrive at the expected result of creating a device with the known benefits of a silicon substrate, such as cost-effectiveness and thermal/mechanical stability with reasonable expectation of success.
Tan in view of Andry is silent with regards to a layer of molding material disposed on the bottom surface of the interposer substrate to embed the at least one semiconductor die and the array of conductive material and wherein the ISP die is embedded in the layer of molding material.
Yen teaches (Fig. 19) a layer of molding material (45) disposed on the bottom surface of the interposer substrate (2) to embed the at least one semiconductor die (47) and the array of conductive material (42) and wherein the ISP die (48) is embedded in the layer of molding material (45).
It would have been obvious to a person of ordinary skill in the art, absent unexpected results, before the date of effective filing, to incorporate the encapsulation and packaging scheme of Yen into the device of Tan in view of Andry in order to arrive at the expected result of creating a more robust device with improved structural integrity with reasonable expectation of success.
Regarding Claim 8, Tan in view of Andry and Yen teaches (Tan Fig. 3i) the package of claim 7, wherein the image signal processing (ISP) die (Tan 170) is flip chip mounted on the back surface of the interposer substrate (Tan 105).
Regarding Claim 9, Tan in view of Andry and Yen teaches (Tan Fig. 3i) the package of claim 7, wherein the at least one semiconductor die (Tan 180) has a width, and the interposer substrate (Tan 105) has a width that is greater than the width of the at least one semiconductor die (Tan 180).
Regarding Claim 10, Tan in view of Andry and Yen teaches (Tan Fig. 3i) The package of claim 7, wherein the at least one semiconductor die (180) includes an optical sensor ([0024], “the sensor chip 180 may be an image-sensing semiconductor chip (hereinafter “image sensor”). “die, and the package further includes a glass cover (155) disposed above the optical sensor die (180).
Regarding Claim 12, Tan in view of Andry Yen teaches (Fig. 3i of Tan) the package of claim 7, wherein the array of conductive material (130) disposed on the bottom surface of the interposer substrate (Tan 105) is a ball grid array of solder (conductive material 130 of Tan is seen being a ball grid array of solder).
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tan in view of Andry and Yen as applied to claim 7 above, and further in view of Takachi.
Regarding Claim 13, Tan in view of Andry and Yen teaches the package of claim 7, but is silent with regards to a package wherein the at least one semiconductor die is a stack of an optical sensor die disposed above an application-specific integrated circuit (ASIC) die, the ASIC die including at least one backside through-semiconductor via (BTSV) for electrical connections to an optical sensor die.
Takachi teaches (Fig. 12) a package wherein the at least one semiconductor die (40) is a stack of an optical sensor die (10) disposed above an application-specific integrated circuit (ASIC) die, the ASIC die including at least one backside through-semiconductor via (BTSV) for electrical connections to an optical sensor die (vias for communication with the optical die 10 within the ASIC die 20 would be obvious to one of ordinary skill in the art).
It would have been obvious to a person of ordinary skill in the art, absent unexpected results, before the date of effective filing, to incorporate the semiconductor die stack of Takachi into the package of Tan in view of Andry and Yen in order to arrive at the expected result of creating a device whose die stack imparts an improved utility with reasonable expectation of success.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tan in view of Andry and Yen as applied to claim 10 above, and further in view of Cho et al (USPGPUB 20210028217, hereinafter “Cho”).
Regarding Claim 11, Tan in view of Andry and Yen teaches the package of claim 10, but is silent with regards to a non-transparent black coating disposed on an edge portion of the glass cover disposed above the optical sensor die.
Cho teaches a non-transparent black coating (DM) disposed on an edge portion of the glass cover (400) disposed above the optical sensor die (100).
It would have been obvious to a person of ordinary skill in the art, absent unexpected results, before the date of effective filing, to incorporate the black coating of Cho into the device of Tan in view of Andry and Yen in order to arrive at the expected result of creating a device which allows for a more refined light signal management with reasonable expectation of success.
Claim(s) 24, is/are rejected under 35 U.S.C. 103 as being unpatentable over Tan in view of Andry and in further view of Takachi.
Regarding Claim 24, Tan teaches (Fig. 3i) a package comprising: an interposer substrate (105) including at least one first through-silicon () via electrically connecting a top surface of the interposer substrate (105) to a bottom surface of the interposer substrate (105) ; an application specific integrated circuit (ASIC) (180) disposed on the interposer substrate (105) with a bottom side of the ASIC (180) electrically coupled to the top surface of the interposer substrate (105), the ASIC (180) including at least one second through-silicon via (122); and an image signal processing (ISP) die (170) disposed on a back surface of the interposer substrate (105) opposite the application specific integrated circuit (ASIC) (180).
Tan is silent with regards to a silicon substrate that would make for the vias being silicon vias.
Andry teaches a silicon interposer substrate ([0027], “a thinned silicon substrate (12b) and a plurality of conductive through-vias (12c)”)
It would have been obvious to a person of ordinary skill in the art, absent unexpected results, before the date of effective filing, to incorporate the silicon material of Andry into the package of Tan in order to arrive at the expected result of creating a device with the known benefits of a silicon substrate, such as cost-effectiveness and thermal/mechanical stability with reasonable expectation of success.
Tan in view of Andry is silent with regards to an optical sensor die disposed on the ASIC with a bottom side of the optical sensor die electrically coupled to the at least one second through-silicon via.
Takachi teaches (Fig. 7) an optical sensor die disposed on the ASIC (20) with a bottom side of the optical sensor die (20) electrically coupled to the at least one second through-silicon via (the optical sensor die, being disposed on the ASIC, being electrically coupled)
It would have been obvious to a person of ordinary skill in the art, absent unexpected results, before the date of effective filing, to incorporate the packaging scheme of Takachi into the package of Tan in view of Andry in order to arrive at the expected result of creating a device with more utility given more logic components enhancing the utility of the die with reasonable expectation of success.
Regarding Claim 27, Tan in view of Andry and Takachi teaches (Fig. 3i) the package of claim 24, wherein the ASIC (180) has a width, and the interposer substrate (105) has a width that is greater than (width of ASIC 180 is seen being greater than that of interposer 105) the width of the ASIC (180).
Regarding Claim 28, Tan in view of Andry and Takachi teaches the package of claim 24, further comprising a glass (155) cover disposed above the optical sensor die (180; the location of the optical sensor die being substantially that of ASIC 180, as would be obvious to one of ordinary skill in the art).
Regarding Claim 30, Tan in view of Andry and Takachi teaches the package of claim 28, further comprising a dam disposed (150) on an edge portion of the top surface of the glass cover (155), the dam coupling the glass cover (155) to the optical sensor die (Tan 180, Takachi 20).
Regarding Claim 31, Tan in view of Andry and Takachi teaches the package of claim 24, wherein the interposer substrate is a silicon interposer (Andry [0027], “a thinned silicon substrate (12b) and a plurality of conductive through-vias (12c)”).
Regarding Claim 32, Tan in view of Andry and Takachi teaches the package of claim 31, further comprising a redistribution layer disposed on (the presence of a redistribution layer would be inherent to these devices so as to allow the ASIC/optical sensor dies to be compatible with the silicon interposer) the top surface of the silicon interposer (Tan 150).
Claim(s) 25, 26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tan in view of Takachi as applied to claim 24 above, and further in view of Yen.
Regarding Claim 25, Tan in view of Takachi teaches (Tan Fig. 3i) the package of claim 24, further comprising: an array of conductive material (Tan 130) disposed on bottom surface of the interposer substrate (105) to form external contacts of the package (100); and a layer of molding material (190) disposed on the bottom surface of the interposer substrate (105) to embed the application specific integrated circuit (ASIC) (180).
Tan in view of Takachi is silent with regards to the molding material embedding the array of conductive material.
Yen teaches (Fig. 6) the molding material embedding (45) the array of conductive material (42).
It would have been obvious to a person of ordinary skill in the art, absent unexpected results, before the date of effective filing, to incorporate the encapsulation and packaging scheme of Yen into the device of Tan in view of Takachi in order to arrive at the expected result of creating a more robust device with improved structural integrity with reasonable expectation of success.
Regarding Claim 26, Tan in view of Takachi and Yen teaches (Yen Fig. 6) the package of claim 25, wherein the ISP die (Yen 48) is embedded in the layer of molding material (Yen 45).
Claim(s) 29 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tan in view of Andry and Takachi as applied to claim 28 above, and further in view of Cho.
Regarding Claim 29, Tan in view of Andry and Takachi teaches the package of claim 28, but is silent with regards to a non-transparent black coating disposed on an edge portion of the glass cover.
Cho teaches a non-transparent black coating (DM) disposed on an edge portion of the glass cover (400) disposed above the optical sensor die (100).
It would have been obvious to a person of ordinary skill in the art, absent unexpected results, before the date of effective filing, to incorporate the black coating of Cho into the device of Tan in view of Andry and Takachi in order to arrive at the expected result of creating a device which allows for a more refined light signal management with reasonable expectation of success.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VICTOR J LASASSO whose telephone number is (703)756-5668. The examiner can normally be reached M-F 8-5 EST.
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/V.J.L./
Examiner, Art Unit 2898
/JESSE Y MIYOSHI/
Primary Examiner, Art Unit 2898
