Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-13 and 24-32 have been considered but are moot in view of the newly cited prior art.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 7-13, 25-32 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding Claim 7, Claim 7 contains the phrase, “a layer of molding material disposed between the interposer substrate and the array of conductive material, the layer of molding material including at least one through-mold via for electrical connection between the interposer substrate and the array of conductive material”. In light of the amendments filed December 10, 2025, there is no support for the above limitation, as the conductive material and the interposer substrate, being in contact with each other, have no mold layer between them (see Fig. 1 of the instant application), and the through-mold vias are not seen electrically coupling the interposer substrate and the array of conductive material. Claims 8-13 are dependent upon Claim 7 and therefore inherit the above deficiencies. In the interest of compact prosecution, these claims will be examined as though the deficient phrases were omitted.
Regarding Claim 25, Claim 25 contains the phrase, “a layer of molding material disposed between the interposer substrate and the array of conductive material”. There is no support for this limitation, as the conductive material and the interposer substrate, being in contact with each other, have no mold layer between them (see Fig. 1 of the instant application), and the through-mold vias are not seen electrically coupling the interposer substrate and the array of conductive material. Claim 26 is dependent upon Claim 25 and therefore inherit the above deficiencies. In the interest of compact prosecution, these claims will be examined as though the deficient phrases were omitted.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-6, 24-25, 27-30 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kwon et al (USPGPUB 20220052097, hereinafter “Kwon”) in view of Cho et al (USPGPUB 20210028217, hereinafter “Cho”)
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Kwon Fig. 12
Regarding Claim 1, Kwon teaches (Fig. 12) package comprising: an interposer substrate (PS) a semiconductor die (1) having a top side (11u), a bottom side (11b), and a sidewall (side wall of semiconductor die 1, hereinafter SW1), the semiconductor die (1) being disposed on (semiconductor die 1 is seen disposed on the interposer substrate PS) the interposer substrate (PS); an optical sensor die (3) disposed on a top surface of (surface located at top side 11u of the semiconductor die 1) the semiconductor die (1); a molding material (51) disposed on at least on a portion (molding material 51 is seen disposed on the semiconductor die 1) of the semiconductor die (1).
Kwon is silent with regards to the interposer substrate including at least one through-silicon via electrically connecting a top surface of the interposer substrate to a bottom surface of the interposer substrate; the bottom side of the semiconductor die electrically coupled to the top surface of the interposer substrate; and an array of conductive material disposed on the bottom surface of the interposer substrate.
Cho teaches (Fig. 10) the interposer substrate (500) including at least one through-silicon via (interposer substrate 500 is seen having conductive structures RDL, which include through-silicon vias) electrically connecting (the interposer substrate 500 is seen having a top and bottom surface which would be electrically coupled by the presence of its vias) a top surface of the interposer substrate (500) to a bottom surface (bottom surface of interposer substrate 500) of the interposer substrate (500); the bottom side (bottom side of semiconductor die 200) of the semiconductor die (200) electrically coupled to (the bottom side of semiconductor die 200 is seen electrically coupled to the top surface of the interposer substrate, which is a connection mediated by conductive contacts SP1) the top surface of the interposer substrate (500); and an array of conductive material (SP2) disposed on (conductive material SP2 is seen arranged in an array at the bottom surface of the interposer substrate 500) the bottom surface of the interposer substrate (500).
It would have been obvious to a person of ordinary skill in the art, absent unexpected results, before the date of effective filing, to substitute the interposer substrate of Cho into the device of Kwon in order to arrive at the expected result of creating a device which has the known benefit of a higher degree of compatibility with other components or circuit components, given the fan-out/redistribution properties of the interposer substrate with reasonable expectation of success.
Regarding Claim 2, Kwon in view of Cho teaches (Cho Fig. 10) the package of claim 1, wherein the semiconductor die (Cho 200) has a width (width of semiconductor die 200 in the horizontal direction), and the interposer substrate (Cho 500) has a width (width of interposer substrate 500 of Cho in the horizontal direction) that is greater than the width (width of the interposer substrate 500 of Cho is seen to be greater than the width of the semiconductor die 200 of Cho) of the at least one semiconductor die (Cho 200).
Regarding Claim 3, Kwon in view of Cho teaches (Kwon Fig. 12) the package of claim 1, further comprising a glass cover (Kwon G) disposed above (glass cover G of Kwon is seen disposed above top side of the optical sensor die 3 of Kwon) the top side of (top side of the optical sensor die 3 of Kwon) the optical sensor die (3).
Regarding Claim 4, Kwon in view of Cho teaches (Kwon Fig. 12) the package of claim 3 further comprising: a non-transparent black coating (Kwon D) disposed on an edge portion of the glass cover (Kwon G) disposed above (black coating D of Kwon is seen above the semiconductor die 1 of Kwon) the top side or the bottom side of the semiconductor die (Kwon 1).
Regarding Claim 5, Kwon in view of Cho teaches (Cho Fig. 10) the package of claim 1, wherein the array of conductive material (Cho SP2) disposed on the bottom surface of the interposer substrate (Cho 500) is a ball grid array of solder (conductive material SP2 of Cho is seen as a ball grid array of solder material).
Regarding Claim 6, Kwon in view of Cho (Kwon Fig. 12) teaches the package of claim 1, wherein the semiconductor die (1) is an application-specific integrated circuit (ASIC) die (the die is application-specific in that it is described as a logic die), the ASIC die including at least one backside through-semiconductor via (BTSV) ([0022], “The logic body 11 may at least partially surround the logic via 13. The logic body 11 may include silicon (Si). For example, the logic body 11 may include a region formed of silicon (Si) in a silicon substrate”) for electrical connections to (the vias 13 are seen connecting to the optical sensor die 3) the optical sensor die (3).
Regarding Claim 24, Kwon teaches (Fig. 12) a package (P) comprising: an interposer substrate (PS); an application specific integrated circuit (ASIC) (2) disposed on the interposer substrate (PS) with a bottom side of the ASIC (bottom side of ASIC 2) being electrically coupled to (conductive elements 55, 53, and 15 are seen electrically connecting the bottom side of ASIC 2 to the top surface of interposer substrate PS) a top surface of the interposer substrate (PS), the ASIC including at least one second through-silicon via (13); an optical sensor die (3) disposed the ASIC (2) with a bottom side of the optical sensor die (3) being electrically coupled to (the vias 13 are in contact with pads 17, and those pads are in contact with pads 37 disposed on optical sensor die 3) the at least one second through-silicon via (13); and an image signal processing (ISP) die (1) disposed on a bottom surface of the interposer substrate.
Kwon is silent with regards to the interposer substrate including at least one first through-silicon via electrically connecting a top surface of the interposer substrate to a bottom surface of the interposer substrate.
Cho teaches (Fig. 10) the interposer substrate (500) including at least one first through-silicon via (interposer substrate 500 is seen having conductive structures RDL, which include through-silicon vias) electrically connecting (the vias in the interposer substrate 500 are seen electrically connecting top and bottom surfaces of the interposer 500) a top surface of (interposer substrate 500, top surface) the interposer substrate (500) to a bottom surface (interposer substrate 500 bottom surface) of the interposer substrate (500).
It would have been obvious to a person of ordinary skill in the art, absent unexpected results, before the date of effective filing, to substitute the interposer substrate of Cho into the device of Kwon in order to arrive at the expected result of creating a device which has the known benefit of a higher degree of compatibility with other components or circuit components, given the fan-out/redistribution properties of the interposer substrate with reasonable expectation of success.
Regarding Claim 25, Kwon in view of Cho teaches (Kwon Fig. 12, Cho Fig. 10) the package of claim 24 further comprising: an array of conductive material (Cho SP2) disposed on a bottom surface of the package (the conductive material array SP2 of Cho is seen arranged on the bottom of the package Cho 1004/Kwon P), the array of conductive material forming external contacts of the package (the conductive material array SP2 of Cho is seen forming external contacts on the package P of Kwon/1004 of Cho); a layer of molding material (Kwon 51), the layer of molding material (Kwon 51) including at least one through-mold via (Kwon 53) for electrical connection between (through mold via 53 of Kwon) the interposer substrate (Kwon PS/ Cho 500) and the array of conductive material (Cho SP2).
Regarding Claim 27, Kwon in view of Cho teaches (Kwon Fig. 12, Cho Fig. 10) the package of claim 24, wherein the ASIC (Cho 200) has a width, and the interposer substrate (Cho 500) has a width that is greater than the width of the at least one semiconductor die (the width of the interposer substrate 500 of Cho is greater than the width of the semiconductor dies of the ASIC 200 of Cho).
Regarding Claim 28, Kwon in view of Cho teaches the package of claim 24 further comprising a glass cover (Kwon G) disposed above a top surface of (glass cover G is disposed above a top surface of the optical sensor die 3) the optical sensor die (3).
Regarding Claim 29, Kwon in view of Cho teaches (Kwon Fig. 12) the package of claim 28 further comprising: a non-transparent black coating (D of Kwon) disposed on an edge portion of (black coating D of Kwon is seen disposed on an edge portion of glass cover G of Kwon) the glass cover (G).
Regarding Claim 30, Kwon in view of Cho teaches the package of claim 28 further comprising a dam (Kwon D) disposed on an edge portion of the top surface of the glass cover (Kwon G), the dam (Kwon D) coupling the glass cover to (the glass cover G of Kwon is seen coupled to the image sensor die 3 of Kwon by the dam D of Kwon) the image sensor die (Kwon 3).
Claim(s) 7-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kwon in view of Cho and further in view of Kim et al (USPGPUB 20180138225, hereinafter “Kim”).
Regarding Claim 7, Kwon teaches a package (P) comprising: an interposer substrate (PS); at least one semiconductor die (2) disposed on (at least one semiconductor die 2 is seen disposed on interposer substrate PS) the interposer substrate (PS) with a bottom side of the at least one semiconductor die (2) being electrically coupled to a top surface of (bottom side of semiconductor dies 2 is seen electrically coupled to a top surface of interposer substrate PS) the interposer substrate (PS); an array of conductive material (55) disposed on (conductive material 55 is seen formed in an array at the bottom surface of the package P) a bottom surface of the package (P), the array of conductive material (55) forming external contacts (the conductive material 55 is seen forming external contacts of the package P) of the package (P); a layer of molding material (51), the layer of molding material (51) including at least one through-mold via (vias 53 are seen formed through the molding material 51); and an image signal processing (ISP) die (3) disposed on a bottom surface (ISP die 3 is seen disposed on bottom surface of interposer substrate PS) of the interposer substrate (PS).
Kwon is silent with regards to the interposer substrate including at least one through-silicon via electrically connecting a top surface of the interposer substrate to a bottom surface of the interposer substrate.
Cho teaches (Fig. 10) the interposer substrate (500) including at least one through substrate through-silicon via (interposer substrate 500 is seen having conductive structures RDL, which include through-silicon vias) electrically connecting a top surface of the interposer substrate to (500) a bottom surface of the interposer substrate (bottom surface of interposer substrate 500).
It would have been obvious to a person of ordinary skill in the art, absent unexpected results, before the date of effective filing, to substitute the interposer substrate of Cho into the device of Kwon in order to arrive at the expected result of creating a device which has the known benefit of a higher degree of compatibility with other components or circuit components, given the fan-out/redistribution properties of the interposer substrate with reasonable expectation of success.
Kwon in view of Cho is silent with regards to the image signal processing (ISP) die embedded in the layer of molding material.
Kim teaches (Fig. 8) the image signal processing (ISP) die (30) embedded in (ISP die 30 is seen embedded in a layer of molding material 302) the layer of molding material (302).
It would have been obvious to a person of ordinary skill in the art, absent unexpected results, before the date of effective filing, to incorporate the molding layout of Kim into the device of Kwon in view of Cho in order to arrive at the expected result of creating a more robust device given the known benefit of supporting the device with more mold material with reasonable expectation of success.
Regarding Claim 8, Kwon in view of Cho and Kim teaches (Kwon Fig. 12, Cho Fig. 10, Kim Fig. 8) the package of claim 7, wherein the image signal processing (ISP) die (1 of Kwon) is flip chip mounted (the ISP die 1 is mounted onto the interposer substrate 500 in a way that is structurally identical to that of a flip-chip mounting process) on the bottom surface of the interposer substrate (500 of Cho).
Regarding Claim 9, Kwon in view of Cho and Kim teaches (Kwon Fig. 12, Cho Fig. 10, Kim Fig. 8) the package of claim 7, wherein the at least one semiconductor die (1 of Kwon; 200 of Cho) has a width, and the interposer substrate (500 of Cho) has a width that is greater than (the interposer 500 of Cho is seen being wider horizontally than the semiconductor 200 of Cho) the width of the at least one semiconductor die (Kwon 1; Cho 200).
Regarding Claim 10, Kwon in view of Cho and Kim teaches (Kwon Fig. 12, Cho Fig. 10, Kim Fig. 8) the package of claim 7, wherein the at least one semiconductor die (Kwon 2) includes an optical sensor die (Kwon 3), and the package further includes a glass cover (Kwon G) disposed above a top side of (Fig. 12 of Kwon, the glass cover G of Kwon is seen disposed above a top side of the at least one semiconductor die, 2 of Kwon) the at least one semiconductor die (Kwon 2).
Regarding Claim 11, Kwon in view of Cho and Kim teaches (Kwon Fig. 12) the package of claim 10 further comprising: a non-transparent black coating (Kwon D) disposed on an edge portion of (black coating D of Kwon is seen on edge portion of glass cover G of Kwon) the glass cover (Kwon G) disposed above (the black coating D of Kwon is seen above the at least one semiconductor die 2 of Kwon) the top side or the bottom side of the at least one semiconductor die (Kwon 2) .
Regarding Claim 12, Kwon in view of Cho and Kim teaches (Cho Fig. 10) the package of claim 7, wherein the array of conductive material (Cho SP2) disposed on the bottom surface of the package is a ball grid array of solder (Cho SP2 is seen to be a ball grid array of solder).
Regarding Claim 13, Kwon in view of Cho and Kim teaches (Kwon Fig. 12, Cho Fig. 10, Kim Fig. 8) the package of claim 7, wherein the at least one semiconductor die (Cho 2) is a stack of an optical sensor die (Cho 3) disposed above (optical sensor die 3 of Cho is seen disposed above ASIC die 1 of Cho) an application-specific integrated circuit (ASIC) die (Cho 1; an integrated circuit logic die is application-specific), the ASIC die including at least one backside through-semiconductor via (BTSV) (Cho 13) for electrical connections to (the via 13 of Cho is seen being electrically connected to the optical sensor die 3 of Cho) the optical sensor die (Cho 3).
Claim(s) 31 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kwon in view of Cho as applied to claim 24 above, and further in view of Liff et al (USPGPUB 20200227377, hereinafter “Liff”).
Regarding Claim 31, Kwon in view of Cho teaches the package of claim 24, but is silent with regards to a device wherein the interposer substrate is a silicon interposer.
Liff teaches a device wherein the interposer substrate is a silicon interposer ([0141], “the interposer 1704 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate”).
It would have been obvious to a person of ordinary skill in the art, absent unexpected results, before the date of effective filing, to incorporate the material of Liff into the device of Kwon in view of Cho in order to arrive at the expected result of taking advantage of silicon’s known properties of low cost and high availability with reasonable expectation of success.
Claim(s) 26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kwon in view of Cho as applied to claim 25 above, and further in view of Kim.
Regarding Claim 26, Kwon in view of Cho teaches the package of claim 25, but is silent with regards to a device wherein the ISP die is embedded in the layer of molding material.
Kim teaches (Fig. 8) a device wherein the ISP die (30) is embedded in the (the layer of molding material 302 is seen surrounding the ISP die 30) layer of molding material (302).
It would have been obvious to a person of ordinary skill in the art, absent unexpected results, before the date of effective filing, to incorporate the molding layout of Kim into the device of Kwon in view of Cho in order to arrive at the expected result of creating a more robust device given the known benefit of supporting the device with more mold material with reasonable expectation of success.
Allowable Subject Matter
Claims 32-33 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding Claim 32, the closest available references, that of Kwon, Cho, Liff, and Kim, alone or in any reasonable combination, fails to teach the limitation, “a redistribution layer disposed on a top surface of the silicon interposer”.
Regarding Claim 33, the closest available references, that of Kwon, Cho, Liff, and Kim, alone or in any reasonable combination, fails to teach the limitation, ”the interposer substrate is a silicon interposer; and wherein the through-silicon via includes a vertical hole extending between a top surface of the silicon interposer and a bottom surface of the silicon interposer with conductive material being disposed in the hole”.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/V.J.L./Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898
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