DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Group II and Species 1 are elected.
Amendment filed May 26, 2026 is acknowledged. Claims 11, 17, 21 and 26 have been amended. Non-Elected Species, claims 14 and 18 have been withdrawn from consideration. Claims 11-30 are pending.
Action on merits of the Elected Group II and Species 1, claims 11-13, 15-17 and 19-30 follows.
Specification
The newly submitted title is not descriptive. The title is
MOS-CAPACITOR FORMED ON A PARTIAL SOI SUBSTRATE
Claim Rejections - 35 USC § 102
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 11-13, 15-17, 19-27 and 29-30 are rejected under 35 U.S.C. 102(a)(1) as being unpatentable over FUKUDA et al. (US. Pub. No. 2013/0210207) of record.
With respect to claim 11, FUKUDA teaches a capacitor device as claimed including:
a semiconductor substrate (11);
a recess (11V) in the semiconductor substrate;
an insulating material (11IF) disposed in the recess;
a semiconductor pillar (11@11V) protruding from the semiconductor substrate (11) and surrounded by the insulating material (11IF);
a single crystalline semiconductor region (11CH-11ES) disposed on the semiconductor substrate (11) to form a bottom plate of the capacitor device;
a capacitor dielectric layer (12) disposed on the bottom plate (11CH-11ES); and
a top plate (13) disposed on the capacitor dielectric layer (12),
wherein the capacitor dielectric layer (12) is in contact with the bottom plate (11CH-11ES) and is disposed between the bottom plate and the top plate (13). (See FIG. 1I).
With respect to claim 12, the recess (11V) of FUKUDA is disposed in a p-well (11PW) in the semiconductor substrate.
With respect to claim 13, the single crystalline semiconductor layer (11CH-11ES) of FUKUDA comprises n-type impurities.
With respect to claim 15, the insulating material (11IF) of FUKUDA comprises silicon oxide.
With respect to claim 16, the capacitor dielectric layer (12) of FUKUDA comprises silicon oxide.
With respect to claim 17, FUKUDA teaches a semiconductor device, as claimed including:
a semiconductor substrate (11);
a recess (11V) in the semiconductor substrate;
a portion of the semiconductor substrate (11) protruding from a bottom of the recess (11V) to form a semiconductor pillar (11 @ 11V); and
a single crystalline semiconductor layer (11CH-11ES) disposed on and attached to a top surface of the semiconductor pillar, wherein the single crystalline semiconductor layer is in contact with the semiconductor substrate (11) through the semiconductor pillar (11 @11V), and is otherwise separated from the semiconductor substrate (11) by the recess (11V). (See FIG. 1E).
With respect to claim 19, the semiconductor device of FUKUDA further comprises an insulating material (11IF) disposed in the recess (11V).
With respect to claim 20, the semiconductor device of FUKUDA further comprises a capacitor dielectric layer (12) disposed on the single crystalline semiconductor layer (11CH-11ES); and a conductive layer (13) disposed on the capacitor dielectric layer (12) to form a capacitor. (FIG. 1I).
With respect to claim 21, FUKUDA teaches a semiconductor structure, as claimed including:
a substrate (11) comprising a well region (W);
an embedded insulating layer (11IF) disposed within the well region (W);
a semiconductor island (11CH-11ES) disposed on the embedded insulating layer (11IF), wherein the semiconductor island is anchored to the well region (W) by a semiconductor pillar (11 @11V) extending through the embedded insulating layer (11IF); and
a capacitor stack disposed on the semiconductor island, the capacitor stack comprising a capacitor dielectric (12) and a top plate (13), wherein the semiconductor island serves as a bottom plate of a capacitor, and the capacitor dielectric laver (12) is in contact with the semiconductor island and is disposed between the semiconductor island and the top plate (13). (See FIG. 1I).
With respect to claim 22, the semiconductor island (11CH-11ES) of FUKUDA comprises a single crystalline silicon layer.
With respect to claim 23, the embedded insulating layer (11IF) of FUKUDA surrounds the semiconductor pillar.
With respect to claim 24, the substrate (11) of FUKUDA is a silicon substrate and the well region (W) of FUKUDA comprises p-type impurities (PW).
With respect to claim 25, the semiconductor island (11CH-11ES) of FUKUDA is doped with n-type impurities to form a conductive bottom plate.
With respect to claim 26, the gate electrode (13) of FUKUDA comprises a metal material or polysilicon.
With respect to claim 27, the embedded insulating layer (11IF) of FUKUDA has a thickness between about 200 Å to about 800 Å, hence within the claimed range of about 100 Angstroms and about 1500 Angstroms.
With respect to claim 29, the semiconductor structure of FUKUDA further comprises isolation structures (11I) surrounding the semiconductor island.
With respect to claim 30, the embedded insulating layer (11IF) of FUKUDA comprises an oxide material filling a cavity (11V) formed under the semiconductor island (11CH-11ES).
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim 28 is rejected under 35 U.S.C. 103 as being unpatentable over FUKUDA ‘207.
FUKUDA teaches the semiconductor structure as described in claim 21 above including: the semiconductor pillar (11CH) has a lateral dimension of about 20 nm to about 80 nm, hence overlapping the claimed range of about 20 nm to about 60 nm.
Note that the specification contains no disclosure of either the critical nature of the claimed dimension of the pillar of any unexpected results arising therefrom. Where patentability is aid to based upon particular chosen dimension or upon another variable recited in a claim, the Applicant must show that the chosen dimension are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
It is well settled that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (Claimed process which was performed at a temperature between 40 ºC and 80 ºC and an acid concentration between 25% and 70% was held to be prima facie obvious over a reference process which differed from the claims only in that the reference process was performed at a temperature of 100 ºC and an acid concentration of 10%.); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382 ("The normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages.").
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the pillar of FUKUDA having the lateral dimension as claimed to prevent floating body effect.
Response to Arguments
Applicant's arguments filed May 26, 2026 have been fully considered but they are not persuasive.
Regarding independent claims 11 and 21, Applicant argues: as clearly shown in Fukuda's FIG. 11, the gate insulation film 12 and the gate electrode pattern 13G (which the Examiner identifies as the capacitor dielectric layer and top plate) are formed directly on top of the substrate portion 11 CH (which the Examiner identifies as the semiconductor pillar). They are not disposed on the epitaxial layer 11ES.
However, as indicated, the bottom plate of the capacitor of FUKUDA is not just 11CH portion but portion 11ES as well because the limitation: “a semiconductor pillar protruding from the semiconductor substrate and surrounded by the insulating material; and a single crystalline semiconductor region disposed on the semiconductor substrate to form a bottom plate of the capacitor device”.
Therefore, the capacitor dielectric 12, which is disposed on portion 11CH, is disposed on the bottom plate, hence “the capacitor dielectric layer is in contact with the bottom plate and is disposed between the bottom plate and the top plate”.
The limitations are met. The rejection is maintained.
Regarding claim 17, Applicant argues: Because Fukuda's epitaxial layer 11ES is located beside the substrate portion 11CH rather than on the top surface of the substrate portion 11 CH, Fukuda physically lacks the specific arrangement recited in the claim.
However, as clearly shown in FIG. 1I, portion 11ES is an extension of portion 11CH, epitaxially grown silicon, thus the “single crystalline semiconductor layer” comprises portions 11CH and 11ES.
Therefore, the limitations: a single crystalline semiconductor layer disposed on and attached to a top surface of the semiconductor pillar, wherein the single crystalline semiconductor layer is in contact with the semiconductor substrate through the semiconductor pillar, and is otherwise separated from the semiconductor substrate by the recess are met.
The limitations are met. The rejection is maintained.
Regarding the dependent claims, since dependent claims 12-13, 15-16, 19-20 and 22-30 depend on the rejected independent claims 11, 17 and 21, the rejections of these claims are maintained.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANH D MAI whose telephone number is (571)272-1710 (Email: Anh.Mai2@uspto.gov). The examiner can normally be reached 10:00-4:00PM.
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/ANH D MAI/Primary Examiner, Art Unit 2893
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