DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Applicant’s election without traverse of Group II and Species 1, in the reply filed on November 25, 2025 is acknowledged.
New claims 21-30 have been added. Claims 1-10 have been cancelled. Applicant identified claims 11-13, 15-17 and 19-30 are readable on the Elected Group II and Species 1.
Non-Elected Species, claims 14 and 18 have been withdrawn from consideration. Claims 11-30 are pending.
Action on merits of the Elected Group II and Species 1, claims 11-13, 15-17 and 19-30 follows.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on February 19, 2024 has been considered by the examiner.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested:
A MOSFET OR MOS-CAPACITOR FORMED ON A PARTIAL SOI STRUCTURE
Claim Objections
Claim 11 is objected to because of the following informalities:
Amendment filed November 25, 2025 identified claim 11 as “(Original)”.
However, Claim 11 has been amended in the Preliminary Amendment filed January 13, 2023.
Therefore, the correct identifier for claim 11 should be “(Previously Present)”
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 21-30 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
New claim 21 recites: “a gate stack disposed on the semiconductor island, the gate stack comprising a gate dielectric and a gate electrode, wherein the semiconductor island serves as a bottom plate of a capacitor”.
Two terms are contradictory.
If the upper portion is “a gate stack” then the “semiconductor island” is an active region of a field effect transistor, where the channel is formed.
If the “semiconductor island serves as a bottom plate of a capacitor” then the stack structure is an upper electrode of a MOS capacitor, not a gate stack.
Therefore, claims 21-30 are indefinite.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 11-13, 15-17, 19-27 and 29-30 are rejected under 35 U.S.C. 103 as being unpatentable over FUKUDA et al. (US. Pub. No. 2013/0210207).
With respect to claim 11, FUKUDA teaches a capacitor device as claimed including:
a semiconductor substrate;
a recess (11V) in the semiconductor substrate;
an insulating material (11IF) disposed in the recess;
a semiconductor pillar (11CH) protruding from the semiconductor substrate and surrounded by the insulating material (11IF);
a single crystalline semiconductor region (11ES) disposed on the semiconductor substrate to form a bottom plate of the capacitor device;
a capacitor dielectric layer (12) disposed on the bottom plate (11ES); and
a top plate (13G) disposed on the capacitor dielectric layer. (See FIG. 1I).
With respect to claim 12, the recess (11V) of FUKUDA is disposed in a p-well (11PW) in the semiconductor substrate.
With respect to claim 13, the single crystalline semiconductor layer (11ES) of FUKUDA comprises n-type impurities.
With respect to claim 15, the insulating material (11IF) of FUKUDA comprises silicon oxide.
With respect to claim 16, the capacitor dielectric layer (12) of FUKUDA comprises silicon oxide.
With respect to claim 17, FUKUDA teaches a semiconductor device, as claimed including:
a semiconductor substrate;
a recess (11V) in the semiconductor substrate;
a portion of the semiconductor substrate protruding from a bottom of the recess (11V) to form a semiconductor pillar (11CH); and
a single crystalline semiconductor layer (11ES) disposed on the semiconductor pillar, wherein the single crystalline semiconductor layer (11ES) is in direct contact with the semiconductor substrate through the semiconductor pillar (11CH), and is otherwise separated from the semiconductor substrate by the recess (11V). (See FIG. 1E).
With respect to claim 19, the semiconductor device of FUKUDA further comprises an insulating material (11IF) disposed in the recess.
With respect to claim 20, the semiconductor device of FUKUDA further comprises a capacitor dielectric layer (12) disposed on the single crystalline semiconductor layer (11ES); and a conductive layer (13) disposed on the capacitor dielectric layer (12) to form a capacitor. (FIG. 1I).
With respect to claim 21, As best understood by the Examiner, FUKUDA teaches a semiconductor structure, as claimed including:
a substrate comprising a well region (W);
an embedded insulating layer (11IF) disposed within the well region;
a semiconductor island (11ES) disposed on the embedded insulating layer, wherein the semiconductor island is anchored to the well region by a semiconductor pillar (11CH) extending through the embedded insulating layer (11IF); and
a gate stack disposed on the semiconductor island, the gate stack comprising a gate dielectric (12) and a gate electrode (13), wherein the semiconductor island (11ES) serves as a bottom plate of a capacitor. (See FIG. 1I).
With respect to claim 22, the semiconductor island (11ES) of FUKUDA comprises a single crystalline silicon layer.
With respect to claim 23, the embedded insulating layer (11IF) of FUKUDA surrounds the semiconductor pillar (11CH).
With respect to claim 24, the substrate is a silicon substrate and the well region (W) of FUKUDA comprises p-type impurities (PW).
With respect to claim 25, the semiconductor island of FUKUDA is doped with n-type impurities to form a conductive bottom plate.
With respect to claim 26, the gate electrode (13) of FUKUDA comprises a metal material or polysilicon.
With respect to claim 27, the embedded insulating layer (11IF) of FUKUDA has a thickness between about 200 Å to about 800 Å, hence within the claimed range of about 100 Angstroms and about 1500 Angstroms.
With respect to claim 29, the semiconductor structure of BARTH further comprises isolation structures surrounding the semiconductor island (16).
With respect to claim 30, the embedded insulating layer (14) of BARTH comprises an oxide material filling a cavity formed under the semiconductor island (16).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 28 is rejected under 35 U.S.C. 103 as being unpatentable over FUKUDA ‘207.
FUKUDA teaches the semiconductor structure as described in claim 21 above including: the semiconductor pillar (11CH) has a lateral dimension of about 20 nm to about 80 nm, hence overlapping the claimed range of about 20 nm to about 60 nm.
Note that the specification contains no disclosure of either the critical nature of the claimed dimension of the pillar of any unexpected results arising therefrom. Where patentability is aid to based upon particular chosen dimension or upon another variable recited in a claim, the Applicant must show that the chosen dimension are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
It is well settled that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (Claimed process which was performed at a temperature between 40 ºC and 80 ºC and an acid concentration between 25% and 70% was held to be prima facie obvious over a reference process which differed from the claims only in that the reference process was performed at a temperature of 100 ºC and an acid concentration of 10%.); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382 ("The normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages.").
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the pillar of FUKUDA having the lateral dimension as claimed to prevent floating body effect.
Conclusion
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/ANH D MAI/Primary Examiner, Art Unit 2893