DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Remarks
The 06/23/2026 amendments of claims 19, 22-23, 29-30, and 35 have been noted and entered.
The 06/23/2026 addition of new claim 42 has been noted and entered.
The 06/23/2026 cancellation of claim 32 has been noted and entered.
Response to Arguments
Applicant’s arguments, see Arguments pages 10-15, filed 06/23/2026, with respect to the rejection of claims 19, 21, 23-30, 32-35 and 37-41 under 35 U.S.C. 103 have been fully considered and are persuasive in light of the newly added amendments. The rejections of record have been withdrawn.
Applicant’s arguments, see Arguments pages 15-17, filed 06/23/2026, with respect to the rejection(s) of claim(s) 22 under 35 U.S.C. 103 have been fully considered and are persuasive in light of the newly added amendments. However, upon further consideration, a new ground(s) of rejection is made in view of Chung et al, US 20210328020 A1 (Chung), Varadarajan et al, (WO 2021067118 A1) (Varadarajan) and Lee et al, KR 101580243 B1 (Lee).
New Grounds of Rejection
New grounds of rejection, prior art reference Chung et al, US 20210328020 A1 (Chung), Varadarajan et al, (WO 2021067118 A1) (Varadarajan) and Lee et al, KR 101580243 B1 (Lee) appears below.
Claims 22, 33-34, and 39 are rejected under 35 U.S.C. 103 as being unpatentable over Chung et al, US 20210328020 A1 (Chung) in further view Varadarajan et al, WO 2021067118 A1 (Varadarajan) in further view of Lee et al, KR 101580243 B1 (Lee).
Regarding claim 22; Chung teaches a method of forming a semiconductor device (Chung: Annotated Fig (11A) shared in this OA: 200) comprising:
forming a semiconductor structure that includes a substrate (202),
a channel portion (210C) disposed over the substrate (Substrate),
two epitaxial structures (232) disposed over the substrate (Substrate) such that the channel portion (210C) is connected between the two epitaxial structures (232),
a gate structure (250 and the layers surrounding it) disposed on the channel portion (202), and
two dielectric portions (238) respectively disposed on the two epitaxial structures (232); and
forming a recess (recess that contains 242) in the semiconductor structure (200), the recess (recess that contains 242) being spaced apart from the channel portion (210C);
forming a via (242) in the recess (recess that contains 242);
forming a barrier layer (236) between the via (242) and the semiconductor structure (200), the barrier layer (236) including a graphene-based material; and
forming a conductive structure on the via,
wherein an intercalant is introduced during formation of the barrier layer so that the barrier layer includes intercalated graphene which includes elements in the intercalant, the intercalant including Mo, W, Au, Ru, Co, metal oxide, or combinations thereof.
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Chung does not teach the barrier layer including a graphene-based material; and
forming a conductive structure on the via.
However, Varadarajan teaches including a graphene-based material (Varadarajan: Fig (1B): 122); and forming a conductive structure (150) on the via (120).
Chung and Varadarajan are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Chung by constructing the barrier layer out of graphene as disclosed in Varadarajan to improve the protection of the different device components against metal atom diffusion and oxidation leading to a more reliable device.
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Chung in view of Varadarajan does not teach wherein an intercalant is introduced during formation of the barrier layer so that the barrier layer includes intercalated graphene which includes elements in the intercalant, the intercalant including Mo, W, Au, Ru, Co, metal oxide, or combinations thereof.
Lee teaches wherein an intercalant includes intercalated graphene which includes elements in the intercalant, the intercalant including metal oxide (Lee: Page: 3 Lines: 5-7 of the translation of Lee attached to this OA: “That is, the composite laminate according to the present invention includes a metal oxide intercalated and chemically bonded between the oxidized graphene laminate and the oxidized graphene layer of the graphene oxide laminate.”).
Chung in view of Varadarajan and Lee are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Chung in view of Varadarajan by using an intercalant that includes a metal oxide as disclosed in Lee to improve the conductivity of the formed graphene layer leading to better conductivity in the device and better performance of it.
Regarding claim 33; Chung in view of Varadarajan in further view of Lee teaches all the limitations of the method of claim 22.
Chung teaches wherein the recess (Chung: Annotated Fig (11A) shared in this OA: recess that contains 242) extends through the substrate (Substrate) such that one of the two epitaxial structures (232) is exposed from the recess (recess that contains 242), and the barrier layer (236) is disposed between the via (242) and the one of the two epitaxial structures (232).
Regarding claim 34; Chung in view of Varadarajan in further view of Lee teaches all the limitations of the method of claim 22.
Chung teaches wherein the gate structure (Chung: Annotated Fig (11A) shared in this OA: 250 and the layers surrounding it) includes a gate electrode (250) and a gate dielectric (254) disposed between the gate electrode (250) and the channel portion ([0038]: “In various embodiments, the gate structure 250 includes an interfacial layer 252, a high-K gate dielectric layer 254 formed over the interfacial layer 252,....”).
Regarding claim 39; Chung in view of Varadarajan in further view of Lee teaches all the limitations of the method of claim 22.
Chung teaches wherein the substrate (Chung: Fig (11A): Substrate) has a front side and a back side opposite to the front surface (Front and Back Side of the Substrate), the channel portion and the two epitaxial structures (232) are disposed on the front side of the substrate (Front Side of the Substrate), and the recess (the recess filled by (242)) is recessed from the back side (Back Side of the Substrate) of the substrate (Substrate).
Allowable Subject Matter
Claims 19, 21, 35, 37-38 and 40-41 are allowable over prior art.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 19; Guler in view of Tien in further view Xie in further view of McNerny in further view of Yang teaches a method of forming a semiconductor device comprising: forming a semiconductor structure that includes a substrate, a channel portion disposed over the substrate, and two epitaxial structures disposed over the substrate such that the channel portion is connected between the two epitaxial structures; flipping the semiconductor structure upside down so that the substrate faces upward; forming a recess in the substrate to expose a surface of one of the two epitaxial structures; forming a silicide feature on the surface of the one of the two epitaxial structures; forming a via in the recess; forming a graphene barrier that surrounds the via and that is connected between the via and the silicide feature; and forming a conductive structure that is disposed on the substrate and that is connected to the via, wherein formation of the via and the graphene barrier includes forming a filling conductive layer on the substrate and in the recess, the filling conductive layer having a first surface which is opposite to the substrate and a second surface which is opposite to the first surface, after forming the filling conductive layer.
However, Guler alone or in combination with other available art does not teach forming a carbon-containing material on the first surface of the filling conductive layer, forcing carbon atoms of the carbon-containing material to diffuse from the first surface of the filling conductive layer through the filling conductive layer to the second surface of the filling conductive layer, so as to form the graphene barrier on the second surface of the filling conductive layer, and after forming the graphene barrier, removing a first part of the filling conductive layer and leaving a second part of the filling conductive layer in the recess, the second part of the filling conductive layer serving as the via in a manner that can be combined with the above limitations reasonably.
Claim 21 is allowable for its dependence on an allowable claim.
Regarding claim 35; Guler in view of Tien in further view of Bao in further view of McNerny teaches a method of forming a semiconductor device comprising: forming a semiconductor structure that includes a substrate, two channel portions disposed over the substrate, two epitaxial structures disposed over the substrate, the two epitaxial structures being respectively connected to the two channel portions, a gate structure disposed on the two channel portions, a dielectric portion which is disposed adjacent to the gate structure and which is disposed on the two epitaxial structures; forming a recess in the semiconductor structure, the recess being spaced apart from the two channel portions; forming a via in the recess; forming a barrier layer between the via and the semiconductor structure, the barrier layer including a graphene-based material; and forming a conductive structure on the via, wherein formation of the via and the barrier layer includes forming a filling conductive layer on the semiconductor structure to fill the recess, the filling conductive layer having a first surface which faces away from the semiconductor structure and a second surface which faces the semiconductor structure.
However, Guler alone or in combination with other available art does not teach forming a carbon-containing material on the first surface of the filling conductive layer, the carbon-containing material not being formed on the second surface of the filling conductive layer, performing a drive-in treatment such that carbon atoms of the carbon-containing material are forced to diffuse from the first surface of the filling conductive layer through the filling conductive layer to the second surface of the filling conductive layer, so as to form the barrier layer which is disposed on the second surface of the filling conductive layer and which is located between the filling conductive layer and the semiconductor structure, after the drive-in treatment, removing a remaining portion of the carbon-containing material on the first surface of the filling conductive layer, the filling conductive layer being left after removing the remaining portion of the carbon-containing material, and removing a first part of the filling conductive layer and leaving a second part of the filling conductive layer in the recess, the second part of the filling conductive layer serving as the via in a manner that can be combined with the above limitations reasonably.
Claims 37-38 and 40-41 are allowable for their dependence on an allowable claim.
Claims 23-30 and 42 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 23; Chung in view of Varadarajan in further view of Lee teaches the method as claimed in claim 22, wherein formation of the via and the barrier layer includes: forming a filling conductive layer on the semiconductor structure to fill the recess.
However, Chung alone or in combination with other available art does not teach forming a carbon-containing material on the filling conductive layer; performing a drive-in treatment such that carbon atoms of the carbon-containing material are forced to diffuse through the filling conductive layer so as to form the barrier layer which is disposed between the filling conductive layer and the semiconductor structure; and after the drive-in treatment, removing a first part of the filling conductive layer and leaving a second part of the filling conductive layer in the recess, the second part of the filling conductive layer serving as the via in a manner that can be combined with the above limitations reasonably.
Claims 24-30 and 42 are objected to for their dependence on an objected to claim.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/M.K./Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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