DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed on May 6th 2026 has been entered. Claims 1, 3-9, 11-15, 23, 25 and 27-31 remain pending in the application.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 3-5, 8-9, 11-15, 23, 25, 27 and 30-31 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 20170317027), hereinafter Chen.
Regarding claim 1, Chen teaches a semiconductor device (Abstract), comprising:
a first source/drain structure (Annotated fig. 7C, left source/drain regions 704 labeled as 1st S/D; para. 0046) and a second source/drain structure (middle 704 labeled as 2nd S/D) of a first transistor (left transistor with gate structures 706 labeled as 1st gate; para. 0047);
a third source/drain structure (middle 704 labeled as 3rd S/D) and a fourth source/drain structure (right 704 labeled as 4th S/D) of a second transistor (right transistor with 706 labeled as 2nd gate), wherein the second source/drain structure (2nd S/D) and the third source/drain structure (3rd S/D) merge as a common source/drain structure (middle 704 labeled as 2nd/3rd S/D);
a first interconnect structure (first metal wire 110a; para. 0048) extending along a first lateral direction (horizontal) and disposed directly above the common source/drain structure (110a disposed above 2nd/3rd S/D).
Chen fails to explicitly teach a first dielectric structure disposed directly above and fully overlaying the common source/drain structure; and
the first interconnect structure along at least one side of the first dielectric structure, wherein the first dielectric structure interposes between and electrically isolates the common source/drain structure and the first interconnect structure.
However, Chen teaches a first dielectric structure (Annotated fig. 4C based on fig. 7C structure, ILD layers 302a, 302b, etch stop layers 304a, 304b in the middle; para. 0031) disposed directly above and fully overlaying the common source/drain structure (middle source/drain regions 408; para. 0038, similar to 704 of fig. 7C); and
the first interconnect structure (110, similar to 110a of fig. 7C) along at least one side of the first dielectric structure (top side of 304b), wherein the first dielectric structure (302a, 302b, 304a, 304b in the middle) interposes between and electrically isolates the common source/drain structure (middle 408) and the first interconnect structure (110).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to add the first dielectric structure.
Doing so would realize a dielectric structure essential to isolate the conductive elements in the device to avoid electrical shorts. Furthermore, it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8. (MPEP § 2144.04 VI. B.).
PNG
media_image1.png
447
757
media_image1.png
Greyscale
(Annotated fig. 7C)
PNG
media_image2.png
165
377
media_image2.png
Greyscale
(Annotated fig. 4C)
Regarding claim 3, Chen further teaches the semiconductor device of claim 1, wherein the first interconnect structure (fig. 3, in an alternative consideration, middle wire between 110a and 116, and at same layer of 110 as the first interconnect structure) is configured at a floating voltage (middle wire is not connected to an external voltage source or ground, and therefore meets BRI as capable of being operated with a floating voltage).
Regarding claim 4, Chen further teaches the semiconductor device of claim 1, further comprising:
a second interconnect structure (fig. 7C, metal strap 114; para. 0034) extending along a second lateral direction (lateral direction perpendicular to horizontal 110a direction) perpendicular to the first lateral direction (horizontal 110a direction); and
a via structure (first conductive via 112a; para. 0034) electrically connecting the first interconnect structure (110a) to the second interconnect structure (114).
Regarding claim 5, Chen further teaches the semiconductor device of claim 4, wherein the second interconnect structure (fig. 7C, 114) is configured at a power supply voltage or a fixed voltage (114 connect power rail 116 with supply voltage or ground voltage; para. 0020).
Regarding claim 8, Chen further teaches the semiconductor device of claim 1, further comprising:
a third interconnect structure (Annotated fig. 7C, left 110a above 1st S/D) extending along the first lateral direction (horizontal) and disposed above the first source/drain structure (110a disposed above 1st S/D); and
a fourth interconnect structure (right 110a above 4th S/D) extending along the first lateral direction (horizontal), and disposed above the fourth source/drain structure (110a disposed above 4th S/D).
Regarding claim 9, Chen further teaches the semiconductor device of claim 8, wherein the third interconnect structure (Annotated fig. 7C, left 101a) is electrically connected to the first source/drain structure (101a is electrically connected to 1st S/D) and the fourth interconnect structure (right 101a) is electrically connected to the fourth source/drain structure (101a is electrically connected to 4th S/D); wherein each of the third interconnect structure and fourth interconnect structure (101a) is electrically coupled to a fifth interconnect structure (101a is electrically connected to 116) that is configured as an output node or a power rail (power rail 116); and wherein the fifth interconnect structure (116) is formed on a front side (top side) of a substrate (semiconductor substrate 102; para. 0019) where the first and second transistors (left and right transistors of 706) are formed.
Regarding claim 11, Chen teaches a semiconductor device (Abstract), comprising:
an active region (Annotated fig. 7C, active area 104; para. 0019) formed on a front side of a substrate (top side of semiconductor substrate 102; para. 0019) and extending along a first lateral direction (first direction 710; para. 0046);
a first gate structure (left transistor with gate structures 706 labeled as 1st gate; para. 0047) extending along a second lateral direction (second direction 712; para. 0047) and traversing across the active region (104);
a second gate structure (right transistor with 706 labeled as 2nd gate) extending along the second lateral direction (712) and traversing across the active region (104);
a first portion of the active region (104 under middle source/drain regions 704 labeled as 1st S/D; para. 0046) laterally interposed between the first and second gate structures (1st gate and 2nd gate);
a first interconnect structure (power rail 116 portion on middle 704; para. 0020) extending along the second lateral direction (712) and disposed (i} between the first gate structure and the second gate structure (1st gate and 2nd gate).
Chen fails to explicitly teach a first dielectric structure disposed directly above and fully overlaying the first portion of the active region; and
the first interconnect structure directly above and along at least one side of the first dielectric structure, wherein the first dielectric structure is vertically interposed between and in contact with the first interconnect structure and the first portion of the active region to electrically isolate the first interconnect structure from the first portion of the active region.
However, Chen teaches a first dielectric structure (Annotated fig. 4C based on fig. 7C structure, ILD layers 302a, 302b, etch stop layers 304a, 304b in the middle; para. 0031) disposed directly above and fully overlaying the first portion of the active region (middle source/drain regions 408; para. 0038, similar to 704 of fig. 7C); and
the first interconnect structure (metal wire 110, similar to at same layer of 116 of fig. 7C) directly above and along at least one side (top side of 304b) of the first dielectric structure (302a, 302b, 304a, 304b in the middle), wherein the first dielectric structure (302a, 302b, 304a, 304b in the middle) is vertically interposed between and in contact with the first interconnect structure (110) and the first portion of the active region (middle 408) to electrically isolate the first interconnect structure (110) from the first portion of the active region (middle 408).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to add the first dielectric structure.
Doing so would realize a dielectric structure essential to isolate the conductive elements in the device to avoid electrical shorts. Furthermore, it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8. (MPEP § 2144.04 VI. B.).
Regarding claim 12, Chen further teaches the semiconductor device of claim 11, further comprising:
a second interconnect structure (Annotated fig. 7C, left metal strap 114; para. 0034) extending along the second lateral direction (712) and disposed above a second portion (left source/drain regions 704 labeled as 1st S/D; para. 0046) of the active region (104) on the front side, wherein the second portion of the active region (1st S/D) is disposed opposite the first gate structure (1st gate) from the first portion of the active region (middle 704 of 2nd/3rd S/D) along the first lateral direction (710); and
a third interconnect structure (right 114) extending along the second lateral direction (712) and disposed above a third portion (right 704 of 4th S/D) of the active region (104) on the front side, wherein the third portion of the active region (4th S/D) is disposed opposite the second gate structure (2nd gate) from the first portion of the active region (middle 704 of 2nd/3rd S/D) along the first lateral direction (710).
Regarding claim 13, Chen further teaches the semiconductor device of claim 12, wherein the second interconnect structure (Annotated fig. 7C, left 114) is in electrical contact with the second portion of the active region (1st S/D), and the third interconnect structure (right 114) is in electrical contact with the third portion of the active region (4th S/D).
Regarding claim 14, Chen further teaches the semiconductor device of claim 13, wherein each of the second interconnect structure and the third interconnect structure (fig. 7C and fig. 6C, 114) is electrically coupled to a respective fourth interconnect structure (second power rail 604; para. 0044) formed on the front side (top side).
Regarding claim 15, Chen further teaches the semiconductor device of claim 14, wherein the fourth interconnect structure (fig. 6C, 604) is configured as an output node or a power rail (power rail; para. 0044).
Regarding claim 23, Chen teaches a method (Abstract), comprising:
forming a first source/drain structure (Annotated fig. 7C, left source/drain regions 704 labeled as 1st S/D; para. 0046) and a second source/drain structure (middle 704 labeled as 2nd S/D) of a first transistor (left transistor with gate structures 706 labeled as 1st gate; para. 0047);
forming a third source/drain structure (middle 704 labeled as 3rd S/D) and a fourth source/drain structure (right 704 labeled as 4th S/D) of a second transistor (right transistor with 706 labeled as 2nd gate), wherein the second source/drain structure (2nd S/D) and the third source/drain structure (3rd S/D) merge as a common source/drain structure (middle 704 labeled as 2nd/3rd S/D);
forming a first interconnect structure (first metal wire 110a; para. 0048) extending along a first lateral direction (horizontal) and disposed directly above the common source/drain structure (110a disposed above 2nd/3rd S/D).
Chen fails to explicitly teach forming a first dielectric structure disposed directly above and fully overlaying the common source/drain structure; and
the first interconnect structure along at least one side of the first dielectric structure, wherein the first dielectric structure interposes between and electrically isolates the common source/drain structure from the first interconnect structure.
However, Chen teaches forming a first dielectric structure (Annotated fig. 4C based on fig. 7C structure, ILD layers 302a, 302b, etch stop layers 304a, 304b in the middle; para. 0031) disposed directly above and fully overlaying the common source/drain structure (middle source/drain regions 408; para. 0038, similar to 704 of fig. 7C); and
the first interconnect structure (110, similar to 110a of fig. 7C) along at least one side of the first dielectric structure (top side of 304b), wherein the first dielectric structure (302a, 302b, 304a, 304b in the middle) interposes between and electrically isolates the common source/drain structure (middle 408) and the first interconnect structure (110).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to add the first dielectric structure.
Doing so would realize a dielectric structure essential to isolate the conductive elements in the device to avoid electrical shorts. Furthermore, it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8. (MPEP § 2144.04 VI. B.).
Regarding claim 25, Chen further teaches the method of claim 23, further comprising:
forming a second interconnect structure (fig. 7C, metal strap 114; para. 0034) extending along a second lateral direction (lateral direction perpendicular to horizontal 110a direction) perpendicular to the first lateral direction (horizontal 110a direction);
forming a via structure (first conductive via 112a; para. 0034) electrically connecting the first interconnect structure (110a) to the second interconnect structure (114).
Regarding claim 27, Chen further teaches the method of claim 25, wherein the second interconnect structure (fig. 7C, 114) is configured at a power supply voltage or a fixed voltage (114 connect power rail 116 with supply voltage or ground voltage; para. 0020).
Regarding claim 30, Chen further teaches the method of claim 23, further comprising:
forming a third interconnect structure (Annotated fig. 7C, left 110a above 1st S/D) extending along the first lateral direction (horizontal) and disposed above the first source/drain structure (110a disposed above 1st S/D); and
forming a fourth interconnect structure (right 110a above 4th S/D) extending along the first lateral direction (horizontal), and disposed above the fourth source/drain structure (110a disposed above 4th S/D).
Regarding claim 31, Chen further teaches the method of claim 30, wherein the third interconnect structure (Annotated fig. 7C, left 101a) is electrically connected to the first source/drain structure (101a is electrically connected to 1st S/D) and the fourth interconnect structure (right 101a) is electrically connected to the fourth source/drain structure (101a is electrically connected to 4th S/D); wherein each of the third interconnect structure and the fourth interconnect structure (101a) is electrically coupled to a fifth interconnect structure (101a is electrically connected to 116) that is configured as an output node or a power rail (power rail 116); and wherein the fifth interconnect structure (116) is formed on a front side (top side) of a substrate (semiconductor substrate 102; para. 0019) where the first and second transistors (left and right transistors of 706) are formed.
Claims 1 and 6-7, 23 and 28-29 are rejected under 35 U.S.C. 103 as being unpatentable over Farbiz et al. (US 20190073440) in view of Chen.
Regarding claim 1, Farbiz teaches a semiconductor device (Abstract), comprising:
a first source/drain structure (fig. 1, n-type regions 170; para. 0031) and a second source/drain structure (n-type regions 172; para. 0031) of a first transistor (transistor with transistor gate stripes 160; para. 0031);
a third source/drain structure (172) and a fourth source/drain structure (n-type regions 174; para. 0031) of a second transistor (transistor with transistor gate stripes 162; para. 0031), wherein the second source/drain structure (172) and the third source/drain structure (172) merge as a common source/drain structure (172 is the common source/drain for both gate transistors);
a first interconnect structure (Annotated fig. 1, 1st. portion with red label) extending along a first lateral direction (horizontal) and disposed directly above the common source/drain structure (1st. portion disposed above 172).
Farbiz fails to explicitly teach a first dielectric structure disposed directly above and fully overlaying the common source/drain structure; and
the first interconnect structure along at least one side of the first dielectric structure, wherein the first dielectric structure interposes between and electrically isolates the common source/drain structure and the first interconnect structure.
However, Chen teaches a first dielectric structure (Chen: Annotated fig. 4C, ILD layers 302a, 302b, etch stop layers 304a, 304b in the middle; para. 0031) disposed directly above and fully overlaying the common source/drain structure (Chen: middle source/drain regions 408; para. 0038, similar to 172 of Farbiz); and
the first interconnect structure (Chen: metal wire 110 as interconnect over middle 408; para. 0025, similar to 1st. portion of Farbiz) along at least one side of the first dielectric structure (Chen: top side of 304b), wherein the first dielectric structure (Chen: 302a, 302b, 304a, 304b in the middle) interposes between and electrically isolates the common source/drain structure (Chen: middle 408) and the first interconnect structure (Chen: 110).
Chen and Farbiz are considered to be analogous to the claimed invention because they are in the same field of interconnection structures of transistor devices.
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to add the first dielectric structure as taught by Chen.
Doing so would realize a dielectric structure essential to isolate the conductive elements in the device to avoid electrical shorts. Furthermore, it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8. (MPEP § 2144.04 VI. B.).
PNG
media_image3.png
320
394
media_image3.png
Greyscale
(Annotated fig. 1)
Regarding claim 6, Farbiz in view of Chen further teaches the semiconductor device of claim 1, further comprising:
a first gate structure (Farbiz: fig. 1, 160) of the first transistor (Farbiz: transistor with 160) that extends along the first lateral direction (Farbiz: 160 extends along horizontal), wherein the first source/drain structure (Farbiz: 170) and second source/drain structure (Farbiz: 172) are disposed on opposite sides of the first gate structure (Farbiz: 170, 172 on opposite sides of 160), respectively; and
a second gate structure (Farbiz: 162) of the second transistor (Farbiz: transistor with 162) that extends along the first lateral direction (Farbiz: 162 extends along horizontal), wherein the third source/drain structure (Farbiz: 172) and fourth source/drain structure (Farbiz: 174) are disposed on opposite sides of the second gate structure (Farbiz: 172, 174 on opposite sides of 162), respectively.
Regarding claim 7, Farbiz in view of Chen further teaches the semiconductor device of claim 6, wherein the first interconnect structure (Farbiz: Annotated fig. 1, 1st. portion) is configured at a first voltage (Farbiz: voltage of ground reference VSS; para. 0035) identical to a second voltage (Farbiz: voltage of VSS) provided to either the first gate structure (Farbiz: VSS provided to 160) or the second gate structure (Farbiz: VSS provided to 162).
Regarding claim 23, Farbiz teaches a method (Abstract), comprising:
forming a first source/drain structure (fig. 1, n-type regions 170; para. 0031) and a second source/drain structure (n-type regions 172; para. 0031) of a first transistor (transistor with transistor gate stripes 160; para. 0031);
forming a third source/drain structure (172) and a fourth source/drain structure (n-type regions 174; para. 0031) of a second transistor (transistor with transistor gate stripes 162; para. 0031), wherein the second source/drain structure (172) and the third source/drain structure (172) merge as a common source/drain structure (172 is the common source/drain for both gate transistors);
forming a first interconnect structure (Annotated fig. 1, 1st. portion with red label) extending along a first lateral direction (horizontal) and disposed directly above the common source/drain structure (1st. portion disposed above 172).
Farbiz fails to explicitly teach forming a first dielectric structure disposed directly above and fully overlaying the common source/drain structure; and
the first interconnect structure along at least one side of the first dielectric structure, wherein the first dielectric structure interposes between and electrically isolates the common source/drain structure and the first interconnect structure.
However, Chen teaches forming a first dielectric structure (Chen: Annotated fig. 4C, ILD layers 302a, 302b, etch stop layers 304a, 304b in the middle; para. 0031) disposed directly above and fully overlaying the common source/drain structure (Chen: middle source/drain regions 408; para. 0038, similar to 172 of Farbiz); and
the first interconnect structure (Chen: metal wire 110 as interconnect over middle 408; para. 0025, similar to 1st. portion of Farbiz) along at least one side of the first dielectric structure (Chen: top side of 304b), wherein the first dielectric structure (Chen: 302a, 302b, 304a, 304b in the middle) interposes between and electrically isolates the common source/drain structure (Chen: middle 408) and the first interconnect structure (Chen: 110).
Chen and Farbiz are considered to be analogous to the claimed invention because they are in the same field of interconnection structures of transistor devices.
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to add the first dielectric structure as taught by Chen.
Doing so would realize a dielectric structure essential to isolate the conductive elements in the device to avoid electrical shorts. Furthermore, it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8. (MPEP § 2144.04 VI. B.).
Regarding claim 28, Farbiz in view of Chen further teaches the method of claim 23, further comprising:
forming a first gate structure (Farbiz: fig. 1, 160) of the first transistor (Farbiz: transistor with 160) that extends along the first lateral direction (Farbiz: 160 extends along horizontal), wherein the first source/drain structure (Farbiz: 170) and second source/drain structure (Farbiz: 172) are disposed on opposite sides of the first gate structure (Farbiz: 170, 172 on opposite sides of 160), respectively; and
forming a second gate structure (Farbiz: 162) of the second transistor (Farbiz: transistor with 162) that extends along the first lateral direction (Farbiz: 162 extends along horizontal), wherein the third source/drain structure (Farbiz: 172) and fourth source/drain structure (Farbiz: 174) are disposed on opposite sides of the second gate structure (Farbiz: 172, 174 on opposite sides of 162), respectively.
Regarding claim 29, Farbiz in view of Chen further teaches the method of claim 28, wherein the first interconnect structure (Farbiz: Annotated fig. 1, 1st. portion) is configured at a first voltage (Farbiz: voltage of ground reference VSS; para. 0035) identical to a second voltage (Farbiz: voltage of VSS) provided to either the first gate structure (Farbiz: VSS provided to 160) or the second gate structure (Farbiz: VSS provided to 162).
Response to Arguments
Applicant’s arguments with respect to claims 11-15 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant's arguments filed on May 6th 2026 have been fully considered but they are not persuasive.
With respect to pages 8-12 of applicant’s response of Claims 1-9, 23-25, and 27-31 is rejected under 35 U.S.C.103.
Applicant submits "at no point does the Office Action demonstrate that Chen's metal wire 110 is directly above a particular inter-level dielectric (ILD) layers 302a, 302b (or etch stop layer 304a) that is directly above a source/drain region 408, much less demonstrate that the metal wire 110 is actually along at least one side of any of the layers 302a, 302b ( or etch stop layer 304a)".
The examiner respectfully disagrees.
Firstly, the OA is based on fig. 7C of Chen and a dielectric structure is obvious essential to fill the space between the connection structures in fig. 7C. Secondly, for more detail layer structure as shown in the Annotated fig. 4C based on fig. 7C structure, a dielectric structure (302a, 302b, 304a, 304b in the middle) is obvious to fill the space between the connection structures (110) and source/drain region (408) in fig. 7C. Based on the layers sequence, metal wire 110 is directly above a particular inter-level dielectric (ILD) layers 304b that is directly above source/drain region 408. And the metal wire 110 is actually along at least one side (top side) of the layers 304b. As result, given a broadest reasonable interpretation, Chen teaches all limitations of claims 1. Details of rejections are discussed above.
Applicant submits "the Office Action does not provide any passages from the cited reference alluding to having an interposing dielectric structure, for instance, directly between a common source/drain structure and an interconnect structure for electrical isolation.".
The examiner respectfully disagrees.
Firstly, the OA is based on fig. 7C of Chen and a dielectric structure is obvious essential to fill the space to provide electrical isolation between the connection structures in fig. 7C. Secondly, for more detail layer structure as shown in the Annotated fig. 4C based on fig. 7C structure, a dielectric structure (302a, 302b, 304a, 304b in the middle) is obvious to fill the space for electrical isolation as dielectric layers. In addition, the dielectric layer is essential in the device to avoid electrical shorts.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZHIJUN XU whose telephone number is (571)270-3447. The examiner can normally be reached Monday-Thursday 9am-5pm ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ZHIJUN XU/Examiner, Art Unit 2818
/BRIAN TURNER/Primary Examiner, Art Unit 2818
Prosecution Insights