DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on Nov. 10th 2025 has been entered.
Response to Amendment
The amendment filed on Nov. 4th, 2025 has been entered. Claims 1, 3-9, 11-15, 23, 25 and 27-31 remain pending in the application.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 3-5, 8-9, 23, 25, 27 and 30-31 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 20170317027), hereinafter Chen.
Regarding claim 1, Chen teaches a semiconductor device (Abstract), comprising:
a first source/drain structure (Annotated fig. 7C, left source/drain regions 704 labeled as 1st S/D; para. 0046) and a second source/drain structure (middle 704 labeled as 2nd S/D) of a first transistor (left transistor with gate structures 706 labeled as 1st gate; para. 0047);
a third source/drain structure (middle 704 labeled as 3rd S/D) and a fourth source/drain structure (right 704 labeled as 4th S/D) of a second transistor (right transistor with 706 labeled as 2nd gate), wherein the second source/drain structure (2nd S/D) and the third source/drain structure (3rd S/D) merge as a common source/drain structure (middle 704 labeled as 2nd/3rd S/D);
a first interconnect structure (first metal wire 110a or middle MEOL structures 708; para. 0048) extending along a first lateral direction (horizontal) and disposed above the common source/drain structure (110a disposed above 2nd/3rd S/D); and
Chen fails to explicitly teach a first dielectric structure interposed between and in contact with the first interconnect structure and the common source/drain structure, wherein the first dielectric structure is disposed above and fully overlays the common source/drain structure to electrically isolate the common source/drain structure from the first interconnect structure.
However, Chen teaches a first dielectric structure (Annotated fig. 4C based on fig. 7C structure, ILD layers 302a, 302b, etch stop layers 304a in the middle; para. 0031) interposed between (302a, 302b, 304a in the middle between 110 and source/drain regions 408; para. 0038, similar to between 110a and 704 of fig. 7C, Or 302a, 302b, 304a is diagonal direction between middle MEOL structure 402 and 408; para. 0038, similar to between 708 and 704 of fig. 7C) and in contact with the first interconnect structure (in contact with 110 as 110a of fig. 7C, Or 402 as 708 of fig. 7C) and the common source/drain structure (middle 408 as 704 of fig. 7C), wherein the first dielectric structure (302a, 302b, 304a in the middle) is disposed above and fully overlays the common source/drain structure (middle 408) to electrically isolate the common source/drain structure (middle 408) from the first interconnect structure (110 or 402).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to add the first dielectric structure.
Doing so would realize a dielectric structure to isolate the conductive elements in the device to avoid electrical shorts and minimizing parasitic capacitance.
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447
757
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Greyscale
(Annotated fig. 7C)
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165
377
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Greyscale
(Annotated fig. 4C)
Regarding claim 3, Chen further teaches the semiconductor device of claim 1, wherein the first interconnect structure (Annotated fig. 7C, in an alternative consideration, middle 708 on 2nd/3rd S/D) is configured at a floating voltage (middle 708 is not connected to an external voltage such as VSS or VDD as a voltage source or ground, and therefore meets BRI as capable of being operated with a floating voltage).
Regarding claim 4, Chen further teaches the semiconductor device of claim 1, further comprising:
a second interconnect structure (fig. 7C, metal strap 114; para. 0034) extending along a second lateral direction (lateral direction perpendicular to horizontal 110a direction) perpendicular to the first lateral direction (horizontal 110a direction); and
a via structure (first conductive via 112a; para. 0034) electrically connecting the first interconnect structure (110a) to the second interconnect structure (114).
Regarding claim 5, Chen further teaches the semiconductor device of claim 4, wherein the second interconnect structure (fig. 7C, 114) is configured at a power supply voltage or a fixed voltage (114 connect power rail 116 with supply voltage or ground voltage; para. 0020).
Regarding claim 8, Chen further teaches the semiconductor device of claim 1, further comprising:
a third interconnect structure (Annotated fig. 7C, left 110a above 1st S/D) extending along the first lateral direction (horizontal) and disposed above the first source/drain structure (110a disposed above 1st S/D); and
a fourth interconnect structure (right 110a above 4th S/D) extending along the first lateral direction (horizontal), and disposed above the fourth source/drain structure (110a disposed above 4th S/D).
Regarding claim 9, Chen further teaches the semiconductor device of claim 8, wherein the third interconnect structure (Annotated fig. 7C, left 101a) is electrically connected to the first source/drain structure (101a is electrically connected to 1st S/D) and the fourth interconnect structure (right 101a) is electrically connected to the fourth source/drain structure (101a is electrically connected to 4th S/D); wherein each of the third interconnect structure and fourth interconnect structure (101a) is electrically coupled to a fifth interconnect structure (101a is electrically connected to 116) that is configured as an output node or a power rail (power rail 116); and wherein the fifth interconnect structure (116) is formed on a front side (top side) of a substrate (semiconductor substrate 102; para. 0019) where the first and second transistors (left and right transistors of 706) are formed.
Regarding claim 23, Chen teaches a method (Abstract), comprising:
forming a first source/drain structure (Annotated fig. 7C, left source/drain regions 704 labeled as 1st S/D; para. 0046) and a second source/drain structure (middle 704 labeled as 2nd S/D) of a first transistor (left transistor with gate structures 706 labeled as 1st gate; para. 0047);
forming a third source/drain structure (middle 704 labeled as 3rd S/D) and a fourth source/drain structure (right 704 labeled as 4th S/D) of a second transistor (right transistor with 706 labeled as 2nd gate), wherein the second source/drain structure (2nd S/D) and the third source/drain structure (3rd S/D) merge as a common source/drain structure (middle 704 labeled as 2nd/3rd S/D);
forming a first interconnect structure (first metal wire 110a; para. 0048) extending along a first lateral direction (horizontal) and disposed above the common source/drain structure (110a disposed above 2nd/3rd S/D).
Chen fails to explicitly teach forming a first dielectric structure interposed between and in contact with the first interconnect structure and the common source/drain structure such that the first dielectric structure electrically isolates the common source/drain structure from the first interconnect structure.
However, Chen teaches forming a first dielectric structure (Annotated fig. 4C based on fig. 7C structure, ILD layers 302a, 302b, etch stop layers 304a in the middle; para. 0031) interposed between (302a, 302b, 304a in the middle between 110 and source/drain regions 408; para. 0038, similar to between 110a and 704 of fig. 7C) and in contact with the first interconnect structure (in contact with 110 as 110a of fig. 7C) and the common source/drain structure (middle 408 as 704 of fig. 7C) such that the first dielectric structure (302a, 302b, 304a in the middle) electrically isolates the common source/drain structure (middle 408) from the first interconnect structure (110).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to add the first dielectric structure.
Doing so would realize a dielectric structure to isolate the conductive elements in the device to avoid electrical shorts and minimizing parasitic capacitance.
Regarding claim 25, Chen further teaches the method of claim 23, further comprising:
forming a second interconnect structure (fig. 7C, metal strap 114; para. 0034) extending along a second lateral direction (lateral direction perpendicular to horizontal 110a direction) perpendicular to the first lateral direction (horizontal 110a direction);
forming a via structure (first conductive via 112a; para. 0034) electrically connecting the first interconnect structure (110a) to the second interconnect structure (114).
Regarding claim 27, Chen further teaches the method of claim 25, wherein the second interconnect structure (fig. 7C, 114) is configured at a power supply voltage or a fixed voltage (114 connect power rail 116 with supply voltage or ground voltage; para. 0020).
Regarding claim 30, Chen further teaches the method of claim 23, further comprising:
forming a third interconnect structure (Annotated fig. 7C, left 110a above 1st S/D) extending along the first lateral direction (horizontal) and disposed above the first source/drain structure (110a disposed above 1st S/D); and
forming a fourth interconnect structure (right 110a above 4th S/D) extending along the first lateral direction (horizontal), and disposed above the fourth source/drain structure (110a disposed above 4th S/D).
Regarding claim 31, Chen further teaches the method of claim 30, wherein the third interconnect structure (Annotated fig. 7C, left 101a) is electrically connected to the first source/drain structure (101a is electrically connected to 1st S/D) and the fourth interconnect structure (right 101a) is electrically connected to the fourth source/drain structure (101a is electrically connected to 4th S/D); wherein each of the third interconnect structure and the fourth interconnect structure (101a) is electrically coupled to a fifth interconnect structure (101a is electrically connected to 116) that is configured as an output node or a power rail (power rail 116); and wherein the fifth interconnect structure (116) is formed on a front side (top side) of a substrate (semiconductor substrate 102; para. 0019) where the first and second transistors (left and right transistors of 706) are formed.
Claims 1 and 6-7, 23 and 28-29 are rejected under 35 U.S.C. 103 as being unpatentable over Farbiz et al. (US 20190073440) in view of Chen.
Regarding claim 1, Farbiz teaches a semiconductor device (Abstract), comprising:
a first source/drain structure (fig. 1, n-type regions 170; para. 0031) and a second source/drain structure (n-type regions 172; para. 0031) of a first transistor (transistor with transistor gate stripes 160; para. 0031);
a third source/drain structure (172) and a fourth source/drain structure (n-type regions 174; para. 0031) of a second transistor (transistor with transistor gate stripes 162; para. 0031), wherein the second source/drain structure (172) and the third source/drain structure (172) merge as a common source/drain structure (172 is the common source/drain for both gate transistors);
a first interconnect structure (Annotated fig. 1, 1st. portion with red label) extending along a first lateral direction (horizontal) and disposed above the common source/drain structure (1st. portion disposed above 172).
Farbiz fails to explicitly teach a first dielectric structure interposed between and in contact with the first interconnect structure and the common source/drain structure.
However, Chen teaches a first dielectric structure (Chen: fig. 3, ILD layer 302a, 302b, etch stop layers 304a in the middle; para. 0031, 0033) interposed between (Chen: diagonal direction between power rail 116 and active area 104; para. 0025) and in contact with the first interconnect structure (Chen: in contact with 116, similar to 1st. portion of Farbiz) and the common source/drain structure (Chen: 104, similar to 172 of Farbiz), wherein the first dielectric structure (Chen: 302a, 302b, 304a) is disposed above and fully overlays (Chen: 302a, 302b, 304a extends beyond edges of 106/104, so meets BRI of 'fully overlays) the common source/drain structure (Chen: 104) to electrically isolate the common source/drain structure (Chen: 104) from the first interconnect structure (Chen: 116).
Chen and Farbiz are considered to be analogous to the claimed invention because they are in the same field of interconnection structures of transistor devices.
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to add the first dielectric structure as taught by Chen.
Doing so would realize a dielectric structure to isolate the conductive elements in the device to avoid electrical shorts and minimizing parasitic capacitance.
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320
394
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Greyscale
(Annotated fig. 1)
Regarding claim 6, Farbiz in view of Chen further teaches the semiconductor device of claim 1, further comprising:
a first gate structure (Farbiz: fig. 1, 160) of the first transistor (Farbiz: transistor with 160) that extends along the first lateral direction (Farbiz: 160 extends along horizontal), wherein the first source/drain structure (Farbiz: 170) and second source/drain structure (Farbiz: 172) are disposed on opposite sides of the first gate structure (Farbiz: 170, 172 on opposite sides of 160), respectively; and
a second gate structure (Farbiz: 162) of the second transistor (Farbiz: transistor with 162) that extends along the first lateral direction (Farbiz: 162 extends along horizontal), wherein the third source/drain structure (Farbiz: 172) and fourth source/drain structure (Farbiz: 174) are disposed on opposite sides of the second gate structure (Farbiz: 172, 174 on opposite sides of 162), respectively.
Regarding claim 7, Farbiz in view of Chen further teaches the semiconductor device of claim 6, wherein the first interconnect structure (Farbiz: Annotated fig. 1, 1st. portion) is configured at a first voltage (Farbiz: voltage of ground reference VSS; para. 0035) identical to a second voltage (Farbiz: voltage of VSS) provided to either the first gate structure (Farbiz: VSS provided to 160) or the second gate structure (Farbiz: VSS provided to 162).
Regarding claim 23, Farbiz teaches a method (Abstract), comprising:
forming a first source/drain structure (fig. 1, n-type regions 170; para. 0031) and a second source/drain structure (n-type regions 172; para. 0031) of a first transistor (transistor with transistor gate stripes 160; para. 0031);
forming a third source/drain structure (172) and a fourth source/drain structure (n-type regions 174; para. 0031) of a second transistor (transistor with transistor gate stripes 162; para. 0031), wherein the second source/drain structure (172) and the third source/drain structure (172) merge as a common source/drain structure (172 is the common source/drain for both gate transistors);
forming a first interconnect structure (Annotated fig. 1, 1st. portion with red label) extending along a first lateral direction (horizontal) and disposed above the common source/drain structure (1st. portion disposed above 172).
Farbiz fails to explicitly teach a first dielectric structure interposed between and in contact with the first interconnect structure and the common source/drain structure.
However, Chen teaches a first dielectric structure (Chen: fig. 3 and Annotated fig. 4C, ILD layer 302a, 302b, etch stop layers 304a in the middle without middle first metal wire 110a; para. 0031, 0033) interposed between (Chen: diagonal direction between power rail 116 and active area 104; para. 0025) and in contact with the first interconnect structure (Chen: in contact with 116, similar to 1st. portion of Farbiz) and the common source/drain structure (Chen: 104, similar to 172 of Farbiz), wherein the first dielectric structure (Chen: 302a, 302b, 304a is fully overlays without middle110a) is disposed above and fully overlays the common source/drain structure (Chen: 104) to electrically isolate the common source/drain structure (Chen: 104) from the first interconnect structure (Chen: 116).
Chen and Farbiz are considered to be analogous to the claimed invention because they are in the same field of interconnection structures of transistor devices.
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to add the first dielectric structure as taught by Chen.
Doing so would realize a dielectric structure to isolate the conductive elements in the device to avoid electrical shorts and minimizing parasitic capacitance.
Regarding claim 28, Farbiz in view of Chen further teaches the method of claim 23, further comprising:
forming a first gate structure (Farbiz: fig. 1, 160) of the first transistor (Farbiz: transistor with 160) that extends along the first lateral direction (Farbiz: 160 extends along horizontal), wherein the first source/drain structure (Farbiz: 170) and second source/drain structure (Farbiz: 172) are disposed on opposite sides of the first gate structure (Farbiz: 170, 172 on opposite sides of 160), respectively; and
forming a second gate structure (Farbiz: 162) of the second transistor (Farbiz: transistor with 162) that extends along the first lateral direction (Farbiz: 162 extends along horizontal), wherein the third source/drain structure (Farbiz: 172) and fourth source/drain structure (Farbiz: 174) are disposed on opposite sides of the second gate structure (Farbiz: 172, 174 on opposite sides of 162), respectively.
Regarding claim 29, Farbiz in view of Chen further teaches the method of claim 28, wherein the first interconnect structure (Farbiz: Annotated fig. 1, 1st. portion) is configured at a first voltage (Farbiz: voltage of ground reference VSS; para. 0035) identical to a second voltage (Farbiz: voltage of VSS) provided to either the first gate structure (Farbiz: VSS provided to 160) or the second gate structure (Farbiz: VSS provided to 162).
Claims 11-15 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 20190237542 as Chen2), in view of Chen.
Regarding claim 11, Chen2 teaches a semiconductor device (Abstract), comprising:
an active region (fig. 1, active region 110; para. 0034) formed on a front side (top side) of a substrate (substrate of the chip; para. 0034) and extending along a first lateral direction (horizontal or lateral direction 150; para. 0034);
a first gate structure (fig. 4A, gate 314; para. 0076) extending along a second lateral direction (314 extending along lateral direction 465; para. 0074) and traversing across the active region (314 traversing across active region of S/D);
a second gate structure (gate 416; para. 0076) extending along the second lateral direction (416 extending along 465) and traversing across the active region (416 traversing across active region of S/D);
a first interconnect structure (gate 440, gate contact 442 and metal interconnect 445 between 314 and 416; para. 0075) extending along the second lateral direction (440 extending along 465) and disposed between the first gate structure (314) and the second gate structure (416),
a first portion of the active region (middle two drain regions D; para. 0040) laterally interposed between the first and second gate structures (314 and 416).
Chen2 fails to explicitly teach a first dielectric structure vertically interposed between and in contact with the first interconnect structure and a first portion of the active region laterally interposed between the first and second gate structures;
wherein the first dielectric structure is disposed above and fully overlays the first portion of the active region to electrically isolate the first interconnect structure from the first portion of the active region.
However, Chen teaches a first dielectric structure (Chen: Annotated fig. 4C based on fig. 7C structure, ILD layers 302a, 302b, etch stop layers 304a in the middle; para. 0031) vertically interposed between and in contact with the first interconnect structure (Chen: 302a, 302b, 304a in the middle between and in contact with first metal wire 110; para. 0034, similar to 445 of Chen2) and a first portion of the active region (Chen: middle source/drain regions 408; para. 0037, similar to one of middle two D of Chen2) laterally interposed between the first and second gate structures (Chen: middle region laterally between gate structure 206; para. 0038, similar to 314 and 416 of Chen2);
wherein the first dielectric structure (Chen: 302a, 302b, 304a in the middle) is disposed above and fully overlays the first portion of the active region (Chen: middle 408, similar to one of middle two D of Chen2) to electrically isolate the first interconnect structure (Chen: 110) from the first portion of the active region (Chen: middle 408).
Chen and Chen2 are considered to be analogous to the claimed invention because they are in the same field of interconnection structures of transistor devices.
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to add the first dielectric structure as taught by Chen.
Doing so would realize a dielectric structure to isolate the conductive elements in the device to avoid electrical shorts and minimizing parasitic capacitance.
Regarding claim 12, Chen2 in view of Chen further teaches the semiconductor device of claim 11, further comprising:
a second interconnect structure (Chen2: fig. 4A, structure of source contact 320; para. 0059) extending along the second lateral direction (Chen2: 320 extending along 465) and disposed above a second portion (Chen2: fig. 4B, source region under source contact 320; para. 0059) of the active region on the front side (top side), wherein the second portion of the active region (Chen2: source region under 320) is disposed opposite the first gate structure (Chen2: 320 is opposite side of 314) from the first portion of the active region (Chen2: drain regions under 318 and 420) along the first lateral direction (horizontal); and
a third interconnect structure (Chen2: fig. 4A, structure of source contact 422; para. 0073) extending along the second lateral direction (Chen2: 422 extending along 465) and disposed above a third portion (Chen2: fig. 4B, source region under source contact 422; para. 0073) of the active region on the front side (top side), wherein the third portion (Chen2: source region under 422) of the active region is disposed opposite the second gate structure (Chen2: 422 is opposite side of 416) from the first portion of the active region (Chen2: drain regions under 318 and 420) along the first lateral direction (horizontal).
Regarding claim 13, Chen2 in view of Chen further teaches the semiconductor device of claim 12, wherein the second interconnect structure (Chen2: fig. 4B, 320) is in electrical contact with the second portion of the active region (Chen2: 320 is in electrical contact with source region under 320), and the third interconnect structure (Chen2: 422) is in electrical contact with the third portion of the active region (Chen2: 422 is in electrical contact with source region under 422).
Regarding claim 14, Chen2 in view of Chen further teaches the semiconductor device of claim 13, wherein each of the second interconnect structure (Chen2: fig. 4A, 320) and the third interconnect structure (Chen2: 422) is electrically coupled to a respective fourth interconnect structure (Chen2: common power rail 450; para. 0075) formed on the front side (top side).
Regarding claim 15, Chen2 in view of Chen further teaches the semiconductor device of claim 14, wherein the fourth interconnect structure (Chen2: fig. 4A, 450) is configured as an output node or a power rail (Chen2: common power rail; para. 0075).
Response to Arguments
Applicant's arguments filed on Nov. 4th, 2025 have been fully considered but they are not persuasive.
With respect to pages 8-11 of applicant’s response of claim 1 is rejected under 35 U.S.C.103.
Applicant submits "Chen is entirely silent regarding any dielectric structure interposing the source/drain region 408 and the MEOL structure 402, much less fully overlaying the source/drain region 408 to electrically isolate the source/drain region 408 from the MEOL structure 402".
The examiner respectfully disagrees.
As cited in the Annotated fig. 4C based on fig. 7C structure, a dielectric structure is obvious to fill the space between the connection structures in fig. 7C. Chen teaches a first dielectric structure (302a, 302b, 304a in the middle) interposed between and in contact with the first interconnect structure (middle 110) and the common source/drain structure (middle 408), wherein the first dielectric structure (302a, 302b, 304a in the middle) is disposed above and fully overlays the common source/drain structure (middle 408) to electrically isolate the common source/drain structure (middle 408) from the first interconnect structure (middle 110). In the alternative consideration for claim 3, Chen still teaches a first dielectric structure (302a, 302b, 304a in the middle) interposed between (in diagonal direction) and in contact with the first interconnect structure (middle 402) and the common source/drain structure (middle 408), wherein the first dielectric structure (302a, 302b, 304a in the middle) is disposed above and fully overlays the common source/drain structure (middle 408) to electrically isolate (short from side) the common source/drain structure (middle 408) from the first interconnect structure (middle 402). As result, given a broadest reasonable interpretation, Chen teaches all limitations of claims 1. Details of rejections are discussed above.
With respect to pages 11-13 of applicant’s response of claim 11 is rejected under 35 U.S.C.103.
Applicant submits "Chen merely provides ILD layers 302 that are next to MEOL structure 402 arranged over a source/drain structure 408. Nowhere does Chen consider electrically isolating the MEOL structure 402 from the source/drain structure 408 much less having any dielectric structure or ILD layer that fully overlays the first portion of the active region to electrically isolate the first interconnect structure from the first portion of the active region".
The examiner respectfully disagrees.
As cited in the Annotated fig. 4C, a dielectric structure is obvious to fill the space between the connection structures of fig. 4B of Chen2. Chen teaches the first dielectric structure (302a, 302b, 304a in the middle) is disposed above and fully overlays the first portion of the active region (middle 408, similar to one of middle two D of Chen2) to electrically isolate the first interconnect structure (110, similar to 445 part of Chen2 and dielectric structure also fill the space to electrically isolate 440 from D) from the first portion of the active region (middle 408). The middle MEOL structure 402 is similar to drain contact 318 or 420 of Chen2 and is different from 440 of Chen2. As result, given a broadest reasonable interpretation, Chen2 in view of Chen teaches all limitations of claims 11. Details of rejections are discussed above.
Conclusion
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/ZHIJUN XU/Examiner, Art Unit 2818
/BRIAN TURNER/Examiner, Art Unit 2818