DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Remarks
The 01/07/2026 amendments of claims 1, 8-17 and 19-20 have been noted and entered.
Response to Arguments
Applicant’s arguments, see Remarks pages 8-9, filed 01/07/2026, with respect to the rejection(s) of claim(s) 1-20 under 35 U.S.C. 103 have been fully considered and are persuasive in light of the newly added amendments. However, upon further consideration, a new ground(s) of rejection is made in view of Hsiao et al, US 11121315 B2 (Hsiao).
New Grounds for Rejection
New grounds for rejection, prior art reference Hsiao et al, US 11121315 B2 (Hsiao) appears below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over
Hsiao et al, US 11121315 B2 (Hsiao) in view of Rajenda Singh and Richard K. Ulrich 1999 Electrochem. Soc. Interface 8 26, DOI 10.1149/2.F06992IF (Singh) in further view of Standaert et al, US 20220359814 A1 (Standaert).
Regarding claim 1; Hsiao teaches a semiconductor device (100), comprising: a semiconductor substrate (202); and a memory cell (107) on the semiconductor substrate (202), wherein the memory cell (107) comprises: a bottom contact (125), a memory material (123) on the bottom contact (125), a top contact (111) on the memory material (123), a first electrical isolation structure (115) laterally surrounding the top contact, and a second electrical isolation structure (117), distinct from the first electrical isolation structure, laterally surrounding the memory material (123) and in direct contact with the memory material (123); wherein a region between the memory cell (Memory Cell – see annotated Fig (1) of Hsiao shared in this OA for convenience) and an adjacent memory cell (Memory Cell – see annotated Fig (1) of Hsiao shared in this OA for convenience) is filled with one or more insulating materials ((113) and (117)), and wherein any line segment between the memory material (123) of the memory cell (Memory Cell – see annotated Fig (1) of Hsiao shared in this OA for convenience) and a memory material (123) of the adjacent memory cell (Memory Cell – see annotated Fig (1) of Hsiao shared in this OA for convenience) intersects only insulating materials having a dielectric constant greater than 2.5 (the path between the memory material of the two adjacent memory cells intersects only the two dielectric materials (113) and (117). The composition of both of them is described in the specification of Hsiao ad follows: “The dielectric filling layer 113 can be a dielectric material, such as silicon dioxide (SiO .sub.2 ), or similar materials.” And “Action 2223 is to form the second sidewall spacer 117. This may include depositing a spacer material layer 1101 as shown in FIG. 11 and then performing spacer etching to form the second sidewall spacer 117 as shown in FIG. 12.” And “The second spacer layer 1101 may be the same material as the first sidewall spacer 115 or a different material. In some embodiments, the second spacer layer 1101 is silicon oxynitride (SiON), and the first sidewall spacer 115 is silicon nitride (SiN)”), wherein the second electrical isolation structure (117) is disposed between the first electrical isolation (115) structure and the one or more insulating materials (113).
Hsiao does not teach that the dielectric constant of the dielectric materials between the memory cells is greater than 2.5. However, Singh teaches that the dielectric constant of the dielectric materials between the memory cells is greater than 2.5 (see the sections about High and Low Dielectric Constant materials disclosed in Singh). Hsiao and Singh are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Hsiao by making the dielectric constant of the dielectric material between the memory cells be greater than 2.5 as disclosed in Singh to improve the electrical insulation of the memory cells leading to a more reliable device.
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Hsiao in view of Singh teaches all the above disclosed subject matter.
However, Hsiao in view of Singh does not teach the second electrical isolation structure surrounding the bottom electrode.
Standaert teaches the second electrical isolation structure (90) surrounding the bottom electrode (30). Hsiao in view of Singh and Standaert are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Hsiao in view of Singh by making the second isolation structure surround the bottom electrode as disclosed in Standaert to increase the isolation of the memory cell and its contacts to reduce the chance of destroying the information stored on the memory cell by mistake.
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Regarding claim 2; Hsiao in view of Singh in further view of Standaert teaches all the limitations claimed in claim 1.
Further, Hsiao teaches wherein the first electrical isolation structure (115) has a first material (see the specifications of Hsiao: “Suitable materials for the first sidewall spacer 115 include but are not limited to oxygen Silicon, silicon nitride, silicon oxynitride, or similar materials, etc.”), wherein the second electrical isolation structure (117) has a second material, and the first and second materials are different (see the specifications of Hsiao: “In some embodiments, the second spacer layer 1101 is silicon oxynitride (SiON), and the first sidewall spacer 115 is silicon nitride (SiN). As shown in the cross-sectional view 1200 of FIG. 12, the second spacer layer 1101 is etched to form the second sidewall spacer 117.”).
Regarding claim 3; Hsiao in view of Singh in further view of Standaert teaches all the limitations claimed in claim 1.
Further, Hsiao teaches wherein the first electrical isolation structure (115) has a first material (see the specifications of Hsiao: “Suitable materials for the first sidewall spacer 115 include but are not limited to oxygen Silicon, silicon nitride, silicon oxynitride, or similar materials, etc.”), wherein the second electrical isolation structure (117) has a second material, and the first and second materials are the same (see the specifications of Hsiao: “In some embodiments, the second spacer layer 1101 is silicon oxynitride (SiON), and the first sidewall spacer 115 is silicon nitride (SiN). As shown in the cross-sectional view 1200 of FIG. 12, the second spacer layer 1101 is etched to form the second sidewall spacer 117.”).
Regarding claim 4; Hsiao in view of Singh in further view of Standaert teaches all the limitations claimed in claim 1.
Further, Hsiao teaches wherein the memory material (123) comprises a ferroelectric material (see specifications of Hsiao: “The memory units 107 and 153 can be any type of resistance switching random access memory. Examples of resistance switching random access memory include but are not limited to oxygen displacement memory (oxygen random access memory (OxRAM)), conductive bridging random access memory (CBRAM)), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM)”).
Regarding claim 5; Hsiao in view of Singh in further view of Standaert teaches all the limitations claimed in claim 1.
Further, Hsiao wherein the second electrical isolation structure (117) extends substantially to a point along the first electrical isolation structure (115) which is farthest from the semiconductor substrate (202).
Regarding claim 6; Hsiao in view of Singh in further view of Standaert teaches all the limitations claimed in claim 1.
Further, Hsiao teaches wherein the second electrical isolation structure (117) extends substantially to a point along the first electrical isolation structure (115) which is nearest to the semiconductor substrate (202).
Regarding claim 7; Hsiao in view of Singh in further view of Standaert teaches all the limitations claimed in claim 1.
Further, Hsiao teaches wherein the second electrical isolation structure (117) extends substantially to a point along the first electrical isolation structure (115) which is about half way between points of the first electrical isolation structure (115) nearest to and farthest from the semiconductor substrate (202).
Regarding claim 8; Hsiao teaches a semiconductor device (100), comprising: a semiconductor substrate (202); and a memory cell (107) on the semiconductor substrate (202), wherein the memory cell (107) comprises: a bottom contact (125), a memory material (123) on the bottom contact (125), a top contact (111) on the memory material (123), and a first electrical isolation structure (115) laterally surrounding the memory material (123), and at least a portion of the top contact (111); wherein a region between the memory cell (Memory Cell – see annotated Fig (1) of Hsiao shared in this OA for convenience) and an adjacent memory cell (Memory Cell – see annotated Fig (1) of Hsiao shared in this OA for convenience) is filled with one or more insulating materials ((113) and (117)), and wherein any line segment between the memory material (123) of the memory cell (Memory Cell – see annotated Fig (1) of Hsiao shared in this OA for convenience) and a memory material (123) of the adjacent memory cell (Memory Cell – see annotated Fig (1) of Hsiao shared in this OA for convenience) intersects only insulating materials having a dielectric constant greater than 2.5 (the path between the memory material of the two adjacent memory cells intersects only the two dielectric materials (113) and (117). The composition of both of them is described in the specification of Hsiao ad follows: “The dielectric filling layer 113 can be a dielectric material, such as silicon dioxide (SiO .sub.2 ), or similar materials.” And “Action 2223 is to form the second sidewall spacer 117. This may include depositing a spacer material layer 1101 as shown in FIG. 11 and then performing spacer etching to form the second sidewall spacer 117 as shown in FIG. 12.” And “The second spacer layer 1101 may be the same material as the first sidewall spacer 115 or a different material. In some embodiments, the second spacer layer 1101 is silicon oxynitride (SiON), and the first sidewall spacer 115 is silicon nitride (SiN)”), and a second electrical isolation structure (117) laterally surrounding at least a portion of the top contact (111), wherein the second electrical isolation structure (117) is disposed between the first electrical isolation structure (115) and the one or more insulating materials (113).
Hsiao does not teach that the dielectric constant of the dielectric materials between the memory cells is greater than 2.5.
However, Singh teaches that the dielectric constant of the dielectric materials between the memory cells is greater than 2.5 (see the sections about High and Low Dielectric Constant materials disclosed in Singh). Hsiao and Singh are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Hsiao by making the dielectric constant of the dielectric material between the memory cells be greater than 2.5 as disclosed in Singh to improve the electrical insulation of the memory cells leading to a more reliable device.
Hsiao in view of Singh teaches all the above disclosed subject matter.
However, Hsiao in view of Singh does not teach the first electrical isolation material laterally surrounding the bottom contact wherein the first electrical isolation structure is in direct contact with the memory material.
Standaert teaches the first electrical isolation structure (77) laterally surrounding the bottom contact (30) wherein the first electrical isolation structure (77) is in direct contact with the memory material (41). Hsiao in view of Singh and Standaert are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Hsiao in view of Singh by making the second isolation structure surround the bottom electrode as disclosed in Standaert to increase the isolation of the memory cell and its contacts to reduce the chance of destroying the information stored on the memory cell by mistake.
Regarding claim 9; Hsiao in view of Singh in further view of Standaert teaches all the limitations claimed in claim 8.
Further, Hsiao teaches wherein the first electrical isolation structure (115) has a first material(see the specifications of Hsiao: “Suitable materials for the first sidewall spacer 115 include but are not limited to oxygen Silicon, silicon nitride, silicon oxynitride, or similar materials, etc.”), wherein the second electrical isolation structure (117) has a second material, and the first and second materials are different (see the specifications of Hsiao: “In some embodiments, the second spacer layer 1101 is silicon oxynitride (SiON), and the first sidewall spacer 115 is silicon nitride (SiN). As shown in the cross-sectional view 1200 of FIG. 12, the second spacer layer 1101 is etched to form the second sidewall spacer 117.”).
Regarding claim 10; Hsiao in view of Singh in further view of Standaert teaches all the limitations claimed in claim 8.
Further, Hsiao teaches wherein the first electrical isolation structure (115) has a first material (see the specifications of Hsiao: “Suitable materials for the first sidewall spacer 115 include but are not limited to oxygen Silicon, silicon nitride, silicon oxynitride, or similar materials, etc.”), wherein the second electrical isolation structure (117) has a second material, and the first and second materials are the same (see the specifications of Hsiao: “In some embodiments, the second spacer layer 1101 is silicon oxynitride (SiON), and the first sidewall spacer 115 is silicon nitride (SiN). As shown in the cross-sectional view 1200 of FIG. 12, the second spacer layer 1101 is etched to form the second sidewall spacer 117.”).
Regarding claim 11; Hsiao in view of Singh in further view of Standaert teaches all the limitations claimed in claim 8.
Further, Hsiao teaches wherein the memory material (123) comprises a ferroelectric material (see specifications of Hsiao: “The memory units 107 and 153 can be any type of resistance switching random access memory. Examples of resistance switching random access memory include but are not limited to oxygen displacement memory (oxygen random access memory (OxRAM)), conductive bridging random access memory (CBRAM)), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM)”).
Regarding claim 12; Hsiao in view of Singh in further view of Standaert teaches all the limitations claimed in claim 8.
Further, Hsiao teaches wherein the first electrical isolation structure (115) extends substantially to a point along the second electrical isolation structure (117) which is farthest from the semiconductor substrate (202).
Regarding claim 13; Hsiao in view of Singh in further view of Standaert teaches all the limitations claimed in claim 8.
Further, Hsiao teaches wherein the first electrical isolation structure (115) extends substantially to a point along the second electrical isolation structure (117) which is nearest to the semiconductor substrate (202).
Regarding claim 14; Hsiao in view of Singh in further view of Standaert teaches all the limitations claimed in claim 8.
Further, Hsiao teaches wherein the first electrical isolation structure (115) extends substantially to a point along the second electrical isolation structure (117) which is about half way between points of the second electrical isolation structure (117) nearest to and farthest from the semiconductor substrate (202).
Regarding claim 15; Hsiao teaches a method of making a semiconductor device (100), the method comprising: providing a semiconductor substrate (202); and forming a memory cell (107) on the semiconductor substrate (202), wherein forming the memory cell (107) comprises: forming a bottom contact (125), forming a memory material (123) on the bottom contact (125), forming a top contact (111) on the memory material (123), and forming a first electrical isolation structure (115) laterally surrounding the memory material (123), and at least a portion of the top contact (111), wherein the first electrical isolation structure (115) extends from the semiconductor substrate (202) by a distance greater than a combined thickness of the memory material (123) and the top contact (111); wherein a region between the memory cell (Memory Cell – see annotated Fig (1) of Hsiao shared in this OA for convenience) and an adjacent memory cell (Memory Cell – see annotated Fig (1) of Hsiao shared in this OA for convenience) is filled with one or more insulating materials ((113) and (117)), and wherein any line segment between the memory material (123) of the memory cell (Memory Cell – see annotated Fig (1) of Hsiao shared in this OA for convenience) and a memory material (123) of the adjacent memory cell (Memory Cell – see annotated Fig (1) of Hsiao shared in this OA for convenience) intersects only insulating materials having a dielectric constant greater than 2.5 (the path between the memory material of the two adjacent memory cells intersects only the two dielectric materials (113) and (117). The composition of both of them is described in the specification of Hsiao ad follows: “The dielectric filling layer 113 can be a dielectric material, such as silicon dioxide (SiO .sub.2 ), or similar materials.” And “Action 2223 is to form the second sidewall spacer 117. This may include depositing a spacer material layer 1101 as shown in FIG. 11 and then performing spacer etching to form the second sidewall spacer 117 as shown in FIG. 12.” And “The second spacer layer 1101 may be the same material as the first sidewall spacer 115 or a different material. In some embodiments, the second spacer layer 1101 is silicon oxynitride (SiON), and the first sidewall spacer 115 is silicon nitride (SiN)”), and forming a second electrical isolation structure (117) laterally surrounding at least a portion of the top contact (111), wherein the second electrical isolation structure (117) is disposed between the first electrical isolation structure (115) and the one or more insulating materials (113).
Hsiao does not teach that the dielectric constant of the dielectric materials between the memory cells is greater than 2.5.
However, Singh teaches that the dielectric constant of the dielectric materials between the memory cells is greater than 2.5 (see the sections about High and Low Dielectric Constant materials disclosed in Singh). Hsiao and Singh are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Hsiao by making the dielectric constant of the dielectric material between the memory cells be greater than 2.5 as disclosed in Singh to improve the electrical insulation of the memory cells leading to a more reliable device.
Hsiao in view of Singh teaches all the above disclosed subject matter.
However, Hsiao in view of Singh does not teach the first isolation material surrounding the bottom electrode wherein the first electrical isolation structure is in direct contact with the memory material.
Standaert teaches the first isolation structure (77) surrounding the bottom electrode (30) wherein the first electrical isolation structure (77) is in direct contact with the memory material (41). Hsiao in view of Singh and Standaert are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Hsiao in view of Singh by making the second isolation structure surround the bottom electrode as disclosed in Standaert to increase the isolation of the memory cell and its contacts to reduce the chance of destroying the information stored on the memory cell by mistake.
Regarding claim 16; Hsiao in view of Singh in further view of Standaert teaches all the limitations claimed in claim 15.
Further, Hsiao teaches wherein the first electrical isolation structure (115) has a first material(see the specifications of Hsiao: “Suitable materials for the first sidewall spacer 115 include but are not limited to oxygen Silicon, silicon nitride, silicon oxynitride, or similar materials, etc.”), wherein the second electrical isolation structure (117) has a second material, and the first and second materials are different (see the specifications of Hsiao: “In some embodiments, the second spacer layer 1101 is silicon oxynitride (SiON), and the first sidewall spacer 115 is silicon nitride (SiN). As shown in the cross-sectional view 1200 of FIG. 12, the second spacer layer 1101 is etched to form the second sidewall spacer 117.”).
Regarding claim 17; Hsiao in view of Singh in further view of Standaert teaches all the limitations claimed in claim 15.
Further, Hsiao teaches wherein the first electrical isolation structure (115) has a first material (see the specifications of Hsiao: “Suitable materials for the first sidewall spacer 115 include but are not limited to oxygen Silicon, silicon nitride, silicon oxynitride, or similar materials, etc.”), wherein the second electrical isolation structure (117) has a second material, and the first and second materials are the same (see the specifications of Hsiao: “In some embodiments, the second spacer layer 1101 is silicon oxynitride (SiON), and the first sidewall spacer 115 is silicon nitride (SiN). As shown in the cross-sectional view 1200 of FIG. 12, the second spacer layer 1101 is etched to form the second sidewall spacer 117.”).
Regarding claim 18; Hsiao in view of Singh in further view of Standaert teaches all the limitations claimed in claim 15.
Further, Hsiao teaches wherein the memory material (123) comprises a ferroelectric material (see specifications of Hsiao: “The memory units 107 and 153 can be any type of resistance switching random access memory. Examples of resistance switching random access memory include but are not limited to oxygen displacement memory (oxygen random access memory (OxRAM)), conductive bridging random access memory (CBRAM)), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM)”).
Regarding claim 19; Hsiao in view of Singh in further view of Standaert teaches all the limitations claimed in claim 15.
Further, Hsiao teaches wherein the first electrical isolation structure (115) extends substantially to a point along the second electrical isolation structure (117) which is farthest from the semiconductor substrate (202).
Regarding claim 20; Hsiao in view of Singh in further view of Standaert teaches all the limitations claimed in claim 15.
Further, Hsiao teaches wherein the first electrical isolation structure (115) extends substantially to a point along the second electrical isolation structure (117) which is about half way between points of the second electrical isolation structure (117) nearest to and farthest from the semiconductor substrate (202).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Moataz Khalifa whose telephone number is (703)756-1770. The examiner can normally be reached Monday - Friday (8:30 am - 5:00).
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/MOATAZ KHALIFA/Examiner, Art Unit 2815
/MONICA D HARRISON/Primary Examiner, Art Unit 2815